ANALOG DEVICES AD8197B Service Manual

A

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4:1 HDMI/DVI Switch with Equalization

FEATURES

4 inputs, 1 output HDMI™/DVI links Enables HDMI 1.3-compliant receiver Pin-to-pin compatible with the AD8191

4 TMDS® channels per link

Supports 250 Mbps to 2.25 Gbps data rates Supports 25 MHz to 225 MHz pixel clocks Equalized inputs for operation with long HDMI c

(20 meters at 2.25 Gbps) Fully buffered unidirectional inputs/outputs Globally switchable, 50 Ω on-chip terminations Pre-emphasized outputs Low added jitter Single-supply operation (3.3 V)

4 auxiliary channels per link

Bidirectional unbuffered inputs/outputs Flexible supply operation (3.3 V to 5 V) HDCP standard compatible Allows switching of DDC bus and 2 additional signals

Multiple channel bundling modes

1× (4:1) HDMI/DVI link switch (default) 2× (8:1) TMDS channel and auxiliary signal switch 1× (16:1) TMDS channel and auxiliary signal switch

Output disable feature

Reduced power dissipation Removable output termination

Allows building of larger arrays Two AD8197s support HDMI/DVI dual-link Standards compatible: HDMI receiver, HDCP, DVI

2

Serial (I

C® slave) and parallel control interface

100-lead, 14 mm × 14 mm LQFP, Pb-free package

APPLICATIONS

Multiple input displays Projectors A/V receivers Set-top boxes Advanced television (HDTV) sets

GENERAL DESCRIPTION

The AD8197 is an HDMI/DVI switch featuring equalized TMDS inputs and pre-emphasized TMDS outputs, ideal for systems with long cable runs. Outputs can be set to a high impedance state to reduce the power dissipation and/or to allow the construction of larger arrays using the wire-OR technique. Flexible channel bundling modes (for both the TMDS channels and the auxiliary signals) allow the AD8197 to be configured as a

ables

AD8197

FUNCTIONAL BLOCK DIAGRAM

PP_CH[1:0]

PP_OTO

PP_OCL

PP_EQ

PARALLEL

SERIAL

I2C_SDA I2C_SCL

I2C_ADDR[2:0]

VTTI

IP_A[3:0]

IN_A[3:0]

IP_B[3:0] IN_B[3:0]

IP_C[3:0] IN_C[3:0]

IP_D[3:0] IN_D[3:0]

VTTI AUX_A[3:0] AUX_B[3:0] AUX_C[3:0] AUX_D[3:0]

3

+

– +

–

2 2

CONFI G

INTERFACE

4

HIGH SPEED BUFFERED

4

LOW SPEE D UNBUFFERED

TYPICAL APPLICATION

MEDIA CENTER

SET-TOP BOX

Figure 2. Typical HDTV Application

4:1 single HDMI/DVI link switch, a dual 8:1 switch, or a single 16:1 switch.

The AD8197 is provided in a 100-lead LQFP, Pb-free, surfacem

ount package, specified to operate over the −40°C to +85°C

temperature range.

PRODUCT HIGHLIGHTS

1. Supports data rates up to 2.25 Gbps, enabling 1080p deep

color (12-bit color) HDMI formats, and greater than UXGA (1600 × 1200) DVI resolutions.

nput cable equalizer enables use of long cables at the input

2. I

(more than 20 meters of 24 AWG cable at 2.25 Gbps).

3. A

uxiliary switch routes a DDC bus and two additional signals

for a single-chip, HDMI 1.3 receive-compliant solution.

RESET

PP_EN

PP_PRE[1:0]

CONTRO L

LOGIC

SWITCH

CORE

EQ

SWITCH

CORE

BIDIRECTIO NAL

Figure 1.

HDTV SET

HDMI

RECEIVE R

AD8197

4

PE

4

GAME CONSOL E

DVD PLAYER

AVCC DVCC AMUXVCC AVEE DVEE

VTTO

+

OP[3:0] ON[3:0]

–

UX_COM[3:0]

6471-001

04:20

06471-002

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

AD8197

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REVISION HISTORY

1/07—Revision 0: Initial Version

Rev. 0 | Page 2 of 32

AD8197

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SPECIFICATIONS

TA = 27°C, AVCC = 3.3 V, VTTI = 3.3 V, VTTO = 3.3 V, DVCC = 3.3 V, AMUXVCC = 5 V, AVEE = 0 V, DVEE = 0 V, differential input swing = 1000 mV, TMDS outputs terminated with external 50 Ω resistors to 3.3 V, unless otherwise noted.

Table 1.

Parameter Conditions/Comments Min Typ Max Unit

DYNAMIC PERFORMANCE

Maximum Data Rate (DR) per Channel NRZ 2.25 Gbps Bit Error Rate (BER) PRBS 223 − 1 10−9 Added Deterministic Jitter DR ≤ 2.25 Gbps, PRBS 27 − 1, EQ = 12 dB 25 ps (p-p) Added Random Jitter 1 ps (rms) Differential Intrapair Skew At output 1 ps Differential Interpair Skew

EQUALIZATION PERFORMANCE

Receiver (Highest Setting) Transmitter (Highest Setting)

INPUT CHARACTERISTICS

Input Voltage Swing Differential 150 1200 mV Input Common-Mode Voltage (V

OUTPUT CHARACTERISTICS

High Voltage Level Single-ended high speed channel AVCC − 10 AVCC + 10 mV Low Voltage Level Single-ended high speed channel AVCC − 600 AVCC − 400 mV Rise/Fall Time (20% to 80%) 75 135 200 ps

INPUT TERMINATION

Resistance Single-ended 50 Ω

AUXILIARY CHANNELS

On Resistance, R On Capacitance, C Input/Output Voltage Range DVEE AMUXVCC V

POWER SUPPLY

AVCC Operating range 3 3.3 3.6 V

QUIESCENT CURRENT

AVCC Outputs disabled 30 40 44 mA

Outputs enabled, no pre-emphasis 48 60 64 mA

Outputs enabled, maximum pre-emphasis 88 100 110 mA VTTI Input termination on VTTO Output termination on, no pre-emphasis 35 40 46 mA Output termination on, maximum pre-emphasis 72 80 90 mA DVCC 3.2 7 8 mA AMUXVCC 0.01 0.1 mA

POWER DISSIPATION Outputs disabled 115 271 361 mW Outputs enabled, no pre-emphasis 384 574 671 mW Outputs enabled, maximum pre-emphasis 704 910 1050 mW TIMING CHARACTERISTICS

Switching/Update Delay High speed switching register: HS_CH 200 ms All other configuration registers 1.5 ms RESET Pulse Width

AUX

1

2

3

100 Ω

DC bias = 2.5 V, ac voltage = 3.5 V, f = 100 kHz 8 pF

At output 40 ps

Boost frequency = 825 MHz 12 dB Boost frequency = 825 MHz 6 dB

) AVCC − 800 AVCC mV

ICM

4

50 ns

5 40 54 mA

Rev. 0 | Page 3 of 32

AD8197

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Parameter Conditions/Comments Min Typ Max Unit

SERIAL CONTROL INTERFACE

Input High Voltage, VIH 2 V Input Low Voltage, VIL 0.8 V Output High Voltage, VOH 2.4 V Output Low Voltage, VOL 0.4 V

PARALLEL CONTROL INTERFACE

Input High Voltage, VIH 2 V Input Low Voltage, VIL 0.8 V

1

Differential interpair skew is measured between the TMDS pairs of a single link.

2

AD8197 output meets the transmitter eye diagram as defined in the DVI Standard Revision 1.0 and the HDMI Standard Revision 1.3.

3

Cable output meets the receiver eye diagram mask as defined in the DVI Standard Revision 1.0 and the HDMI Standard Revision 1.3.

4

Typical value assumes only the selected HDMI/DVI link is active with nominal signal swings and that the unselected HDMI/DVI links are deactivated. Minimum and

maximum limits are measured at the respective extremes of input termination resistance and input voltage swing.

5

The AD8197 is an I2C slave and its serial control interface is based on the 3.3 V I2C bus specification.

5

Rev. 0 | Page 4 of 32

AD8197

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ABSOLUTE MAXIMUM RATINGS

Table 2.

Parameter Rating

AVCC to AVEE 3.7 V DVCC to DVEE 3.7 V DVEE to AVEE ±0.3 V VTTI AVCC + 0.6 V VTTO AVCC + 0.6 V AMUXVCC 5.5 V Internal Power Dissipation 2.2 W High Speed Input Voltage

High Speed Differential Input Voltage 2.0 V Low Speed Input Voltage

I2C and Parallel Logic Input Voltage

Storage Temperature Range −65°C to +125°C Operating Temperature Range −40°C to +85°C Junction Temperature 150°C

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

AVC C − 1.4 V < V AVCC + 0.6 V

DVEE − 0.3 V < V AMUXVCC + 0.6 V

DVEE − 0.3 V < V DVCC + 0.6 V

<

IN

<

IN

<

IN

THERMAL RESISTANCE

θJA is specified for the worst-case conditions: a device soldered in a 4-layer JEDEC circuit board for surface-mount packages.

is specified for no airflow.

θ

JC

Table 3. Thermal Resistance

Package Type θJA θ

100-Lead LQFP 56 19 °C/W

Unit

JC

MAXIMUM POWER DISSIPATION

The maximum power that can be safely dissipated by the AD8197 is limited by the associated rise in junction temperature. The maximum safe junction temperature for plastic encapsulated devices is determined by the glass transition temperature of the plastic, approximately 150°C. Temporarily exceeding this limit may cause a shift in parametric performance due to a change in the stresses exerted on the die by the package.

Exceeding a junction temperature of 175°C for an extended p

eriod can result in device failure. To ensure proper operation, it is necessary to observe the maximum power rating as determined by the coefficients in Tab l e 3 .

ESD CAUTION

Rev. 0 | Page 5 of 32

AD8197

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PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

PP_OTO

AUX_A0

AUX_A1

AUX_A2

AUX_A3

DVEE

AUX_B0

AUX_B1

AUX_B2

AUX_B3

AUX_COM0

AUX_COM1

AUX_COM2

AUX_COM3

AUX_C0

AUX_C1

AUX_C2

AUX_C3

AMUXVCC

AUX_D0

AUX_D1

AUX_D2

AUX_D3

PP_EQ

PP_EN

100

99

98

95

93

97

96

92

94

898887

91

90

84

86

85

82

83

787776

81

80

79

AVCC

IN_B0

IP_B0

AVEE

IN_B1

IP_B1

VTTI

IN_B2

IP_B2

AVEE

IN_B3

IP_B3

AVCC

IN_A0

IP_A0

AVEE

IN_A1

IP_A1

VTTI

IN_A2

IP_A2

AVCC

IN_A3

IP_A3

AVEE

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

PIN 1 IN DICATOR

27

26

29

28

DVEE

I2C_ADDR0

I2C_ADDR2

I2C_ADDR1

AD8197

TOP VIEW

(Not to Scale)

31

33

30

PP_CH0

34

32

OP0

ON0

DVCC

PP_CH1

37

38

39

42

35

36

ON1

VTTO

40

41

OP1

OP2

ON2

DVCC

44

43

OP3

ON3

VTTO

RESET

45

PP_PRE046PP_PRE1

48

47

DVCC

PP_OCL

75

AVCC

74

IP_C3

73

IN_C3

72

AVEE

71

IP_C2

70

IN_C2

69

VTTI

68

IP_C1

67

IN_C1

66

AVEE

65

IP_C0

64

IN_C0

63

AVCC

62

IP_D3

61

IN_D3

60

AVEE

59

IP_D2

58

IN_D2

57

VTTI

56

IP_D1

55

IN_D1

54

AVCC

53

IP_D0

52

IN_D0

51

AVEE

49

50

I2C_SCL

I2C_SDA

6471-003

Figure 3. Pin Configuration

Table 4. Pin Function Descriptions

Pin No. Mnemonic Type

1

Description

1, 13, 22, 54, 63, 75 AVCC Power Positive Analog Supply. 3.3 V nominal. 2 IN_B0 HS I High Speed Input Complement. 3 IP_B0 HS I High Speed Input. 4, 10, 16, 25, 51, 60, 66, 72 AVEE Power Negative Analog Supply. 0 V nominal. 5 IN_B1 HS I High Speed Input Complement. 6 IP_B1 HS I High Speed Input. 7, 19, 57, 69 VTTI Power Input Termination Supply. Nominally connected to AVCC. 8 IN_B2 HS I High Speed Input Complement. 9 IP_B2 HS I High Speed Input. 11 IN_B3 HS I High Speed Input Complement. 12 IP_B3 HS I High Speed Input. 14 IN_A0 HS I High Speed Input Complement. 15 IP_A0 HS I High Speed Input. 17 IN_A1 HS I High Speed Input Complement. 18 IP_A1 HS I High Speed Input. 20 IN_A2 HS I High Speed Input Complement. 21 IP_A2 HS I High Speed Input. 23 IN_A3 HS I High Speed Input Complement.

Rev. 0 | Page 6 of 32

AD8197

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Pin No. Mnemonic Type

24 IP_A3 HS I High Speed Input. 26 I2C_ADDR0 Control I2C Address 1st LSB. 27 I2C_ADDR1 Control I2C Address 2nd LSB. 28 I2C_ADDR2 Control I2C Address 3rd LSB. 29, 95 DVEE Power Negative Digital and Auxiliary Multiplexer Power Supply. 0 V nominal. 30 PP_CH0 Control Quad Switching Mode High Speed Source Selection Parallel Interface LSB. 31 PP_CH1 Control Quad Switching Mode High Speed Source Selection Parallel Interface MSB. 32, 38, 47 DVCC Power Positive Digital Power Supply. 3.3 V nominal. 33 ON0 HS O High Speed Output Complement. 34 OP0 HS O High Speed Output. 35, 41 VTTO Power Output Termination Supply. Nominally connected to AVCC. 36 ON1 HS O High Speed Output Complement. 37 OP1 HS O High Speed Output. 39 ON2 HS O High Speed Output Complement. 40 OP2 HS O High Speed Output. 42 ON3 HS O High Speed Output Complement. 43 OP3 HS O High Speed Output. 44 45 PP_PRE0 Control High Speed Pre-Emphasis Selection Parallel Interface LSB. 46 PP_PRE1 Control High Speed Pre-Emphasis Selection Parallel Interface MSB. 48 PP_OCL Control High Speed Output Current Level Parallel Interface. 49 I2C_SCL Control I2C Clock. 50 I2C_SDA Control I2C Data. 52 IN_D0 HS I High Speed Input Complement. 53 IP_D0 HS I High Speed Input. 55 IN_D1 HS I High Speed Input Complement. 56 IP_D1 HS I High Speed Input. 58 IN_D2 HS I High Speed Input Complement. 59 IP_D2 HS I High Speed Input. 61 IN_D3 HS I High Speed Input Complement. 62 IP_D3 HS I High Speed Input. 64 IN_C0 HS I High Speed Input Complement. 65 IP_C0 HS I High Speed Input. 67 IN_C1 HS I High Speed Input Complement. 68 IP_C1 HS I High Speed Input. 70 IN_C2 HS I High Speed Input Complement. 71 IP_C2 HS I High Speed Input. 73 IN_C3 HS I High Speed Input Complement. 74 IP_C3 HS I High Speed Input. 76 PP_EN Control High Speed Output Enable Parallel Interface. 77 PP_EQ Control High Speed Equalization Selection Parallel Interface. 78 AUX_D3 LS I/O Low Speed Input/Output. 79 AUX_D2 LS I/O Low Speed Input/Output. 80 AUX_D1 LS I/O Low Speed Input/Output. 81 AUX_D0 LS I/O Low Speed Input/Output. 82 AMUXVCC Power Positive Auxiliary Multiplexer Supply. 5 V typical. 83 AUX_C3 LS I/O Low Speed Input/Output. 84 AUX_C2 LS I/O Low Speed Input/Output. 85 AUX_C1 LS I/O Low Speed Input/Output. 86 AUX_C0 LS I/O Low Speed Input/Output. 87 AUX_COM3 LS I/O Low Speed Common Input/Output. 88 AUX_COM2 LS I/O Low Speed Common Input/Output. 89 AUX_COM1 LS I/O Low Speed Common Input/Output.

RESET

1

Control Configuration Registers Reset. Normally pulled up to AVCC.

Description

Rev. 0 | Page 7 of 32

AD8197

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Pin No. Mnemonic Type

90 AUX_COM0 LS I/O Low Speed Common Input/Output. 91 AUX_B3 LS I/O Low Speed Input/Output. 92 AUX_B2 LS I/O Low Speed Input/Output. 93 AUX_B1 LS I/O Low Speed Input/Output. 94 AUX_B0 LS I/O Low Speed Input/Output. 96 AUX_A3 LS I/O Low Speed Input/Output. 97 AUX_A2 LS I/O Low Speed Input/Output. 98 AUX_A1 LS I/O Low Speed Input/Output. 99 AUX_A0 LS I/O Low Speed Input/Output. 100 PP_OTO Control High Speed Output Termination Selection Parallel Interface.

1

HS = high speed, LS = low speed, I = input, O = output.

1

Description

Rev. 0 | Page 8 of 32

AD8197

V

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TYPICAL PERFORMANCE CHARACTERISTICS

TA = 27°C, AVCC = 3.3 V, VTTI = 3.3 V, VTTO = 3.3 V, DVCC = 3.3 V, AMUXVCC = 5 V, AVEE = 0 V, DVEE = 0 V, differential input swing = 1000 mV, TMDS outputs terminated with external 50 Ω resistors to 3.3 V, pattern = PRBS 2 otherwise noted.

HDMI CABLE

DIGITAL

PATTERN

GENERATOR

AD8197

EVALUATION

BOARD

7

− 1, data rate = 2.25 Gbps, unless

SERIAL DATA

ANALYZER

SMA COAX CABLE

REFERENCE EYE DI AGRAM AT TP1

250mV/DI

0.125UI/DI V AT 2.25Gbps

Figure 5. RX Eye Diagram at TP2 (Cable = 2 meters, 30 AWG)

TP1 TP2 TP3

Figure 4. Test Circuit Diagram for RX Eye Diagram

250mV/DI

06471-005

Figure 7. RX Eye Diagram at TP3, EQ = 6 dB (Cable = 2 meters, 30 AWG)

0.125UI/DI V AT 2.25Gbps

6470-004

06471-007

250mV/DI

0.125UI/DI V AT 2.25Gbps

06471-006

Figure 6. RX Eye Diagram at TP2 (Cable = 20 meters, 24 AWG)

Rev. 0 | Page 9 of 32

250mV/DI

Figure 8. RX Eye Diagram at TP3, EQ = 12 dB (Cable = 20 meters, 24 AWG)

0.125UI/DI V AT 2.25Gbps

06471-008

AD8197

V

www.BDTIC.com/ADI

TA = 27°C, AVCC = 3.3 V, VTTI = 3.3 V, VTTO = 3.3 V, DVCC = 3.3 V, AMUXVCC = 5 V, AVEE = 0 V, DVEE = 0 V, differential input swing = 1000 mV, TMDS outputs terminated with external 50 Ω resistors to 3.3 V, pattern = PRBS 2 otherwise noted.

HDMI CABLE

7

− 1, data rate = 2.25 Gbps, unless

REFERENCE EYE DIAGRAM AT T P1

DIGITAL

PATTERN

GENERATOR

SMA COAX CABLE

AD8197

EVALUATIO N

BOARD

TP1 TP2 TP3

SERIAL DATA

ANALYZER

06470-009

Figure 9. Test Circuit Diagram for TX Eye Diagrams

250mV/DI

0.125UI/DI V AT 2.25Gbps

Figure 10. TX Eye Diagram at TP2, PE = 2 dB

06471-010

250mV/DI

0.125UI/DI V AT 2.25Gbps

06471-012

Figure 12. TX Eye Diagram at TP3, PE = 2 dB (Cable = 2 meters, 30 AWG)

250mV/DI

0.125UI/DI V AT 2.25Gbps

06471-011

Figure 11. TX Eye Diagram at TP2, PE = 6 dB

Rev. 0 | Page 10 of 32

250mV/DI

0.125UI/DI V AT 2.25Gbps

Figure 13. TX Diagram at TP3, PE = 6 dB (Cable = 10 meters, 28 AWG)

06471-013

ANALOG DEVICES AD8197B Service Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

FEATURES

APPLICATIONS

GENERAL DESCRIPTION

FUNCTIONAL BLOCK DIAGRAM

TYPICAL APPLICATION

PRODUCT HIGHLIGHTS

TABLE OF CONTENTS

REVISION HISTORY

SPECIFICATIONS

ABSOLUTE MAXIMUM RATINGS

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

TYPICAL PERFORMANCE CHARACTERISTICS