Analog Devices AD8184 Datasheet

700 MHz, 5 mA

a

FEATURES
Single and Dual 2-to-1 Also Available (AD8180 and AD8182)
Fully Buffered Inputs and Outputs
Fast Channel Switching: 10 ns
High Speed

> 700 MHz Bandwidth (–3 dB)
> 750 V/ms Slew Rate
Fast Settling Time of 15 ns to 0.1%

Excellent Video Specifications (R

Gain Flatness of 0.1 dB of 75 MHz

0.01% Differential Gain Error, R

0.018 Differential Phase Error, RL = 10 kV
Low Power: 4.4 mA
Low Glitch: < 25 mV
Low All-Hostile Crosstalk of –95 dB @ 5 MHz
High “OFF” Isolation of –115 dB @ 5 MHz
Low Cost
Fast Output Disable Feature for Connecting Multiple Devices

APPLICATIONS
Pin Compatible with HA4314* and GX4314*
Video Switchers and Routers
Pixel Switching for “Picture-In-Picture”
Switching in LCD and Plasma Displays

> 2 kV)

L

= 10 kV

L

4-to-1 Video Multiplexer

AD8184

FUNCTIONAL BLOCK DIAGRAM

IN0

GND

IN1

GND

IN2

GND

IN3

+1

1
2

3

+1

DECODER

4

+1

5

6

7

+1

AD8184

NC = NO CONNECT

Table I. Truth Table

ENABLE A1 A0 OUTPUT

0 0 0 IN0
0 0 1 IN1
0 1 0 IN2
0 1 1 IN3
1 X X High Z

14
13

12

11
10

9

8

+V

S

A0
A1

ENABLE

OUT

NC

–V

S

PRODUCT DESCRIPTION

The AD8184 is a high speed 4-to-1 multiplexer. It offers –3 dB
signal bandwidth of 700 MHz along with a slew rate of 750 V/µs.
With 95 dB of crosstalk and 115 dB isolation, it is useful in
many high speed applications. The differential gain and differ­ential phase error of 0.01% and 0.01°, along with 0.1 dB flatness
of 75 MHz, make AD8184 ideal for professional video multi­plexing. It offers 10 ns switching time, making it an excellent
choice for pixel switching (picture-in-picture) while consuming
less than 4.5 mA on ±5 V supply voltage.

The AD8184 offers a high speed disable feature allowing the
output to be put into a high impedance state. This allows mul­tiple outputs to be connected together for cascading stages while
the “OFF” channels do not load the output bus. It operates on
voltage supplies of ±5 V and is offered in 14-lead PDIP and
SOIC packages.

*All trademarks are the property of their respective holders.

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Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.

5

VIN = 50mVrms

4

R

= 5kΩ

L

3

2

1

0

–1

–2

NORMALIZED OUTPUT – dB

–3

–4
–5

1M

10M 100M 1G

FREQUENCY – Hz

Figure 1. Small Signal Frequency Response

One T echnology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] World Wide Web Site: http://www.analog.com
Fax: [phone] © Analog Devices, Inc., 1997

AD8184–SPECIFICA TIONS

(@ TA = +258C, VS = 65 V, RL = 2 kV unless otherwise noted)

Parameter Conditions Min Typ Max Units

AD8184A

SWITCHING CHARACTERISTICS

Channel Switching Time

1

Channel-to-Channel
50% Logic to 10% Output Settling IN0 = +1 V, IN1 = –1 V 5 ns
50% Logic to 90% Output Settling 10 ns
50% Logic to 99.9% Output Settling 15 ns

ENABLE to Channel ON Time

50% Logic to 90% Output Settling IN0 = +1 V, –1 V or IN1 = –1 V, +1 V 12 ns

ENABLE to Channel OFF Time

50% Logic to 90% Output Settling IN1 = +1 V, –1 V or IN1 = –1 V, +1 V 22 ns

Channel Switching Transient (Glitch)

2

2

3

A0, A1 = 0 or 1

A0, A1 = 0 or 1

All Inputs Are Grounded ±25 mV

DIGITAL INPUTS

Logic “1” Voltage A0, A1 and ENABLE Inputs 2.0 V
Logic “0” Voltage A0, A1 and ENABLE Inputs 0.8 V
Logic “1” Input Current A0, A1, ENABLE = +4 V 10 200 nA
Logic “0” Input Current A0, A1, ENABLE = +0.4 V 2 3 µA

DYNAMIC PERFORMANCE

–3 dB Bandwidth (Small Signal)4AD8184AR VIN = 50 mV rms, RL = 5 kΩ 550 700 MHz
–3 dB Bandwidth (Large Signal) AD8184AR VIN = 1 V rms, RL = 5 kΩ 105 135 MHz

0.1 dB Bandwidth

4, 5

AD8184AR VIN = 50 mV rms, RL = 5 kΩ 60 75 MHz
Slew Rate 2 V Step 600 750 V/µs
Settling Time to 0.1% 2 V Step 15 ns

DISTORTION/NOISE PERFORMANCE

Differential Gain ƒ = 3.58 MHz, RL = 2 kΩ 0.2 %

f = 3.58 MHz, RL = 10 kΩ 0.01 0.02 %

Differential Phase f = 3.58 MHz, RL = 2 kΩ 0.2 Degrees
All Hostile Crosstalk
OFF Isolation

7

6

AD8184AR ƒ = 5 MHz –95 dB

AD8184AR ƒ = 5 MHz, RL = 30 Ω –115 dB

f = 3.58 MHz, RL = 10 kΩ 0.01 0.02 Degrees

ƒ = 30 MHz –78 dB

Voltage Noise ƒ = 30 MHz 4.5 nV/√Hz
Total Harmonic Distortion ƒC = 10 MHz, VO = 2 V p-p, RL = 1 kΩ –74 dBc

DC/TRANSFER CHARACTERISTICS

Voltage Gain

8

VIN = ±1 V 0.982 V/V

Input Offset Voltage 28 mV

T

to T

MIN

Input Offset Voltage Drift 5 µV/°C

MAX

15 mV

Input Offset Voltage Matching Channel-to-Channel 0.6 3 mV
Input Bias Current 2.5 7.5 µA

T

to T

MIN

Input Bias Current Drift 5 nA/°C

MAX

9.5 µA

INPUT CHARACTERISTICS

Input Resistance 1.0 2.4 MΩ
Input Capacitance Channel Enabled (R Package) 1.6 pF

Channel Disabled (R Package) 1.6 pF

Input Voltage Range ±3.3 V

OUTPUT CHARACTERISTICS

Output Voltage Swing VIN = ±4 V, RL = 2 kΩ

9

±3.15 ±3.2 V
Short Circuit Current 30 mA
Output Resistance Enabled 28 33 Ω

Disabled 10 MΩ

Output Capacitance Disabled (R Package) 3.2 pF

POWER SUPPLY

Operating Range ± 4 ±6V
Power Supply Rejection Ratio +PSRR +VS = +4.5 V to +5.5 V, –VS = –5 V 5 4 57 dB

Power Supply Rejection Ratio –PSRR –VS = –4.5 V to –5.5 V, +VS = +5 V 51 54 dB

Quiescent Current Enabled 4.4 5.2 mA

T

to T

MIN

MIN

to T

MAX

MAX

Disabled 2.1 2.9 mA
T

5.7 mA

2.9 mA

OPERATING TEMPERATURE RANGE –40 +85 °C

–2–

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AD8184

WARNING!

ESD SENSITIVE DEVICE

NOTES

1

ENABLE pin is grounded. IN0 and IN2 = +1 V dc, IN1 and IN3 = –1 V dc. A0 is driven with a 0 V to +5 V pulse, A1 is grounded. Measure transition time from 50% of the A0
input value (+2.5 V) and 10% (or 90%) of the total output voltage transition from IN0 channel voltage (+1 V) to IN1 (–1 V), or vice versa. All inputs are measured in a similar
manner using A0 and A1 to select the channels.

2

ENABLE pin is driven with 0 V to +5 V pulse (with 3 ns edges). The state of the A0 and A1 pins determines which input is activate d (refer to Table I). Set IN0 and IN2 = +1 V dc,
IN1 and IN3 = –1 V dc, and measure transition time from 50% of
is the enable time.

3

All inputs are grounded. A0 input is driven with 0 V to +5 V pulse, A1 is grounded. The output is monitored. Speeding the edges of the A0 pulse increases the glitch magnitude
due to coupling via the ground plane. Removing the A0 and A1 terminations will lower the glitch, as does increasing R

4

Decreasing RL slightly lowers the bandwidth. Increasing CL significantly lowers the bandwidth (see Figure 18).

5

A resistor (RS) placed in series with the multiplexer inputs serves to optimize 0.1 dB flatness, but is not required (see Figure 19.)

6

Select an input that is not being driven (i.e., A0 and A1 are logic 0, IN0 is selected); drive all other inputs with VIN = 0.707 V rms and monitor the output at ƒ = 5 and 30 MHz.

= 2 kΩ (see Figure 12).

R

L

7

Multiplexer is disabled (i.e., ENABLE = logic 1) and all inputs are driven simultaneously with VIN = 0.446 V rms. Output is monitored at ƒ = 5 and 30 MHz. RL = 30 Ω to simu-

of one enabled multiplexer within a system (see Figure 13). In this mode the output impedance is very high (typ 10 MΩ), and the signal couples across the package; the

late R

ON

load impedance determines the crosstalk.

8

Voltage gain decreases for lower values of RL. The resistive divider formed by the multiplexers enables output resistance (28 Ω) and RL causes a gain that increases as R
decreases (i.e., the voltage gain is approximately 0.97 V/V [3% gain error] for RL = 1 kΩ).

9

Larger values of RL provide wider output voltage swings, as well as better gain accuracy. See Note 8.

Specifications subject to change without notice.

ENABLE pulse (+2.5 V) to 90% of the total output voltage change. In Figure 4, ∆t

.

L

is the disable time, ∆t

OFF

ON

L-

ABSOLUTE MAXIMUM RATINGS

Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12.6 V

Internal Power Dissipation

2

1

AD8184 14-Lead Plastic (N) . . . . . . . . . . . . . . . . 1.6 Watts

AD8184 14-Lead Small Outline (R) . . . . . . . . . . 1.0 Watts

Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .±V

S

Output Short Circuit Duration . . Observe Power Derating Curves
Storage Temperature Range

N & R Package . . . . . . . . . . . . . . . . . . . . . –65°C to +125°C

Lead Temperature Range (Soldering 10 sec) . . . . . . . +300°C

NOTES

1

Stresses above those listed under Absolute Maximum Ratings may cause perma-

nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.

2

Specification is for device in free air: 14-pin plastic package: θJA = 75°C/Watt

14-pin SOIC package: θJA = 120°C/Watt, where PD = (TJ–TA)/θJA.

ORDERING GUIDE

Temperature Package Package

Model Range Description Option

AD8184AN –40°C to +85°C 14-Lead Plastic DIP N-14
AD8184AR –40°C to +85°C 14-Lead Narrow SOIC R-14
AD8184AR-REEL –40°C to +85°C Reel 14-Lead SOIC R-14
AD8184-EB Evaluation Board For AD8184R

While the AD8184 is internally short circuit protected, this may
not be sufficient to guarantee that the maximum junction tempera­ture (+150°C) is not exceeded under all conditions. To ensure
proper operation, it is necessary to observe the maximum power
derating curves shown in Figure 2.

2.5
TJ = +150°C

2.0

14-PIN DIP PACKAGE

1.5

1.0

MAXIMUM POWER DISSIPATION – Watts

0.5

14-PIN SOIC

–30 –20 –10 0 10 20 30 40 50 60 80

–50 90–40

AMBIENT TEMPERATURE – °C

70

Figure 2. Maximum Power Dissipation vs. Temperature

MAXIMUM POWER DISSIPATION

The maximum power that can be safely dissipated by the AD8184
is limited by the associated rise in junction temperature. The maxi­mum safe junction temperature for plastic encapsulated devices is
determined by the glass transition temperature of the plastic,
approximately +150°C. Exceeding this limit temporarily may
cause a shift in parametric performance due to a change in the
stresses exerted on the die by the package. Exceeding a junction
temperature of +175°C for an extended period can result in
device failure.

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD8184 feature proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.

REV. 0

–3–

AD8184–T ypical Performance Curves

DUT OUT

500mV/DIV

A0 PULSE
0 TO 5V

1V

–1V

OUTPUT

5ns/DIV

5

V

= 50mVrms

IN

4

R

= 5kΩ

L

= 0Ω

R

3

S

2

1

0

–1

–2

NORMALIZED OUTPUT – dB

–3

–4
–5

1M

10M 100M 1G

FREQUENCY – Hz

Figure 3 Channel Switching Characteristics

PULSE

0 TO 5V

t

OFF

10ns/DIV

t

ON

+1V

DUT OUT

800mV/DIV

–1V
+1V

–1V

Figure 4. Enable and Disable Switching Characteristics

OUTPUT

SWITCHING A0

25mV/DIV

OUTPUT

SWITCHING A1

A0 and A1 PULSE

0 TO +5V

25ns/DIV

Figure 6. Small Signal Frequency Response

0.5
VIN = 50mVrms

0.4

= 5kΩ

R

L

= 0Ω

R

S

0.3

0.2

0.1

0.0

–0.1
–0.2

NORMALIZED FLATNESS – dB

–0.3

–0.4
–0.5

1M 10M 100M 1G

FREQUENCY – Hz

Figure 7. Gain Flatness vs. Frequency

3

RL = 5kΩ

0

–3

–6
–9

–12

–15

OUTPUT – dBV

–18
–21

–24
–27

1M 10M 100M 1G

VIN = 1.0Vrms

VIN = 0.5Vrms

VIN = 0.25Vrms

VIN = 125mVrms

VIN = 62.5mVrms

FREQUENCY – Hz

Figure 5. Channel Switching Transient (Glitch)

–4–

Figure 8. Large Signal Frequency Response

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