Analog Devices AD8116 Datasheet

AD8116

SWITCH
MATRIX

OUTPUT
BUFFER

ENABLE/DISABLE

80

80

256

80-BIT SHIFT REG.

PARALLEL LATCH

DECODE

16 ⴛ 5:16 DECODERS

16

+1

+1

+1

+1

+1

+1

+1

+1

+1

+1

+1

+1

+1

+1

+1

+1

CLK

DATA IN

UPDATE

CE

RESET

16 INPUTS

CLK

DATA OUT

UPDATE
CE

RESET

16 OUTPUTS

SET INDIVIDUAL OR

RESET ALL OUTPUTS

TO "OFF"

200 MHz, 16 ⴛ 16 Buffered

FREQUENCY – Hz

+4

+3

–4

100k 1G1M

MAGNITUDE – dB

10M 100M

0

–1

–2

–3

+2

+1

+0.5

+0.4

–0.3

0

–0.1

–0.2

+0.3

+0.2

0.1dB FLATNESS – dB

+0.1

2V p-p

200mV p-p

FLATNESS

RL=150V

200mV p-p

2V p-p

a

FEATURES
Large 16 ⴛ 16 High Speed Nonblocking Switch Array
Switch Array Controllable via an 80-Bit Serial Word
Serial Data Out Allows “Daisy Chaining” of Multiple

AD8116s to Create Large Switch Arrays Over 256 ⴛ 256

Complete Solution

Buffered Inputs
16 Individual Output Amplifiers
Drives 150 ⍀ Loads

Excellent Video Performance

60 MHz 0.1 dB Gain Flatness

0.01% Differential Gain Error (R

0.01ⴗ Differential Phase Error (R

Excellent AC Performance

200 MHz –3 dB Bandwidth

300 V/␮s Slew Rate
Low Power of 900 mW (3.5 mW per Point)
Low All Hostile Crosstalk of –70 dB @ 5 MHz
Output Disable Allows Direct Connection of Multiple

Device Outputs
Chip Enable Allows Selection of Individual AD8116s in

Large Arrays (or Parallel Programming of AD8116s)
Reset Pin Allows Disabling of All Outputs (Connected

Through a Capacitor to Ground Provides “Power-

On” Reset Capability)

128-Lead LQFP Package (14 mm ⴛ 14 mm)

= 150 ⍀)

L

= 150 ⍀)

L

Video Crosspoint Switch

AD8116*

FUNCTIONAL BLOCK DIAGRAM

APPLICATIONS
Routing of High Speed Signals Including:

Composite Video (NTSC, PAL, S, SECAM, etc.)

Component Video (YUV, RGB, etc.)

3-Level Digital (HDB3)
Video on Demand
Ultrasound
Communication Satellites

PRODUCT DESCRIPTION

The AD8116 is a high speed 16 × 16 video crosspoint switch

matrix. It offers a –3 dB signal bandwidth greater than 200 MHz
and channel switch times of 60 ns with 0.1% settling. With –70 dB
of crosstalk and –105 dB of isolation (@ 5 MHz), the AD8116
is useful in many high speed applications. The differential gain

and differential phase errors of better than 0.01% and 0.01°,

respectively, along with 0.1 dB flatness out to 60 MHz make the
AD8116 ideal for video signal switching.

The AD8116 includes output buffers that can be placed into a
high impedance state for paralleling crosspoint outputs so that
off channels do not load the output bus. It operates on voltage

*Patent Pending.

REV. A

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.

Figure 1. Frequency Response

supplies of ±5 V while consuming only 90 mA of idle current.

The channel switching is performed via a serial digital control
that can accommodate “daisy chaining” of several devices.

The AD8116 is packaged in a 128-lead LQFP package occupy­ing only 0.36 square inches, and is specified over the commer-

cial temperature range of 0°C to +70°C.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] World Wide Web Site: http://www.analog.com
Fax: [phone] © Analog Devices, Inc., 1999

AD8116–SPECIFICATIONS

(VS = ⴞ 5 V, TA = +25ⴗC, RL = 1 k⍀ unless otherwise noted)

Limit Reference

Parameter Conditions Min Typ Max Units Figure

DYNAMIC PERFORMANCE

–3 dB Bandwidth 200 mV p-p, R

1 V p-p, R

2 V p-p, R
Slew Rate 2 V Step, R
Settling Time 0.1%, 2 V Step, R
Gain Flatness 0.05 dB, 200 mV p-p, R

0.05 dB, 2 V p-p, R

0.1 dB, 200 mV p-p, R

0.1 dB, 2 V p-p, R

= 150 Ω 200 MHz 6

L

= 150 Ω 120 MHz –

L

= 150 Ω 80 MHz 6

L

= 150 Ω 300 V/µs10

L

= 150 Ω 60 ns 11

L

= 150 Ω 25 MHz 6

L

= 150 Ω 20 MHz 6

L

= 150 Ω 60 MHz 6

L

= 150 Ω 45 MHz 6

L

NOISE/DISTORTION PERFORMANCE

Differential Gain Error NTSC or PAL, R

NTSC or PAL, R
Differential Phase Error NTSC or PAL, R

NTSC or PAL, R

= 1 kΩ 0.01 % –

L

= 150 Ω 0.01 % –

L

= 1 kΩ 0.01 Degrees –

L

= 150 Ω 0.01 Degrees –

L

Crosstalk, All Hostile ƒ = 5 MHz –70 dB 7

ƒ = 10 MHz –60 dB 7
Off Isolation, Input-Output ƒ = 10 MHz, R

= 150 Ω, One Channel –105 dB 16

L

Input Voltage Noise 0.01 MHz to 50 MHz 15 nV/√Hz 13

DC PERFORMANCE

Gain No Load 0.995 0.999 1.000 V/V –

R

= 1 kΩ 0.992 0.999 1.000 V/V –

L

Gain Matching No Load, Ch-Ch 0.15 % –

R

= 1 kΩ, Ch-Ch 0.5 % –

L

OUTPUT CHARACTERISTICS

Output Offset Voltage Worst Case All Switch Configurations 15 45 mV 22

Output Impedance DC, Enabled 0.2 Ω 17

Disabled 1 10 MΩ 14

Output Disable Capacitance 3 pF 14

Output Leakage Current Disabled 1 µA–
Output Voltage Range ±2.5 ±3V–

Output Current 20 40 mA –
Short Circuit Current 65 mA –

INPUT CHARACTERISTICS

Input Voltage Range ±2.5 ±3V–

Input Capacitance Any Switch Configuration 5 pF 18

Input Resistance 1 10 MΩ 18
Input Bias Current 25µA–

SWITCHING CHARACTERISTICS

Enable On Time 60 ns –
Switching Time 50% UPDATE to 1% Output Settling, 50 ns 21

2 V Step
Switching Transient (Glitch) 15 mV p-p 15

POWER SUPPLIES

Supply Current AVCC, Outputs Enabled, No Load 75 95 mA –

AVCC, Outputs Disabled 25 mA –

AVEE, Outputs Enabled, No Load 70 95 mA –

AVEE, Outputs Disabled 22.5 mA –

DVCC, Outputs Enabled, No Load 25 35 mA –

DVEE, Outputs Enabled, No Load 10 15 mA –

Supply Voltage Range ±4.5 to ±5.5 V –

PSRR ƒ = 100 kHz 60 dB 12

ƒ = 1 MHz 40 dB 12

OPERATING TEMPERATURE RANGE

Temperature Range Operating (Still Air) 0 to +70 °C–

θ

JA

Specifications subject to change without notice.

Operating (Still Air) 37 °C/W –

–2–

REV. A

AD8116

TIMING CHARACTERISTICS

Limit

Parameter Symbol Min Typ Max Units

Data Setup Time t
CLK Pulsewidth t
Data Hold Time t
CLK Pulse Separation t
CLK to UPDATE Delay t
UPDATE Pulsewidth t
CLK to DATA OUT Valid t

1

2

3

4

5

6

7

Propagation Delay, UPDATE to Switch On or Off – 50 ns
Data Load Time, CLK = 5 MHz – 16 µs
CLK, UPDATE Rise and Fall Times – 100 ns
RESET Time – 200 ns

20 ns
100 ns
20 ns
100 ns
0ns
50 ns

200 ns

CLK

DATA IN

1 = LATCHED

UPDATE

0 = TRANSPARENT

DATA OUT

CLOCK

DATA IN

UPDATE

t

1

0

t1t

1

OUT15 (D4) OUT15 (D3) OUT00 (D0)

0

2

3

t

7

0

1 2 3 4 5 6 7 8 9 10 15 20 25 75 79

NPUT 00

CONNECT TO

ENABLE OUTPUT 15

t

4

INPUT 01

CONNECT TO

ENABLE OUTPUT 14

DISABLE OUTPUT 13

DON’T CARE

ENABLE OUTPUT 12

LOAD DATA INTO
SERIAL REGISTER
ON FALLING EDGE

INPUT 15

CONNECT TO

ENABLE OUTPUT 11

TRANSFER DATA FROM SERIAL

REGISTER TO PARALLEL

LATCHES DURING LOW LEVEL

INPUT 03

CONNECT TO

t

5

CONNECT TO

ENABLE OUTPUT 00

INPUT 00

t

6

T = 0

INCREASING TIME

Figure 2. Timing Diagram and Programming Example

Table I. Logic Levels

V

IH

CLK, DATA IN, CLK, DATA IN, DATA OUT DATA OUT CLK, DATA IN, CLK, DATA IN, DATA OUT DATA OUT
CE, UPDATE CE, UPDATE CE, UPDATE CE, UPDATE

2.0 V min 0.8 V max 2.7 V min 0.5 V max 20 µA max –400 µA min –400 µA max 3.0 mA min

REV. A

V

IL

V

OH

V

OL

I

IH

I

IL

I

OH

I

OL

–3–

AD8116

AMBIENT TEMPERATURE – ⴗC

5.0

MAXIMUM POWER DISSIPATION – Watts

4.0

0

–50 80–40 –30 –20 –10 0 10 20 30 40 50 60 70

3.0

2.0

1.0

TJ = 150ⴗC

90

WARNING!

ESD SENSITIVE DEVICE

ABSOLUTE MAXIMUM RATINGS

Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12.0 V

Internal Power Dissipation

2

1

AD8116 128-Lead Plastic LQFP (ST) . . . . . . . . . . . . 3.5 W

Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .±V

S

Output Short Circuit Duration

. . . . . . . . . . . . . . . . . . . . Observe Power Derating Curves

Storage Temperature Range . . . . . . . . . . . . –65°C to +125°C

Lead Temperature Range (Soldering 10 sec) . . . . . . . . +300°C

NOTES

1

Stresses above those listed under Absolute Maximum Ratings may cause perma-

nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.

2

Specification is for device in free air (T

128-lead plastic LQFP (ST): θJA = 37°C/W.

= +25°C):

A

ORDERING GUIDE

Temperature Package Package

Model Range Description Option

AD8116JST 0°C to +70°C 128-Lead Plastic LQFP ST-128A

(14 mm × 14 mm)

AD8116-EB Evaluation Board

MAXIMUM POWER DISSIPATION

The maximum power that can be safely dissipated by the
AD8116 is limited by the associated rise in junction tempera­ture. The maximum safe junction temperature for plastic
encapsulated devices is determined by the glass transition

temperature of the plastic, approximately +150°C. Temporarily

exceeding this limit may cause a shift in parametric performance
due to a change in the stresses exerted on the die by the package.

Exceeding a junction temperature of +175°C for an extended

period can result in device failure.

While the AD8116 is internally short circuit protected, this may
not be sufficient to guarantee that the maximum junction temp-

erature (+150°C) is not exceeded under all conditions. To

ensure proper operation, it is necessary to observe the maximum
power derating curves shown in Figure 3.

Figure 3. Maximum Power Dissipation vs. Temperature

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD8116 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.

–4–

REV. A

AD8116

Table II. Operation Truth Table

Control Lines

CE UPDATE CLK DATA IN DATA OUT RESET Operation/Comment

1 X X X X 1 No change in logic.
01 f Data

i

0 0 X X X 1 Data in the serial shift register transfers into the

X X X X X 0 Asynchronous operation. All outputs are disabled.

Data

i-80

1 The data on the DATA IN line is loaded into the

serial register. The first bit clocked into the serial
register appears at DATA OUT 80 clocks later.

parallel latches that control the switch array.
Latches are transparent.

Remainder of logic is unchanged.

DATA IN

CLK

OUTPUT CH

CH BIT #

SERIAL BIT #

DDDDDDQQQQQQ

CLK CLK CLK CLK CLK CLK

0

12 3EN

LSB

MSB

0

Figure 4. Logic Diagram

DECODE

256

SWITCH MATRIX

DDDDDDQQQQQQ

CLK CLK CLK CLK CLK CLK

LE D LE D LE D LE D LE D LE DLE D LE D LE D LE D LE D LE D
OUT14 OUT15 OUT15 OUT15 OUT15 OUT15OUT0 OUT0 OUT0 OUT0 OUT0 OUT1

EN 0

543 21079 78 77 76 75 74

CLRQQQQQQCLRCLR Q QQQQQ

123EN

LSB

MSB

DATA OUT

16

OUTPUT
ENABLE

REV. A

–5–

AD8116

PIN FUNCTION DESCRIPTIONS

Pin Name Pin Numbers Pin Description

INxx 2, 4, 6, 8, 10, 12, 14, 16, 18, Analog Inputs; xx = Channel No. 00 thru 15.

20, 22, 24, 26, 28, 30, 32
DATA IN 37, 126 Serial Data Input, TTL Compatible.
CLK 36, 125 Serial Clock, TTL Compatible. Falling edge triggered.
DATA OUT 35, 124 Serial Data Out, TTL Compatible.
UPDATE 38, 123 Enable (Transparent) “Low.” Allows serial register to connect directly to switch

matrix. Data latched when “high.”

RESET 39, 122 Disable Outputs, Enable “Low.”
CE 40, 121 Chip Enable, Enable “Low.” Must be “low” to clock in & latch data.

OUTyy 65, 67, 69, 71, 73, 75, 77, 79, Analog Outputs yy = Channel Nos. 00 thru 15.

81, 83, 85, 87, 89, 91, 93, 95
AGND 1, 3, 5, 7, 9, 11, 13, 15, 17, 19, Analog Ground for inputs and switch matrix.

21, 23, 25, 27, 29, 31, 33, 128
DVCC 34, 39, 127 +5 V for Digital Circuitry.
DGND 41, 120 Ground for Digital Circuitry.
DVEE 42, 119 –5 V for Digital Circuitry.
AVEE 43, 44, 45, 116, 117, 118 –5 V for Inputs and Switch Matrix.
AVCC 46, 47, 48, 113, 114, 115 +5 V for Inputs and Switch Matrix.
AGNDxx 56–63, 97–104 Ground for Output Amp, xx = Output Channel Nos. 00 thru 15. Must be connected.
AVCC00 96 +5 V for Output Channel 00. Must be connected.
AVCC15 64 +5 V for Output Channel 15. Must be connected.
AVCCxx/yy 68, 72, 76, 80, 84, 88, 92 +5 V for Output Amplifier that is shared by Channel Nos. xx and yy. Must be connected.
AVEExx/yy 66, 70, 74, 78, 82, 86, 90, 94 –5 V for Output Amplifier that is shared by Channel Nos. xx and yy. Must be connected.

V

ESD

INPUT

ESD

V

a. Analog Input

V

CC

EE

V

CC

ESD

INPUT

ESD

V

EE

d. Logic Input

CC

ESD

ESD

V

EE

b. Analog Output

OUTPUT

RESET

V

CC

2k⍀

ESD

ESD

V

EE

e. Logic Output

V

CC

ESD

ESD

c. Reset Input

OUTPUT

20k⍀

Figure 5. I/O Pin Schematics

–6–

REV. A

AGND
128

1

AGND

2

IN00

3

AGND

4

IN01

5

AGND

6

IN02

7

AGND

8

IN03

9

AGND

10

IN04

11

AGND

12

IN05

13

AGND

14

IN06

15

AGND

16

IN07

17

AGND

18

IN08

19

AGND

20

IN09

21

AGND

22

IN10

23

AGND

24

IN11

25

AGND

26

IN12

27

AGND

28

IN13

29

AGND

30

IN14

31

AGND

32

IN15

33

AGND

NC = NO CONNECT

DVCC

DATA IN

127

126

PIN 1
IDENTIFIER

35

34

DVCC

DATA OUT

DATA OUT

CLK
125

124

36

37

CLK

DATA IN

123

38

AD8116

PIN CONFIGURATION

NC
110

51

NC

NC

108

109

53

52
NC

NCNCNC

NC
107

54

NC
106

55

AGND00

NC
105

104

57

56

AGND15

AGND14

AGND02

AGND01

102

103

59

58

AGND13

AGND12

NC

DVEE

AVEE

AVEE

DGND

121

122

120

41

39

40

DGND

119

42

DVEE

118

43

AVEE

117

44

AVEE

AVEE

116

45

AVEE

NC

AVCC

AVCC

AVCC
115

112

113

114

AD8116

128L LQFP

(14mm x 14mm)

TOP VIEW

(Not to Scale)

49

48

47

46

NCNCNC

AVCC

AVCC

AVCC

111

50

AGND04

AGND03
101

100

61

60

AGND11

AGND10

AGND06

AGND05

98

99

62

63

AGND09

AGND08

AGND07
97

96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65

64

AVCC15

AVCC00
OUT00
AVEE00/01
OUT01
AVCC01/02
OUT02
AVEE02/03
OUT03
AVCC03/04
OUT04
AVEE04/05
OUT05
AVCC05/06
OUT06
AVEE06/07
OUT07
AVCC07/08
OUT08
AVEE08/09
OUT09
AVCC09/10
OUT10
AVEE10/11
OUT11
AVCC11/12
OUT12
AVEE12/13
OUT13
AVCC13/14
OUT14
AVEE14/15
OUT15

REV. A

–7–

AD8116

100ns/DIV

500mV/DIV

2V p-p

2mV/DIV

= 0.1%/DIV

20ns/DIV

0 20 40 60 80 100 120 140 160 180

2V STEP

RL = 150⍀

–Typical Performance Characteristics

+4

RL=150V
CL=0pF

+3

+2

+1

0

–1

MAGNITUDE – dB

–2

–3

–4

100k 1G1M

FLATNESS

2V p-p

2V p-p

200mV p-p

10M 100M

FREQUENCY – Hz

200mV p-p

Figure 6. Frequency Response

–10

RL = 1kV
R

= 37.5V

–20

S

–30

–40

–50

–60

–70

CROSSTALK – dB

–80

–90

–100

300k 200M1M 10M 100M

ALL HOSTILE CROSSTALK

V

= 632mV p-p

IN

ADJACENT CHANNEL

CROSSTALK

V

= 632mV p-p

IN

FREQUENCY – Hz

+0.5

+0.4

+0.3

+0.2

+0.1

0

–0.1

–0.2

–0.3

100mV p-p

25mV/DIV

FLATNESS – dB

100ns/DIV

Figure 9. Step Response, 100 mV Step

0

VIN = 2V p-p, RL = 150V

–10
–20

–30
–40

–50
–60
–70

HARMONIC DISTORTION – dB

–80
–90

–100

100k 1M 10M 100M

Figure 8. Total Harmonic Distortion

Figure 7. Crosstalk vs. Frequency

2ND HARMONIC

3RD HARMONIC

FREQUENCY – Hz

Figure 10. Step Response, 2 V Step

Figure 11. Settling Time

–8–

REV. A

5
4
3
2
1

0
20
10

0

–10
–20

1V/DIV

10mV/DIV

50ns/DIV

FREQUENCY – Hz

–50
–60

–150

100k 500M1M 10M 100M

–90

–120

–130

–140

–70

–80

–110

–100

OFF ISOLATION – dB

VIN = 2V p-p

OUTPUT IMPEDANCE – Ω

FREQUENCY – Hz

10,000

0.1
100k

500M1M 10M 100M

100

1

1000

10

–20

–30

–40

–50

–60

POWER SUPPLY REJECTION – dB

–70

10k 10M100k 1M

FREQUENCY – Hz

Typical Performance Characteristics–

AD8116

Figure 12. PSRR vs. Frequency

316

100

31.6

nV/ Hz

10

3.16
10 100M100

1k 10k 100k 1M 10M

FREQUENCY – Hz

Figure 13. Voltage Noise vs. Frequency

10M

1M

Figure 15. Switching Transient (Glitch)

Figure 16. Off Isolation, Input-Output

100k

10k

OUTPUT IMPEDANCE – ⍀

1k

REV. A

100

100k

Figure 14. Output Impedance, Disabled

FREQUENCY – Hz

500M1M 10M 100M

Figure 17. Output Impedance, Enabled

–9–

AD8116

VOUT

100mV, 50ns

TEMPERATURE – 8C

2.0

–2.0

–60 100–40 –20 0 20 40 60 80

1.5

0.0

–0.5

–1.0

–1.5

1.0

0.5

V

OS

– mV

10M

1M

100k

10k

INPUT IMPEDANCE – V

1k

100

30k

100k 500M1M 10M 100M

FREQUENCY – Hz

Figure 18. Input Impedance vs. Frequency

+15

VIN = 200mV

+12

RL = 150V

+9
+6
+3

0

GAIN – dB

–3

–6
–9

–12
–15

100k 500M1M 10M 100M

30k

FREQUENCY – Hz

30pF

18pF

12pF

Figure 19. Frequency Response vs. Capacitive Load

+0.5

VIN = 200mV

+0.4

RL = 150V

+0.3
+0.2

+0.1

0

–0.1

FLATNESS – dB

–0.2
–0.3

–0.4
–0.5

100k 1M 10M 100M30k

FREQUENCY – Hz

CL = 30pF

CL = 18pF

CL = 12pF

Figure 20. Flatness vs. Capacitive Load

Figure 21. Switching Time

170
160
150

140
130
120
110
100

90
80
70

FREQUENCY

60
50

40
30

20
10

0

–0.035 0.025–0.025 –0.015 –0.005 0.005 0.015

OFFSET VOLTAGE – Volts

Figure 22. Offset Voltage Distribution

Figure 23. Offset Voltage Drift vs. Temperature

–10–

REV. A

AD8116

THEORY OF OPERATION

Loading Data

Data to control the switches is clocked serially into an 80-bit
shift register and then transferred in parallel to an 80-bit latch.
The falling edge of CLK (the serial clock input) loads data into
the shift register. The first five bits of the 80 bits are loaded via
DATA IN (the serial data input) program OUT15. The first of
the five bits (D4) enables or disables the output. The next four
bits (D3–D0, D3 = MSB, D0 = LSB) determine which one of
the 16 inputs will be connected to OUT15 (only one of the 16
inputs can be connected to a given output). The remaining bits
program OUT14 thru OUT00.

After the shift register is filled with the new 80 bits of control
data, UPDATE is activated (low) to transfer the data to the
parallel latches. The switch control latches are static and will
hold their data as long as power is applied.

To extend the number of switches in an array, the DATA
OUT and DATA IN pins of multiple AD8116s can be daisy­chained together. The DATA OUT pin is the end of the shift
register and may be directly connected to the DATA IN pin of
the follow-on AD8116. CE can be used to control the clocking
of data into selected devices.

Serial Logic

The AD8116 employs a serial interface for programming the
state of the crosspoint array. The 80-bit shift register (Figure 4)
consists of static D flip-flops while the parallel latch uses transpar­ent latches that are latched by a logic high state of UPDATE,
and transparent on logic low of the same signal. The 4-to-16
decoder is a small current-mode multilevel gate array that steers
a small select current to the selected point in the crosspoint array.

The RESET signal is connected to only the enable/disable bit on
each output buffer. This means that the AD8116 will have a
random configuration on power-up. In normal operation though,
RESET and UPDATE can be used together to alternately en-
able and disable an entire array at once, if desired.

Separate chip enable (CE), update (UPDATE) and serial data
out (DATA OUT) signals allow several options for program­ming larger arrays of AD8116s. The function of each bit in the
80-bit word that programs the state of the AD8116 is shown in
Figure 4. In normal operation, the DATA OUT pin of one
AD8116 is connected to the DATA IN of the next. In this way, for
example, an array of eight AD8116s would be programmed with
one 640-bit sequence. In this mode CE is logic low and the
CLK and UPDATE pins are connected in parallel.

In one alternate mode of programming, the CE pin can be used
to select one AD8116 at a time. This might be desirable when
the ability to program just one device at a time is required. In
this mode CLK, UPDATE and DATA IN are all connected in
parallel. The user then selects each AD8116 in turn (with the
CE signal) and programs it with the desired data. Larger arrays
can also be programmed by connecting each DATA IN signal to
a larger parallel bus. In this way only 80 clock cycles would be
needed to program the entire array. The logic signals are con­figured so that all programming can be accomplished with
synchronous logic and a continuous clock, so that no missing
cycles or delays need be generated.

APPLICATIONS
Multichannel Video

The excellent video specifications of the AD8116 make it an
ideal candidate for creating composite video crosspoint switches.
These can be made quite dense by taking advantage of the
AD8116’s high level of integration and the fact that composite
video requires only one crosspoint channel per system video
channel. There are, however, other video formats that can be
routed with the AD8116 requiring more than one crosspoint
channel per video channel.

Some systems use twisted pair wiring to carry video signals.
These systems utilize differential signals and can lower costs
because they use lower cost cables, connectors and termination
methods. They also have the ability to lower crosstalk and reject
common-mode signals, which can be important for equip­ment that operates in noisy environments or where common­mode voltages are present between transmitting and receiving
equipment.

In such systems, the video signals are differential; there is a
positive and negative (or inverted) version of the signals. These
complementary signals are transmitted onto each of the two
wires of the twisted pair, yielding a first order zero common­mode voltage. At the receive end, the signals are differentially
received and converted back into a single-ended signal.

When switching these differential signals, two channels are
required in the switching element to handle the two differential
signals that make up the video channel. Thus, one differential
video channel is assigned to a pair of crosspoint channels, both
input and output. For a single AD8116, eight differential video
channels can be assigned to the 16 inputs and 16 outputs. This

will effectively form an 8 × 8 differential crosspoint switch.

Programming such a device will require that inputs and outputs
be programmed in pairs. This information can be deduced by
inspection of the programming format of the AD8116 and the
requirements of the system.

There are other analog video formats requiring more than one
analog circuit per video channel. One two-circuit format that is
more commonly being used in systems such as satellite TV,
digital cable boxes and higher quality VCRs, is called S-video or
Y/C video. This format carries the brightness (luminance or Y)
portion of the video signal on one channel and the color
(chrominance or C) on a second channel.

Since S-video also uses two separate circuits for one video chan­nel, creating a crosspoint system requires assigning one video
channel to two crosspoint channels as in the case of a differen­tial video system. Aside from the nature of the video format,
other aspects of these two systems will be the same.

There are yet other video formats using three channels to carry
the video information. Video cameras produce RGB (red, green,
blue) directly from the image sensors. RGB is also the usual
format used by computers internally for graphics. RGB can also
be converted to Y, R-Y, B-Y format, sometimes called YUV
format. These three-circuit video standards are referred to as
component analog video.

The three-circuit video standards require three crosspoint chan­nels per video channel to handle the switching function. In a
fashion similar to the two-circuit video formats, the inputs and
outputs are assigned in groups of three and the appropriate logic
programming is performed to route the video signals.

REV. A

–11–

AD8116

IN OUT

AD8116

IN

OUT

AD8116

16

0–15

IN

AD8116

IN OUT

AD8116

16

16–31

16

16

OUT 16–31

0–15

16–31

IN

IN

OUT 0–15

OUT

IN

OUT

AD8116

IN OUT

AD8116

IN

AD8116

16

0–15

IN OUT

AD8116

IN

AD8116

IN

AD8116

16

16–31

IN

AD8116

IN

AD8116

IN

AD8116

16

32–47

16 16 16

OUT 0–15

OUT 16–31

OUT 32–47

IN

IN

IN

OUT

OUT OUT

OUT OUT OUT

Creating Larger Crosspoint Arrays

The AD8116 is a high density building block for crosspoint

arrays over 256 × 256. Various features such as output disable,

chip enable, serial data out and multiple pinouts for logic signals
are very useful for the creation of these larger arrays.

The first consideration in constructing a larger crosspoint is to
determine the minimum number of devices that are required.

The 16 × 16 architecture of the AD8116 contains 256 “points,”
which is a factor of four greater than an 8 × 8 crosspoint and a
factor of 64 greater than a 4 × 1 crosspoint. The PC board area

and power consumption savings are readily apparent when
compared to using these smaller devices.

For a nonblocking crosspoint, the number of points required is
the product of the number of inputs multiplied by the number
of outputs. Nonblocking requires that the programming of a

Using additional crosspoint devices in the design can lower the
number of outputs that have to be wire-ORed together. Figure
26 shows a block diagram of a system using ten AD8116s to

create a nonblocking 128 × 16 crosspoint that restricts the wire-

ORing at the output to only four outputs. This will prevent an
enabled output from having to drive a large number of disabled
devices. Additionally, by using the lower eight outputs from

each of the two Rank 2 AD8116s, a blocking 128 × 32 crosspoint

array can be realized.

There are, however, some drawbacks to this technique. The
offset voltages of the various cascaded devices will accumulate
and the bandwidth limitations of the devices will compound. In
addition, the extra devices will consume more current and take
up more board space. Once again, the overall system design
specifications will determine how to make the various trade-offs.

given input to one or more outputs does not restrict the avail­ability of that input to be a source for any other outputs.

Thus a 32 × 32 crosspoint will require 1024 points. This number is

then divided by 256, or the number of points in one AD8116
device, to yield four in this case. This says that the minimum

number of 16 × 16 devices required for a fully programmable
32 × 32 crosspoint is four.

Some nonblocking crosspoint architectures will require more
than this minimum as calculated above. Also, there are blocking
architectures that can be constructed with fewer devices than this
minimum. These systems have connectivity available on a statis­tical basis that is determined when designing the overall system.

The basic concept in constructing larger crosspoint arrays is to
connect inputs in parallel in a horizontal direction and to “wire­OR” the outputs together in the vertical direction. The meaning
of horizontal and vertical can best be understood by looking at a

Figure 24. 32 × 32 Crosspoint Array Using Four AD8116s

diagram. Figure 24 illustrates this concept for a 32 × 32 crosspoint
array. A 48 × 48 crosspoint is illustrated in Figure 25.

The 32 × 32 crosspoint requires each input driver drive two

inputs in parallel and each output be wire-ORed with one other

output. The 48 × 48 crosspoint requires driving three inputs in

parallel and having the outputs wire-ORed in groups of three. It
is required of the system programming that only one output of a
wired-OR node be active at a time.

It is not essential that crosspoint architectures be square. For

example, a 64 × 16 crosspoint array can be constructed with

four AD8116s by driving each input with a separate signal and
wire-ORing together the corresponding outputs of each device.
It can be seen, however, that by going to larger arrays the
number of disabled outputs an active output has to drive
starts to increase.

At some point, the number of outputs that are wire-ORed be­comes too great to maintain system performance. This will vary
according to which system specifications are most important.

For example, a 128 × 16 crosspoint can be created with eight

AD8116s. This design will have 128 separate inputs and have
the corresponding outputs of each device wire-ORed together
in groups of eight.

Figure 25. 48 × 48 Crosspoint Array Using Nine AD8116s

–12–

REV. A

AD8116

RANK 1

IN 0–15

IN 16–31

IN 32–47

IN 48–63

IN 64–79

IN 80–95

IN 96–111

IN 112–127

(128:32)

16

16

16

16

16

16

16

16

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

RANK 2

32:16 NONBLOCKING

(32:32 BLOCKING)

FOUR AD8116 OUTPUTS
WIRE-ORED TOGETHER

NONBLOCKING

OUTPUTS

8

OUT 0–16

8

8

ADDITIONAL
16 OUTPUTS

8

Figure 26. Nonblocking 128 × 16 Array (128 × 32 Blocking)

Logic Operation

There are two basic options for controlling the logic in multi­crosspoint arrays. One is to serially connect the data paths
(DATA OUT to DATA IN) of all the devices and tie all the
CLK and UPDATE signals in parallel. CE can be tied low for
all the devices. A long serial sequence with the desired pro­gramming data consisting of 80 bits times the number of
AD8116 devices can then be shifted through all the parallel
devices by using the DATA IN of the first device and the CLK.
When finished clocking in the data, UPDATE can be pulled low
to program all the device crosspoint matrices.

This technique has an advantage in that a separate CE signal
is not required for each chip, but has a disadvantage in that
several chips’ data cannot be shifted in parallel. In addition, if
another device is added into the system between already existing
devices, the programming sequence will have to be lengthened
at some midpoint to allow for programming of the added device.

The second programming method is to connect all the CLK
and the DATA IN pins in parallel and use the CE pins in se­quence to program each device. If a byte or 16-bit word of data
is available for providing the programming data, then multiple
AD8116s can be programmed in parallel with just 80 clock
cycles. This method can be used to speed up the programming
of large arrays. Of course, in a practical system, various combi­nations of these basic methods can be used.

Power-On Reset

Most systems will want all the AD8116s to be in the reset state
(all outputs disabled) when power is applied to the system. This
ensures that two outputs that are wire-ORed together will not
fight each other at power up.

The power-on reset function can be implemented by adding a

0.1 µF capacitor from the RESET pin to ground. This will hold

this signal low after the power is applied to reset the device. An

on-chip 20 kΩ resistor from RESET to DVCC will charge the

capacitor to the logical high state. If several AD8116s are used,
the pull-up resistors will be in parallel, so a larger value capaci­tance should be used.

If the system requires the ability to be reset while power is still
applied, the RESET driver will have to be able to charge and
discharge this capacitance in the required time. With too many
devices in parallel, this might become more difficult; if this
occurs, the reset circuits should be broken up into smaller sub­sets with each controlled by a separate driver.

CROSSTALK

Many systems, such as broadcast video, that handle numerous
analog signal channels have strict requirements for keeping the
various signals from influencing any of the others in the system.
Crosstalk is the term used to describe the coupling of the signals
of other nearby channels to a given channel.

When there are many signals in close proximity in a system, as
will undoubtedly be the case in a system that uses the AD8116,
the crosstalk issues can be quite complex. A good understanding
of the nature of crosstalk and some definition of terms is required
in order to specify a system that uses one or more AD8116s.

Types of Crosstalk

Crosstalk can be propagated by means of any of three methods.
These fall into the categories of electric field, magnetic field and
sharing of common impedances. This section will explain these
effects.

Every conductor can be both a radiator of electric fields and a
receiver of electric fields. The electric field crosstalk mechanism
occurs when the electric field created by the transmitter propagates
across a stray capacitance and couples with the receiver and
induces a voltage. This voltage is an unwanted crosstalk signal
in any channel that receives it.

Currents flowing in conductors create magnetic fields that circu­late around the currents. These magnetic fields will then gener­ate voltages in any other conductors whose paths they link. The
undesired induced voltages in these other channels are crosstalk
signals. The channels that crosstalk can be said to have a
mutual inductance that couples signals from one channel to
another.

The power supplies, grounds and other signal return paths of a
multichannel system are generally shared by the various channels.
When a current from one channel flows in one of these paths, a
voltage that is developed across the impedance becomes an
input crosstalk signal for other channels that share the common
impedance.

All these sources of crosstalk are vector quantities, so the
magnitudes cannot be simply added together to obtain the total
crosstalk. In fact, there are conditions where driving additional
circuits in parallel in a given configuration can actually reduce
the crosstalk.

Areas of Crosstalk

For a practical AD8116 circuit, it is required that it be mounted
to some sort of circuit board in order to connect it to power
supplies and measurement equipment. Great care has been
taken to create a characterization board (also available as an
evaluation board) that adds minimum crosstalk to the intrinsic
device. This, however, raises the issue that a system’s crosstalk
is a combination of the intrinsic crosstalk of the devices and the
circuit board to which they are mounted. It is important to try

REV. A

–13–

AD8116

to separate these two areas of crosstalk when attempting to
minimize its effect.

In addition, crosstalk can occur among the input circuits to a
crosspoint and among the output circuits. Techniques will be
discussed for diagnosing which part of a system is contributing
to crosstalk.

Measuring Crosstalk

Crosstalk is measured by applying a signal to one or more channels
and measuring the relative strength of that signal on a desired
selected channel. The measurement is usually expressed as dB
down from the magnitude of the test signal. The crosstalk is
expressed by:

|XT| = 20 log

(Asel(s)/Atest(s))

10

where s = jω is the Laplace transform variable, Asel(s) is the

amplitude of the crosstalk-induced signal in the selected channel
and Atest(s) is the amplitude of the test signal. It can be seen
that crosstalk is a function of frequency, but not a function of
the magnitude of the test signal. In addition, the crosstalk signal
will have a phase relative to the test signal associated with it.

A network analyzer is most commonly used to measure crosstalk
over a frequency range of interest. It can provide both magni­tude and phase information about the crosstalk signal.

As a crosspoint system or device grows larger, the number
of theoretical crosstalk combinations and permutations can

become extremely large. For example, in the case of the 16 × 16

matrix of the AD8116, we can examine the number of crosstalk
terms that can be considered for a single channel, say IN00
input. IN00 is programmed to connect to one of the AD8116
outputs where the measurement can be made.

First, we can measure the crosstalk terms associated with driv­ing a test signal into each of the other 15 inputs one at a time.
We can then measure the crosstalk terms associated with driving
a parallel test signal into all 15 other inputs taken two at a time
in all possible combinations; and then three at a time, etc., until,
finally, there is only one way to drive a test signal into all 15 other
inputs.

Each of these cases is legitimately different from the others and
might yield a unique value depending on the resolution of the
measurement system, but it is hardly practical to measure all
these terms and then to specify them. In addition, this describes
the crosstalk matrix for just one input channel. A similar crosstalk
matrix can be proposed for every other input. In addition, if
the possible combinations and permutations for connecting
inputs to the other (not used for measurement) outputs are
taken into consideration, the numbers rather quickly grow to
astronomical proportions. If a larger crosspoint array of multiple
AD8116s is constructed, the numbers grow larger still.

Obviously, some subset of all these cases must be selected to be
used as a guide for a practical measure of crosstalk. One common
term is “all hostile” crosstalk. This term means that all other
system channels are driven in parallel, and the crosstalk to the
selected channel is measured. In general, this will yield the
worst crosstalk number, but this is not always the case.

Other useful crosstalk measurements are those created by one
nearest neighbor or by the two nearest neighbors on either side.
These crosstalk measurements will generally be higher than
those of more distant channels, so they can serve as a worst case
measure for any other one-channel or two-channel crosstalk
measurements.

–14–

Input and Output Crosstalk

The flexible programming capability of the AD8116 can be used
to diagnose whether crosstalk is occurring more on the input
side or the output side. Some examples are illustrative. A given
input channel (IN07 in the middle for this example) can be
programmed to drive OUT07. The input to IN07 is just
terminated to ground and no signal is applied.

All the other inputs are driven in parallel with the same test
signal (practically provided by a distribution amplifier), but all
other outputs except OUT07 are disabled. Since grounded IN07
is programmed to drive OUT07, there should be no signal
present. Any signal that is present can be attributed to the other
15 hostile input signals, because no other outputs are driven.
Thus, this method measures the all-hostile input contribution to
crosstalk into IN07. Of course, the method can be used for
other input channels and combinations of hostile inputs.

For output crosstalk measurement, a single input channel is
driven (IN00 for example) and all outputs other than a given
output (IN07 in the middle) are programmed to connect to
IN00. OUT07 is programmed to connect to IN15 which is
terminated to ground. Thus OUT07 should not have a signal
present since it is listening to a quiet input. Any signal measured
at the OUT07 can be attributed to the output crosstalk of the
other 15 hostile outputs. Again, this method can be modified to
measure other channels and other crosspoint matrix combinations.

Effect of Impedances on Crosstalk

The input side crosstalk can be influenced by the output
impedance of the sources that drive the inputs. The lower the
impedance of the drive source, the lower the magnitude of the
crosstalk. The dominant crosstalk mechanism on the input
side is capacitive coupling. The high impedance inputs do not
have significant current flow to create magnetically induced
crosstalk.

From a circuit standpoint, the input crosstalk mechanism looks
like a capacitor coupling to a resistive load. For low frequencies
the magnitude of the crosstalk will be given by:

where R

|XT| = 20 log

is the source resistance, CM is the mutual capacitance

S

[(RS C

10

) × s]

M

between the test signal circuit and the selected circuit, and s is
the Laplace transform variable.

From the equation it can be observed that this crosstalk mecha­nism has a high pass nature; it can be also minimized by reducing
the coupling capacitance of the input circuits and lowering
the output impedance of the drivers. If the input is driven from

a 75 Ω terminated cable, the input crosstalk can be reduced by

buffering this signal with a low output impedance buffer.

On the output side, the crosstalk can be reduced by driving a
lighter load. Although the AD8116 is specified with excellent

differential gain and phase when driving a standard 150 Ω video

load, the crosstalk will be higher than the minimum due to the
high output currents. These currents will induce crosstalk via
the mutual inductance of the output pins and bond wires of the
AD8116.

From a circuit standpoint, this output crosstalk mechanism
looks like a transformer with a mutual inductance between the
windings that drives a load resistor. For low frequencies, the
magnitude of the crosstalk is given by:

|XT| = 20 log

(Mxy × s/R

10

)

L

REV. A

AD8116

1

2

+V

S

AD8079AR

3

4

5

–V

S

1k⍀

1k⍀

AD8116

OUTXX

OUTYY

AD8116

OUTZZ

OUTWW

–5V

0.1␮F

10␮F

+

75⍀

75⍀

75⍀

75⍀

8

0.1␮F 10␮F
+

+5V

TO OTHER
AD8116 OUTPUTS

G = +2

G = +2

where Mxy is the mutual inductance of output x to output y and

is the load resistance on the measured output. This crosstalk

R

L

mechanism can be minimized by keeping the mutual inductance
low and increasing R

. The mutual inductance can be kept low

L

by increasing the spacing of the conductors and minimizing
their parallel length.

One way to increase the load resistance is to buffer the outputs
with a high input impedance buffer as shown in Figure 27. The
AD8079AR is a dual buffer that can be strapped for a gain of +2
(B grade = +2.2). This offsets the halving of the signal when
driving a standard back-terminated video cable.

The input of the buffer requires a path for bias current. This can

be provided by a 500 Ω to 5 kΩ resistor to ground. This resistor

also serves the purpose of biasing the outputs of the crosspoints
at zero volts when all the outputs are disabled.

In addition, the load resistor actually lowers the crosstalk com­pared to the conditions of the AD8116 outputs driving a high

impedance (greater than 10 kΩ) or driving a video load (150 Ω).

This is because the electric field crosstalk that dominates in the
high impedance case has a phase of –90 degrees, while the mag­netic field crosstalk that dominates in the video load case has a

phase of +90 degrees. With a 500 Ω to 5 kΩ load, the contribu-

tions from each of these is roughly equal, and there is some
cancellation of crosstalk due to the phase differences.

PCB Layout

Extreme care must be exercised to minimize additional crosstalk
generated by the system circuit board(s). The areas that must be
carefully detailed are grounding, shielding, signal routing and
supply bypassing.

The packaging of the AD8116 is designed to help keep the
crosstalk to a minimum. Each input is separated from each
other’s input by an analog ground pin. All of these AGNDs
should be directly connected to the ground plane of the circuit
board. These ground pins provide shielding, low impedance
return paths and physical separation for the inputs. All of these
help to reduce crosstalk.

Each output is separated from its two neighboring outputs by
analog supply pins of either polarity. Each of these analog sup­ply pins provides power to the output stages of only the two
adjacent outputs. These supply pins provide shielding, physical
separation and low impedance supply for the channel outputs.
Individual bypassing of each of these supply pins with a

0.01 µF chip capacitor directly to the ground plane minimizes

high frequency output crosstalk via the mechanism of sharing
common impedances.

Each output also has an on-chip compensation capacitor that
is individually tied to a package pin via the signals called
AGND00 through AGND15. This technique reduces crosstalk
by preventing the currents that flow in these paths from sharing
a common impedance on the IC and in the package pins. These
AGNDxx signals should all be connected directly to the ground
plane.

The input and output signals minimize crosstalk if they are
located between ground planes on layers above and below, and
separated by ground in between. Vias should be located as close
to the IC as possible to carry the inputs and outputs to the inner
layer. The only place the input and output signals surface is at
the input termination resistors and the output series back termi­nation resistors. These signals should also be separated, to the
extent possible, as soon as they emerge from the IC package.

Figure 27. Buffering Wired OR Outputs with the AD8079

Evaluation Board

A four-layer evaluation board for the AD8116 is available. This
board has been carefully laid out and tested to demonstrate the
specified high speed performance of the device. Figure 28 shows
the schematic of the evaluation board. Figure 29 shows the
component side silk-screen. The layouts of the board’s four
layers are given in Figures 30, 31, 32 and 33.

The evaluation board package includes the following:

• Fully populated board with BNC-type connectors.

• Windows

®

based software for controlling the board from a

PC via the printer port.

• Custom cable to connect evaluation board to PC.

• Disk containing Gerber files of board layout.

REV. A

Windows is a registered trademark of Microsoft Corporation.

–15–

AD8116

AGND

*6-PIN 0.100 CENTER HEADER

MOLEX PART NR. 22-23-2061

MATING CONNECTOR

MOLEX PART NR. 22-01-03067

INPUT 00

75⍀

INPUT 01

75⍀

INPUT 02

75⍀

INPUT 03

75⍀

INPUT 04

75⍀

INPUT 05

75⍀

INPUT 06

75⍀

INPUT 07

75⍀

INPUT 08

75⍀

INPUT 09

75⍀

INPUT 10

75⍀

INPUT 11

75⍀

INPUT 12

75⍀

INPUT 13

75⍀

INPUT 14

75⍀

INPUT 15

75⍀

NCNCNCNCNC

126 125 124 123 122 121

1

AGND

IN00

AGND

IN01

AGND

IN02

AGND

IN03

AGND

IN04

AGND

IN05

AGND

IN06

AGND

IN07

AGND

IN08

AGND

IN09

AGND

IN10

AGND

IN11

AGND

IN12

AGND

IN13

AGND

IN14

AGND

IN15

33

CLIP-ON

DATA IN

AGND

*

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

TEST POINTS

DIGITAL INTERFACE

CONNECTOR

DGND

CLK

UPDATE

DATA OUT

RESET

++ ++

10␮F

NC

127

CE

10␮F

16

0.01␮F 0.01␮F

0.01␮F

DVCC

119

DVEE

10␮F

116–
118 120

AVEE

DGND

113–

115

10␮F

POWER SUPPLY

CONNECTOR

CLIP-ON TEST POINTS

0.01␮F

AVCC

AD8116JST

DGND

DATA IN

UPDATE

61

DATA OUT

CLKCERESET

NC = NO CONNECT

NC

DVCC

NC

DVEE

0.01
␮F

AV

EE

AVEE

AV

105–
112

AVCC

46–4843–45423439363540383741

CC

*

NC

97–104,

NC

0.01
␮F

NC

NC

49–
55

128

AVCC00

AGND

OUT00

AVEE00/01

OUT01

AVCC01/02

OUT02

AVEE02/03

OUT03

AVCC03/04

OUT04

AVEE04/05

OUT05

AVCC05/06

OUT06

AVEE06/07

OUT07

AVCC07/08

OUT08

AVEE08/09

OUT09

AVCC09/10

OUT10

AVEE10/11

OUT11

AVCC11/12

OUT12

AVEE12/13

OUT13

AVCC13/14

OUT14

AVEE14/15

OUT15

AVCC

AGND

56–63

AV

0.1␮F

TO PINS 96,92,88,84

(AVCC)

0.01␮F

0.01␮F

0.01␮F

0.01␮F

0.01µF

0.01␮F

0.01␮F

0.01␮F

0.01␮F

0.01␮F

0.01␮F

0.01␮F

0.01␮F

0.01␮F

0.01␮F

0.01␮F

TO PINS

78,74,70,66

(AVEE)

0.1␮F

AV

AV

AV

AV

AV

AV

AV

AV

AV

AV

AV

AV

AV

AV

AV

AV

96

95

94

93

92

91

90

89

88

87

86

85

84

83

82

81

80

79

78

77

76

75

74

73

72

71

70

69

68

67

66

65

64

0.01
␮F

CC

TO PINS 94,90,86,82

(AVEE)

CC

75⍀

EE

75⍀

CC

75⍀

EE

75⍀

CC

75⍀

EE

75⍀

CC

75⍀

EE

75⍀

CC

75⍀

EE

75⍀

CC

75⍀

EE

75⍀

CC

75⍀

EE

75⍀

CC

75⍀

EE

75⍀

TO PINS

80,76,72,68

(AVCC)

0.1␮F

0.1␮F

OUTPUT 00

OUTPUT 01

OUTPUT 02

OUTPUT 03

OUTPUT 04

OUTPUT 05

OUTPUT 06

OUTPUT 07

OUTPUT 08

OUTPUT 09

OUTPUT 10

OUTPUT 11

OUTPUT 12

OUTPUT 13

OUTPUT 14

OUTPUT 15

Figure 28. Evaluation Board Schematic

–16–

REV. A

AD8116

REV. A

Figure 29. Component Side Silkscreen

–17–

AD8116

Figure 30. Board Layout (Top Layer)

–18–

REV. A

AD8116

REV. A

Figure 31. Board Layout (Signal Layer)

–19–

AD8116

Figure 32. Board Layout (Power Layer)

–20–

REV. A

AD8116

REV. A

Figure 33. Board Layout (Bottom Layer)

–21–

AD8116

Optimized for video applications, all signal inputs and outputs

are terminated with 75 Ω resistors. Figure 34 shows a cross-

section of one of the input or output tracks along with the ar­rangement of the PCB layers. It should be noted that unused
regions of the four layers are filled up with ground planes. As a
result, the input and output traces, in addition to having con­trolled impedances, are well shielded.

w = 0.008"

(0.2mm)

TOP LAYER

b = 0.0132"
(0.335mm)

SIGNAL LAYER

POWER LAYER

d = 0.0132"
(0.335mm)

BOTTOM LAYER

a = 0.008"

(0.2mm)

t = 0.00135" (0.0343mm)

c = 0.028"

(0.714mm)

Figure 34. Cross Section of Input and Output Traces

The board has 32 BNC type connectors: 16 inputs and 16 outputs.
The connectors are arranged in two crescents around the device.
As can be seen from Figure 31, this results in all sixteen input
signal traces and all sixteen signal output traces having the same
length. This is useful in tests such as All-Hostile Crosstalk
where the phase relationship and delay between signals needs to
be maintained from input to output.

The four power supply pins AVCC, DVCC, AVEE and DVEE

should be connected to good quality, low noise, ±5 V supplies.
Where the same ±5 V power supplies are used for analog and

digital, separate cables should be run for the power supply to the
evaluation board’s analog and digital power supply pins.

As can be seen in Figure 35, there is extensive power supply
decoupling on the evaluation board. Figure 35 shows the
location of all the decoupling capacitors relative to the AD8116’s

pins. Four large 10 µF capacitors are located near the evalua-

tion board’s power supply connection terminals. These de­couple the AVCC, DVCC, AVEE and DVEE supplies. Because
it is required that the voltage difference between DGND and
AGND never exceed 0.7 V, these grounds are connected by
two antiparallel diodes. On the output side of the device (Pin 65
to Pin 96), the sixteen output pins are interleaved with the
AVCC and AVEE power supply pins. Each of these pins is

locally decoupled with a 0.01 µF capacitor. These pins are also
decoupled in groups of four with 0.1 µF capacitors. Due to

space constraints the power supply Pins 34 (DVCC) and 42
(DVEE) are neither connected nor decoupled. These pins are,
however, internally connected to DVCC and DVEE (Pins 127
and 119).

As a general rule, each power supply pin (or group of adjacent

power supply pins) should be locally decoupled with a 0.01 µF

capacitor. If there is a space constraint, it is more important to
decouple analog power supply pins before digital power supply

pins. A 0.1 µF capacitor, located reasonably close to the pins,

can be used to decouple a number of power supply pins. Finally

a 10 µF capacitor should be used to decouple power supplies as

they come on to the board.

–22–

REV. A

AD8116

DVCC DVEE AVEE

10␮F10␮F10␮F

128 127 119 113 97

1

*** *

0.1␮F

AVCC

10␮F

0.1␮F

96

*

*

*

*

*

*

*

32

NC = NO CONNECT

NC

(DVCC)

NC

(DVEE)

0.1␮F

*

*

*

*

*

*

*

*

*

0.1␮F

*

65

6448423433

*

*

*

0.01␮F

REV. A

Figure 35. Detail of Decoupling on Evaluation Board

–23–

AD8116

Controlling the Evaluation Board from a PC

The evaluation board include Windows-based control software
and a custom cable that connects the board’s digital interface
to the printer port of the PC. The wiring of this cable is shown
in Figure 36. The software requires Windows 3.1 or later to
operate. To install the software, insert the disk labeled “Disk #1
of 2” in the PC and run the file called SETUP.EXE. Additional
installation instructions will be given on-screen. Before begin­ning installation, it is important to terminate any other Win­dows applications that are running.

MOLEX 0.100" CENTER

CRIMP TERMINAL HOUSING

RESET

CLK

CE

UPDATE

DATA IN

DGND

D-SUB-25

EVALUATION BOARD PC

1

6

TERMINAL HOUSING

2
3
4
5
6
25

MOLEX

3
1
4
5
2
6

SIGNAL

CE
RESET
UPDATE

DATA IN
CLK
DGND

D-SUB 25 PIN

(MALE)

1

14

25

13

can be connected with one or more outputs by simply clicking

on the appropriate radio buttons in the 16 × 16 on-screen array.

Each time a button is clicked on, the software automatically
sends and latches the required 80-bit data stream to the
evaluation board. An output can be turned off by clicking the
appropriate button in the Off column. To turn off all outputs,
click on RESET.

The software offers volatile and nonvolatile storage of configu­rations. For volatile storage, up to two configurations can be
stored and recalled using the Memory 1 and Memory 2 Buffers.
These function in an identical fashion to the memory on a
pocket calculator. For nonvolatile storage of a configuration, the
Save Setup and Load Setup functions can be used. This stores
the configuration as a data file on disk.

Overshoot on PC Printer Ports’ Data Lines

The data lines on some printer ports have excessive overshoot.
Overshoot on the pin that is used as the serial clock (Pin 6 on
the D-Sub-25 connector) can cause communication problems.
This overshoot can be eliminated by connecting a capacitor
from the CLK line on the evaluation board to ground. A pad
has been provided on the solder-side of the evaluation board to
allow this capacitor to be soldered into place. Depending upon
the overshoot from the printer port, this capacitor may need to

be as large as 0.01 µF.

Figure 36. Evaluation Board-PC Connection Cable

When you launch the crosspoint control software, you will be
asked to select the printer port you are using. Most modern PCs
have only one printer port, usually called LPT1; however, some
laptop computers use the PRN port.

Figure 37 shows the main screen of the control software in its
initial reset state (all outputs off). Using the mouse, any input

–24–

REV. A

AD8116

REV. A

Figure 37. Screen Display of Control Software

–25–

AD8116

OUTLINE DIMENSIONS

Dimensions shown in millimeters and (inches).

Metric measurements are not rounded. English measurements are rounded.

128-Lead Plastic LQFP

(ST-128A)

0.030 (0.75)

0.018 (0.45)

SEATING

PLANE

STANDOFF

0.003 (0.08)
MAX

0.063 (1.60)
TYP

0.006 (0.15)

0.002 (0.05)

128
1

32

33

0.057 (1.45)

0.053 (1.35)

0.630 (16.00) BSC

0.551 (14.00) BSC

0.488 (12.40) BSC

TOP VIEW

(PINS DOWN)

0.016 (0.40)
BSC

0.009 (0.23)

0.005 (0.13)

97

96

65

64

0.488 (12.40) BSC

0.551 (14.00) BSC

0.630 (16.00) BSC

7°
0°

C2441a–2–5/99

–26–

PRINTED IN U.S.A.

REV. A