Analog Devices AD8114 5 a Datasheet

Low Cost 225 MHz

a

FEATURES
16  16 High-Speed Nonblocking Switch Arrays

AD8114; G = +1

AD8115; G = +2
Serial or Parallel Programming of Switch Array
Serial Data Out Allows “Daisy Chaining” of Multiple

16  16s to Create Larger Switch Arrays
High Impedance Output Disable Allows Connection of

Multiple Devices Without Loading the Output Bus
For Smaller Arrays See Our AD8108/AD8109 (8  8) or

AD8110/AD8111 (16  8) Switch Arrays
Complete Solution

Buffered Inputs

Programmable High Impedance Outputs

16 Output Amplifiers, AD8114 (G = +1), AD8115 (G = +2)

Drives 150  Loads
Excellent Video Performance

25 MHz, 0.1 dB Gain Flatness

0.05%/0.05 Differential Gain/Differential Phase Error
= 150 )

(R

L

Excellent AC Performance

–3 dB Bandwidth: 225 MHz

Slew Rate: 375 V/s
Low Power of 700 mW (2.75 mW per Point)
Low All Hostile Crosstalk of –70 dB @ 5 MHz
Reset Pin Allows Disabling of All Outputs (Connected

Through a Capacitor to Ground Provides “Power-On”

Reset Capability)

100-Lead LQFP Package (14 mm  14 mm)

APPLICATIONS
Routing of High-Speed Signals Including:

Video (NTSC, PAL, S, SECAM, YUV, RGB)

Compressed Video (MPEG, Wavelet)

3-Level Digital Video (HDB3)

Datacomms

Telecomms

PRODUCT DESCRIPTION

The AD8114/AD8115 are high-speed 16 × 16 video crosspoint
switch matrices. They offer a –3 dB signal bandwidth greater than
200 MHz and channel switch times of less than 50 ns with 1%
settling. With –70 dB of crosstalk and –90 dB isolation (@ 5 MHz),
the AD8114/AD8115 are useful in many high-speed applications.
The differential gain and differential phase of better than 0.05%
and 0.05° respectively, along with 0.1 dB flatness out to 25 MHz
while driving a 75 Ω back-terminated load, make the AD8114/
AD8115 ideal for all types of signal switching.

16

16 Crosspoint Switches



AD8114/AD8115

*

FUNCTIONAL BLOCK DIAGRAM

SER/PAR

CLK

DATA IN

UPDATE

CE

RESET

AD8114/AD8115

16 INPUTS

D0 D1 D2 D3

80-BIT SHIFT REGISTER

PARALLEL LOADING

PARALLEL LATCH

DECODE

16  5:16 DECODERS

SWITCH
MATRIX

D4

WITH 5-BIT

80

80

256

OUTPUT
BUFFER

G = +1,

G = +2

SET
INDIVIDUAL
OR RESET
ALL OUTPUTS
TO "OFF"

16

ENABLE/DISABLE

A0
A1

A2
A3

DATA
OUT

16
OUTPUTS

The AD8114/AD8115 include 16 independent output buffers
that can be placed into a high impedance state for paralleling
crosspoint outputs so that off channels do not load the output
bus. The AD8114 has a gain of +1, while the AD8115 offers
a gain of +2. They operate on voltage supplies of ±5 V while
consuming only 70 mA of idle current. The channel switching
is performed via a serial digital control (which can accommo­date “daisy chaining” of several devices) or via a parallel control
allowing updating of an individual output without reprogram­ming the entire array.

The AD8114/AD8115 is packaged in 100-lead LQFP package
and is available over the extended industrial temperature range
of –40°C to +85°C.

*Patent Pending.

REV. A

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] © Analog Devices, Inc., 2001

AD8114/AD8115–SPECIFICATIONS

(VS = 5 V, TA = +25C, RL = 1 k unless otherwise noted)

AD8114 /AD8115

Parameter Conditions Min Typ Max Unit

DYNAMIC PERFORMANCE

–3 dB Bandwidth 200 mV p-p, R

2 V p-p, R

= 150 Ω 150/125 225/200 MHz

L

= 150 Ω 100/125 MHz

L

Gain Flatness 0.1 dB, 200 mV p-p, RL = 150 Ω 25/40 MHz

0.1 dB, 2 V p-p, R

Propagation Delay 2 V p-p, R

= 150 Ω 5ns

L

Settling Time 0.1%, 2 V Step, R

= 150 Ω 20/40 MHz

L

= 150 Ω 40 ns

L

Slew Rate 2 V Step, RL = 150 Ω 375/450 V/µs

NOISE/DISTORTION PERFORMANCE

Differential Gain Error NTSC or PAL, R

= 1 kΩ 0.05 %

L

NTSC or PAL, RL = 150 Ω 0.05 %

Differential Phase Error NTSC or PAL, R

= 1 kΩ 0.05 Degrees

L

NTSC or PAL, RL = 150 Ω 0.05 Degrees

Crosstalk, All Hostile f = 5 MHz –70/–64 dB

f = 10 MHz –60/–52 dB

Off Isolation, Input-Output f = 10 MHz, R

= 150 Ω, One Channel –90 dB

L

Input Voltage Noise 0.01 MHz to 50 MHz 16/18 nV/√Hz

DC PERFORMANCE

Gain Error No Load 0.05/0.2 0.08/0.6 %

RL = 1 kΩ 0.05/0.2 %
RL = 150 Ω 0.2/0.35 %

Gain Matching No Load, Channel-Channel 0.01/0.5 0.04/1 %

R

= 1 kΩ, Channel-Channel 0.01/0.5 %

L

Gain Temperature Coefficient 0.75/1.5 ppm/°C

OUTPUT CHARACTERISTICS

Output Impedance DC, Enabled 0.2 Ω

Disabled 10 MΩ

Output Disable Capacitance Disabled 5 pF
Output Leakage Current Disabled 1 µA
Output Voltage Range No Load ±3.0 ± 3.3 V
Voltage Range I

= 20 mA ±2.5 ± 3V

OUT

Short Circuit Current 65 mA

INPUT CHARACTERISTICS

Input Offset Voltage Worst Case (All Configurations) 3 15 mV

Temperature Coefficient 10 µV/°C

Input Voltage Range No Load ± 3/±1.5 ± 3.5 V
Input Capacitance Any Switch Configuration 5 pF
Input Resistance 110 MΩ
Input Bias Current Per Output Selected 2 5 µA

SWITCHING CHARACTERISTICS

Enable On Time 60 ns
Switching Time, 2 V Step 50% UPDATE to 1% Settling 50 ns
Switching Transient (Glitch) 20/30 mV p-p

POWER SUPPLIES

Supply Current AVCC, Outputs Enabled, No Load 70/80 mA

AVCC, Outputs Disabled 27/30 mA
AVEE, Outputs Enabled, No Load 70/80 mA
AVEE, Outputs Disabled 27/30 mA
DVCC, Outputs Enabled, No Load 16 mA

Supply Voltage Range ±4.5 to ±5.5 V
PSRR DC 64 80 dB

f = 100 kHz 66 dB
f = 1 MHz 46 dB

OPERATING TEMPERATURE RANGE

Temperature Range Operating (Still Air) –40 to +85 °C

θ

JA

Specifications subject to change without notice.

Operating (Still Air) 40 °C/W

–2–

REV. A

AD8114/AD8115

TIMING CHARACTERISTICS (Serial)

Limit

Parameter Symbol Min Typ Max Unit

Serial Data Setup Time t
CLK Pulsewidth t
Serial Data Hold Time t
CLK Pulse Separation, Serial Mode t
CLK to UPDATE Delay t
UPDATE Pulsewidth t
CLK to DATA OUT Valid, Serial Mode t

1

2

3

4

5

6

7

20 ns
100 ns
20 ns
100 ns
0ns
50 ns

200 ns

Propagation Delay, UPDATE to Switch On or Off – 50 ns
Data Load Time, CLK = 5 MHz, Serial Mode – 16 µs
CLK, UPDATE Rise and Fall Times – 100 ns
RESET Time – 200 ns

CLK

DATA IN

1 = LATCHED

UPDATE

0 = TRANSPARENT

DATA OUT

t

1

0

t1t

1

OUT7 (D4) OUT7 (D3) OUT00 (D0)

0

2

3

t

7

t

4

LOAD DATA INTO
SERIAL REGISTER
ON FALLING EDGE

t

5

TRANSFER DATA FROM SERIAL

REGISTER TO PARALLEL

LATCHES DURING LOW LEVEL

t

6

Figure 1. Timing Diagram, Serial Mode

Table I. Logic Levels

V

IH

RESET, SER/PAR RESET, SER/PAR RESET, SER/PAR RESET, SER/PAR
CLK, DATA IN, CLK, DATA IN, CLK, DATA IN, CLK, DATA IN,
CE, UPDATE CE, UPDATE DATA OUT DATA OUT CE, UPDATE CE, UPDATE DATA OUT DATA OUT

2.0 V min 0.8 V max 2.7 V min 0.5 V max 20 µA max –400 µA min –400 µA max 3.0 mA min

V

IL

V

OH

V

OL

I

IH

I

IL

I

OH

I

OL

REV. A

–3–

AD8114/AD8115

TIMING CHARACTERISTICS (Parallel)

Limit

Parameter Symbol Min Max Unit

Data Setup Time t
CLK Pulsewidth t
Data Hold Time t
CLK Pulse Separation t
CLK to UPDATE Delay t
UPDATE Pulsewidth t

1

2

3

4

5

6

20 ns
100 ns
20 ns
100 ns
0ns
50 ns

Propagation Delay, UPDATE to Switch On or Off – 50 ns
CLK, UPDATE Rise and Fall Times – 100 ns
RESET Time – 200 ns

t

4

t

5

t

6

CLK

D0–D4
A0–A2

1 = LATCHED

UPDATE

0 = TRANSPARENT

t

1

0

1

0

t

1

2

t

3

Figure 2. Timing Diagram, Parallel Mode

Table II. Logic Levels

V

IH

RESET, SER/PAR RESET, SER/PAR RESET, SER/PAR RESET, SER/PAR
CLK, D0, D1, D2, D3, CLK, D0, D1, D2, D3, CLK, D0, D1, D2, D3, CLK, D0, D1, D2, D3,
D4, A0, A1, A2, A3 D4, A0, A1, A2, A3 D4, A0, A1, A2, A3 D4, A0, A1, A2, A3
CE, UPDATE CE, UPDATE DATA OUT DATA OUT CE, UPDATE CE, UPDATE DATA OUT DATA OUT

2.0 V min 0.8 V max 2.7 V min 0.5 V max 20 µA max –400 µA min –400 µA max 3.0 mA min

V

IL

V

OH

V

OL

I

IH

I

IL

I

OH

I

OL

–4–

REV. A

AD8114/AD8115

WARNING!

ESD SENSITIVE DEVICE

ABSOLUTE MAXIMUM RATINGS

Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12.0 V

Internal Power Dissipation

2

AD8114/AD8115 100-Lead Plastic LQFP (ST) . . . . 2.6 W

Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±V

Output Short Circuit Duration

1

ORDERING GUIDE

Temperature Package Package

Model Range Description Option

S

AD8114AST –40°C to +85°C 100-Lead Plastic ST-100

. . . . . . . . . . . . . . . . . . . . . . Observe Power Derating Curves

Storage Temperature Range . . . . . . . . . . . . –65°C to +125°C

Lead Temperature Range (Soldering 10 sec) . . . . . . . . . 300°C

NOTES

1

Stresses above those listed under Absolute Maximum Ratings may cause perma-

nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.

2

Specification is for device in free air (TA = 25°C):

100-lead plastic LQFP (ST): θJA = 40°C/W.

AD8114-EVAL Evaluation Board
AD8115AST –40°C to +85°C 100-Lead Plastic ST-100

AD8115-EVAL Evaluation Board

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD8114/AD8115 features proprietary ESD protection circuitry, permanent dam­age may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper
ESD precautions are recommended to avoid performance degradation or loss of functionality.

MAXIMUM POWER DISSIPATION

5

The maximum power that can be safely dissipated by the
AD8114/AD8115 is limited by the associated rise in junction
temperature. The maximum safe junction temperature for

4

plastic encapsulated devices is determined by the glass transition
temperature of the plastic, approximately 150°C. Temporarily

3

exceeding this limit may cause a shift in parametric performance
due to a change in the stresses exerted on the die by the pack­age. Exceeding a junction temperature of 175°C for an extended

2

period can result in device failure.

While the AD8114/AD8115 is internally short circuit protected,
this may not be sufficient to guarantee that the maximum junc­tion temperature (150°C) is not exceeded under all conditions.
To ensure proper operation, it is necessary to observe the maxi-

1

MAXIMUM POWER DISSIPATION – W

0

–50 80–40 –30 –20 –100 10203040506070

AMBIENT TEMPERATURE – C

mum power derating curves shown in Figure 3.

Figure 3. Maximum Power Dissipation vs. Temperature

LQFP
(14 mm × 14 mm)

LQFP
(14 mm × 14 mm)

TJ = 150C

90

REV. A

–5–

AD8114/AD8115

AVEE14/15

DVCC

DGND

AGND

IN08

AGND

IN09

AGND

IN10

AGND

IN11

AGND

IN12

AGND

IN13

AGND

IN14

AGND

IN15

AGND

AVEE

AVCC

AVCC15

OUT15

OUT14

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

RESETCEDATA OUT

CLK

DATA IN

9998979695

100

PIN 1
IDENTIFIER

PIN CONFIGURATION

UPDATE

SER/PARNCNCNCNCNCNCNCNCNCA0A1A2

9493929190

8988878685

AD8114/AD8115

TOP VIEW

(Not to Scale)

A3

8483828180

D0D1D2D3D4

797877

76

75

74

73

72

71

70

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

54

53

52

51

DVCC

DGND

AGND

IN07

AGND

IN06

AGND

IN05

AGND

IN04

AGND

IN03

AGND

IN02

AGND

IN01

AGND

IN00

AGND

AVEE

AVCC

AVCC00

OUT00

AVEE00/01

OUT01

2728293031

26

OUT13

OUT12

AVEE12/13

AVCC13/14

NC = NO CONNECT

3233343536

OUT11

AVEE10/11

AVCC11/12

OUT10

AVCC09/10

OUT09

AVEE08/09

3738394041

OUT08

OUT07

AVEE06/07

AVCC07/08

4243444546

OUT06

OUT05

AVCC05/06

OUT04

AVEE04/05

AVCC03/04

474849

OUT03

AVEE02/03

50

OUT02

AVCC01/02

–6–

REV. A

AD8114/AD8115

PIN FUNCTION DESCRIPTIONS

Pin Name Pin Numbers Pin Description

INxx 58, 60, 62, 64, 66, 68, 70, 72, Analog Inputs; xx = Channel Numbers 00 Through 15.

4, 6, 8, 10, 12, 14, 16, 18
DATA IN 96 Serial Data Input, TTL Compatible.
CLK 97 Clock, TTL Compatible. Falling Edge Triggered.
DATA OUT 98 Serial Data Out, TTL Compatible.
UPDATE 95 Enable (Transparent) “Low.” Allows serial register to connect directly to switch matrix.

Data latched when “High.”

RESET 100 Disable Outputs, Active “Low.”
CE 99 Chip Enable, Enable “Low.” Must be “low” to clock in and latch data.
SER/PAR 94 Selects Serial Data Mode, “Low” or Parallel Data Mode, “High.” Must be connected.

OUTyy 53, 51, 49, 47, 45, 43, 41, 39, Analog Outputs yy = Channel Numbers 00 Through 15.

37, 35, 33, 31, 29, 27, 25, 23
AGND 3, 5, 7, 9, 11, 13, 15, 17, 19, 57, Analog Ground for Inputs and Switch Matrix. Must be connected.

59, 61, 63, 65, 67, 69, 71, 73
DVCC 1, 75 +5 V for Digital Circuitry.
DGND 2, 74 Ground for Digital Circuitry.
AVEE 20, 56 –5 V for Inputs and Switch Matrix.
AVCC 21, 55 +5 V for Inputs and Switch Matrix.
AVCCxx/yy 54, 50, 46, 42, 38, 34, 30, 26, 22 +5 V for Output Amplifier that is shared by Channel Numbers xx and yy. Must be connected.
AVEExx/yy 52, 48, 44, 40, 36, 32, 28, 24 –5 V for Output Amplifier that is shared by Channel Numbers xx and yy. Must be connected.
A0 84 Parallel Data Input, TTL Compatible (Output Select LSB).
A1 83 Parallel Data Input, TTL Compatible (Output Select).
A2 82 Parallel Data Input, TTL Compatible (Output Select).
A3 81 Parallel Data Input, TTL Compatible (Output Select MSB).
D0 80 Parallel Data Input, TTL Compatible (Input Select LSB).
D1 79 Parallel Data Input, TTL Compatible (Input Select).
D2 78 Parallel Data Input, TTL Compatible (Input Select).
D3 77 Parallel Data Input, TTL Compatible (Input Select MSB).
D4 76 Parallel Data Input, TTL Compatible (Output Enable).

NC 85–93 No Connect.

REV. A

V

CC

ESD

INPUT

ESD

AV

EE

a. Analog Input c. Reset Input

V

CC

ESD

INPUT

ESD

DGND

V

CC

ESD

ESD

AV

EE

b. Analog Output

OUTPUT

2k⍀

V

CC

DGND

RESET

ESD

ESD

V

CC

d. Logic Input e. Logic Output

Figure 5. I/O Schematics

–7–

ESD

ESD

DGND

OUTPUT

20k⍀

AD8114/AD8115

Table III. Operation Truth Table

SER/

CE UPDATE CLK DATA IN DATA OUT RESET PAR Operation/Comment

1 X X X X X X No change in logic.
01 f Data

i

01 f D0 . . . D4, NA in Parallel 1 1 The data on the parallel data lines, D0–D4, are

A0...A3 Mode loaded into the 80-bit serial shift register loca-

0 0 X X X 1 X Data in the 80-bit shift register transfers into the

X X X X X 0 X Asynchronous operation. All outputs are disabled.

D0

DATA

D1
D2
D3
D4

D

CLK

S

D1

Q

Q

D0

S

D1

Q

D0

D

CLK

S

D1

Q

Q

D0

PARALLEL

(OUTPUT

ENABLE)

SER/PAR

DATA IN

(SERIAL)

D

CLK

Data

i-80

1 0 The data on the serial DATA IN line is loaded

into serial register. The first bit clocked into
the serial register appears at DATA OUT 80
clocks later.

tion addressed by A0–A3.

parallel latches that control the switch array.
Latches are transparent.

Remainder of logic is unchanged.

S

D1

Q

Q

D0

D

CLK

S

D1

Q

Q

D0

D

CLK

S

D1

Q

D

Q

Q

D0

CLK

S

D1

Q

D0

D

CLK

S

D1

Q

Q

D0

D

CLK

S

D1

Q

Q

D0

D

CLK

S

D1

Q

Q

D0

D

CLK

S

D1

Q

Q

D0

D

CLK

S

D1

Q

D0

DATA

Q

D

Q

OUT

CLK

CLK

CE

UPDATE

OUT0 EN

OUT1 EN

OUT2 EN

OUTPUT

ADDRESS

OUT3 EN

OUT4 EN

A0

OUT5 EN

A1

OUT6 EN

A2

OUT7 EN

A3

OUT8 EN

OUT9 EN

OUT10 EN

4 TO 16 DECODER

OUT11 EN

OUT12 EN

OUT13 EN

OUT14 EN

OUT15 EN

(OUTPUT ENABLE)

RESET

LE

OUT0

D

B0

Q

LE

OUT0

B1

D

Q

LE

OUT0

B2

D

Q

LE

OUT0

B3

D

Q

LE

OUT0

EN

D

QCLR

LE

OUT1

D

B0

Q

LE

OUT14

EN

D

QCLR

LE

OUT15

B0

D

Q

LE

OUT15

B1

D

Q

LE

OUT15

B2

D

Q

LE

OUT15

B3

D

Q

LE

OUT15

EN

D

QCLR

DECODE

256

SWITCH MATRIX

OUTPUT ENABLE

16

Figure 4. Logic Diagram

–8–

REV. A

FREQUENCY – MHz

GAIN – dB

–7

–3

1

0

–1

–2

–4

–5

–6

–0.2

0.2

0.1

0

–0.1

–0.3

–0.4

–0.5

FLATNESS – dB

2

0.1 1 10 100 1000

0.3

0.4

GAIN

FLATNESS

VO AS SHOWN
R

L

= 150⍀

2V p-p

200mV p-p

0.5

–8

200mV p-p
2V p-p

FREQUENCY – MHz

GAIN – dB

–7

–3

1

0

–1

–2

–4

–5

–6

–0.2

0.2

0.1

0

–0.1

–0.3

–0.4

–0.5

FLATNESS – dB

2

0.1 1 10 100 1000

0.3

0.4

GAIN

FLATNESS

2V p-p

200mV p-p

0.5

3

VO AS SHOWN
R

L

= 1k⍀

200mV p-p
2V p-p

FREQUENCY – MHz

GAIN – dB

–4

0

–2

–6

–8

–10

2

0.1 1 10 100 1000

4

VO = 200mV p-p

R

L

AS SHOWN

C

L

= 18pF

RL = 1k⍀

RL = 150⍀

6

8

10

Typical Performance Characteristics–

AD8114/AD8115

1

GAIN

0

FLATNESS

–1

–2

–3

GAIN – dB

–4

–5

–6

–7

0.1

VO AS SHOWN
RL = 150⍀

1 10 100 1000

2V p-p

FREQUENCY – MHz

TPC 1. AD8114 Frequency Response; RL = 150

3

2

1

0

–1

–2

GAIN – dB

–3

–4

–5

–6

–7

0.1 1 10 100 1000

GAIN

FLATNESS

VO AS SHOWN
R

= 1k⍀

L

2V p-p

FREQUENCY – MHz

TPC 2. AD8114 Frequency Response; RL = 1 k

200mV p-p

200mV p-p

0.2

0.1

0

–0.1

–0.2

–0.3

–0.4

–0.5

–0.6

Ω

0.4

0.3

0.2

0.1

0

–0.1

–0.2

–0.3

–0.4

–0.5

–0.6

Ω

FLATNESS – dB

FLATNESS – dB

TPC 4. AD8115 Frequency Response; RL = 150

TPC 5. AD8115 Frequency Response; RL = 1 k

Ω

Ω

4

VO = 200mV p-p

3

AS SHOWN

R

L

2

C

= 18pF

L

1

0

–1

GAIN – dB

–2

–3

–4

REV. A

–5

–6

0.1 1 10 100 1000

TPC 3. AD8114 Frequency Response vs. Load

FREQUENCY – MHz

Impedance

RL = 1k⍀

RL = 150⍀

TPC 6. AD8115 Frequency Response vs. Load
Impedance

–9–