Analog Devices AD8111, AD8110 Datasheet

REV. 0

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.

a

AD8110/AD8111*

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] World Wide Web Site: http://www.analog.com
Fax: [phone] © Analog Devices, Inc., 1997

260 MHz, 16 3 8 Buffered

Video Crosspoint Switches

FUNCTIONAL BLOCK DIAGRAM

AD8110/AD8111

SWITCH
MATRIX

OUTPUT
BUFFER

G = +1,

G = +2

40

40

128

40-BIT SHIFT REGISTER

WITH 5-BIT

PARALLEL LOADING

PARALLEL LATCH

DECODE

8 3 5:16 DECODERS

8

CLK

DATA IN

UPDATE

CE

RESET

16 INPUTS

A0

DATA OUT

8 OUTPUTS

SET INDIVIDUAL OR

RESET ALL OUTPUTS

TO "OFF"

A1
A2

SER/PAR

D0 D1 D2D3

ENABLE/DISABLE

D4

FEATURES
16 3 8 High Speed Nonblocking Switch Arrays

AD8110: G = +1

AD8111: G = +2
Serial or Parallel Switch Array Control
Serial Data Out Allows “Daisy Chaining” of Multiple

Crosspoints to Create Larger Switch Arrays
Pin Compatible with AD8108/AD8109 8 3 8 Switch

Arrays
For a 16 3 16 Array See AD8116
Complete Solution

Buffered Inputs

Eight Output Amplifiers, AD8110 (G = +1),

AD8111 (G = +2)

Drives 150 V Loads
Excellent Video Performance

60 MHz 0.1 dB Gain Flatness

0.02% Differential Gain Error (R

L

= 150 V)

0.028 Differential Phase Error (R

L

= 150 V)

Excellent AC Performance

260 MHz –3 dB Bandwidth

500 V/ms Slew Rate
Low Power of 50 mA
Low All Hostile Crosstalk of –78 dB @ 5 MHz
Output Disable Allows Direct Connection of Multiple

Device Outputs
Reset Pin Allows Disabling of All Outputs (Connected

Through a Capacitor to Ground Provides “Power-

On” Reset Capability)

Excellent ESD Rating: Exceeds 4000 V Human Body

Model
80-Lead TQFP Package (12 mm 3 12 mm)

APPLICATIONS
Routing of High Speed Signals Including:

Composite Video (NTSC, PAL, S, SECAM)

Component Video (YUV, RGB)

Compressed Video (MPEG, Wavelet)

3-Level Digital Video (HDB3)

PRODUCT DESCRIPTION

The AD8110 and AD8111 are high speed 16 × 8 video cross­point switch matrices. They offer a –3 dB signal bandwidth
greater than 260 MHz, and channel switch times of less than
25 ns with 1% settling. With –78 dB of crosstalk and –97 dB
isolation (@ 5 MHz), the AD8110/AD8111 are useful in many
high speed applications. The differential gain and differential

phase of better than 0.02% and 0.02° respectively, along with

0.1 dB flatness out to 60 MHz, make the AD8110/AD8111 ideal
for video signal switching.

The AD8110 and AD8111 include eight independent output
buffers that can be placed into a high impedance state for paral­leling crosspoint outputs so that off channels do not load the
output bus. The AD8110 has a gain of +1, while the AD8111
offers a gain of +2. They operate on voltage supplies of ±5 V
while consuming only 50 mA of idle current. The channel
switching is performed via a serial digital control (which can
accommodate “daisy chaining” of several devices) or via a paral­lel control, allowing updating of an individual output without re­programing the entire array.

The AD8110/AD8111 is packaged in an 80-lead TQFP package
and is available over the extended industrial temperature range
of –40°C to +85°C.

*Patent Pending.

–2– REV. 0

AD8110/AD8111–SPECIFICA TIONS

(VS = 65 V, TA = +258C, RL = 1 kV unless otherwise noted)

AD8110/AD8111 Reference

Parameter Conditions Min Typ Max Units Figure No.

DYNAMIC PERFORMANCE

–3 dB Bandwidth 200 mV p-p, R

L

= 150 Ω 300/190 390/260 MHz 6, 12

2 V p-p, R

L

= 150 Ω 150 MHz 6, 12

Propagation Delay 2 V p-p, R

L

= 150 Ω 5ns

Slew Rate 2 V Step, R

L

= 150 Ω 500 V/µs

Settling Time 0.1%, 2 V Step, R

L

= 150 Ω 40 ns 11, 17

Gain Flatness 0.05 dB, 200 mV p-p, R

L

= 150 Ω 60/40 MHz 6, 12

0.05 dB, 2 V p-p, R

L

= 150 Ω 65/40 MHz 6, 12

0.1 dB, 200 mV p-p, R

L

= 150 Ω 80/57 MHz 6, 12

0.1 dB, 2 V p-p, RL = 150 Ω 70/57 MHz 6, 12

NOISE/DISTORTION PERFORMANCE

Differential Gain Error NTSC or PAL, RL = 1 kΩ 0.01 %

NTSC or PAL, R

L

=150 Ω 0.02 %

Differential Phase Error NTSC or PAL, R

L

= 1 kΩ 0.01 Degrees

NTSC or PAL, R

L

= 150 Ω 0.02 Degrees

Crosstalk, All Hostile f = 5 MHz 78/85 dB 7, 13

f = 10 MHz 70/80 dB 7, 13

Off Isolation, Input-Output f = 10 MHz, R

L

=150 Ω, One Channel 93/99 dB 22, 28

Input Voltage Noise 0.01 MHz to 50 MHz 15 nV/√Hz 19, 25

DC PERFORMANCE

Gain Error RL = 1 kΩ 0.04/0.1 0.07/0.5 %

R

L

= 150 Ω 0.15/0.25 %

Gain Matching No Load, Channel-Channel 0.02/1.0 %

R

L

= 1 kΩ, Channel-Channel 0.09/1.0 %

Gain Temperature Coefficient 0.5/8 ppm/°C

OUTPUT CHARACTERISTICS

Output Impedance DC, Enabled 0.2 Ω 23, 29

Disabled 10/0.001 MΩ 20, 26
Output Disable Capacitance Disabled 2 pF
Output Leakage Current Disabled, AD8110 Only 1/NA µA
Output Voltage Range No Load ±2.5 ±3V
Output Current 20 40 mA
Short Circuit Current 65 mA

INPUT CHARACTERISTICS

Input Offset Voltage Worse Case (All Configurations) 5 20 mV 34, 40

Temperature Coefficient 12 µV/°C 35, 41
Input Voltage Range ±2.5/±1.25 ±3/±1.5 V
Input Capacitance Any Switch Configuration 2.5 pF
Input Resistance 1 10 MΩ
Input Bias Current Per Output Selected 2 5 µA

SWITCHING CHARACTERISTICS

Enable On Time 60 ns
Switching Time, 2 V Step 50% UPDATE to 1% Settling 25 ns
Switching Transient (Glitch) Measured at Output 20/30 mV p-p 21, 27

POWER SUPPLIES

Supply Current AVCC, Outputs Enabled, No Load 38 mA

AVCC, Outputs Disabled 15 mA

AVEE, Outputs Enabled, No Load 38 mA

AVEE, Outputs Disabled 15 mA

DVCC 11 mA
Supply Voltage Range ±4.5 to ± 5.5 V
PSRR f = 100 kHz 75/78 dB 18, 24

f = 1 MHz –55/–58 dB

OPERATING TEMPERATURE RANGE

Temperature Range Operating (Still Air) –40 to +85 °C

θ

JA

Operating (Still Air) 48 °C/W

Specifications subject to change without notice.

AD8110/AD8111

–3–REV. 0

TIMING CHARACTERISTICS (Serial)

Limit

Parameter Symbol Min Typ Max Units

Serial Data Setup Time t

1

20 ns

CLK Pulsewidth t

2

100 ns

Serial Data Hold Time t

3

20 ns

CLK Pulse Separation, Serial Mode t

4

100 ns

CLK to

UPDATE Delay t

5

0ns

UPDATE Pulsewidth t

6

50 ns

CLK to DATA OUT Valid, Serial Mode t

7

180 ns
Propagation Delay, UPDATE to Switch On or Off – 8 ns
Data Load Time, CLK = 5 MHz, Serial Mode – 8 µs
CLK, UPDATE Rise and Fall Times – 100 ns
RESET Time – 200 ns

1

0

1

0

1 = LATCHED

0 = TRANSPARENT

DATA OUT

CLK

DATA IN

OUT7 (D4) OUT7 (D3) OUT00 (D0)

LOAD DATA INTO
SERIAL REGISTER
ON FALLING EDGE

TRANSFER DATA FROM SERIAL

REGISTER TO PARALLEL

LATCHES DURING LOW LEVEL

t

2

t

4

t1t

3

t

7

t

5

t

6

UPDATE

Figure 1. Timing Diagram, Serial Mode

Table I. Logic Levels

V

IH

V

IL

V

OH

V

OL

I

IH

I

IL

I

OH

I

OL

RESET, SER/PAR RESET, SER/PAR RESET, SER/PAR RESET, SER/PAR
CLK, DATA IN, CLK, DATA IN, CLK, DATA IN, CLK, DATA IN,
CE, UPDATE CE, UPDATE DATA OUT DATA OUT CE, UPDATE CE, UPDATE DATA OUT DATA OUT

2.0 V min 0.8 V max 2.7 V min 0.5 V max 20 µA max –400 µA min –400 µA max 3.0 mA min

AD8110/AD8111

–4– REV. 0

TIMING CHARACTERISTICS (Parallel)

Limit

Parameter Symbol Min Max Units

Data Setup Time t

1

20 ns

CLK Pulsewidth t

2

100 ns

Data Hold Time t

3

20 ns

CLK Pulse Separation t

4

100 ns

CLK to

UPDATE Delay t

5

0ns

UPDATE Pulsewidth t

6

50 ns
Propagation Delay, UPDATE to Switch On or Off – 8 ns
CLK, UPDATE Rise and Fall Times – 100 ns
RESET Time – 200 ns

t

5

t

6

t

4

t

2

t

1

t

3

1

0

1

0

1 = LATCHED

CLK

D0–D4
A0–A2

0 = TRANSPARENT

UPDATE

Figure 2. Timing Diagram, Parallel Mode

Table II. Logic Levels

V

IH

V

IL

V

OH

V

OL

I

IH

I

IL

I

OH

I

OL

RESET, SER/PAR RESET, SER/PAR RESET, SER/PAR RESET, SER/PAR
CLK, D0, D1, D2, CLK, D0, D1, D2, CLK, D0, D1, D2, CLK, D0, D1, D2,
D3, D4, A0, A1, A2 D3, D4, A0, A1, A2 D3, D4, A0, A1, A2 D3, D4, A0, A1, A2
CE, UPDATE CE, UPDATE DATA OUT DATA OUT CE, UPDATE CE, UPDATE DATA OUT DATA OUT

2.0 V min 0.8 V max 2.7 V min 0.5 V max 20 µA max –400 µA min –400 µA max 3.0 mA min

AD8110/AD8111

–5–REV. 0

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD8110/AD8111 features proprietary ESD protection circuitry, permanent dam­age may occur on devices subjected to high energy electrostatic discharges. Therefore, proper
ESD precautions are recommended to avoid performance degradation or loss of functionality.

MAXIMUM POWER DISSIPATION

The maximum power that can be safely dissipated by the
AD8110/AD8111 is limited by the associated rise in junction
temperature. The maximum safe junction temperature for plas­tic encapsulated devices is determined by the glass transition
temperature of the plastic, approximately +150°C. Temporarily
exceeding this limit may cause a shift in parametric performance
due to a change in the stresses exerted on the die by the pack­age. Exceeding a junction temperature of +175°C for an ex­tended period can result in device failure.

While the AD8110/AD8111 is internally short circuit protected,
this may not be sufficient to guarantee that the maximum junc­tion temperature (+150°C) is not exceeded under all condi­tions. To ensure proper operation, it is necessary to observe the
maximum power derating curves shown in Figure 3.

AMBIENT TEMPERATURE – 8C

5.0

MAXIMUM POWER DISSIPATION – Watts

4.0

0

–50 80–40 –30 –20 –10 0 10 20 30 40 50 60 70

3.0

2.0

1.0

TJ = 1508C

90

Figure 3. Maximum Power Dissipation vs. Temperature

ABSOLUTE MAXIMUM RATINGS

1

Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12.0 V

Internal Power Dissipation

2

AD8110/AD8111 80-Lead Plastic TQFP (ST) . . . . . 2.6 W

Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .±V

S

Output Short Circuit Duration

. . . . . . . . . . . . . . . . . . . . . .Observe Power Derating Curves

Storage Temperature Range . . . . . . . . . . . . –65°C to +125°C

Lead Temperature Range (Soldering 10 sec) . . . . . . . .+300°C

NOTES

1

Stresses above those listed under Absolute Maximum Ratings may cause perma-

nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.

2

Specification is for device in free air (TA = +25°C):

80-lead plastic TQFP (ST): θJA = 48°C/W.

ORDERING GUIDE

Temperature Package Package

Model Range Description Option

AD8110AST –40°C to +85°C 80-Lead Plastic TQFP (12 mm × 12 mm) ST-80A
AD8111AST –40°C to +85°C 80-Lead Plastic TQFP (12 mm × 12 mm) ST-80A
AD8110-EB Evaluation Board
AD8111-EB Evaluation Board

WARNING!

ESD SENSITIVE DEVICE

AD8110/AD8111

–6– REV. 0

Table III. Operation Truth Table

SER/

CE UPDATE CLK DATA IN DATA OUT RESET PAR Operation/Comment

1 X X X X X X No change in logic.
01 f Data

i

Data

i-40

1 0 The data on the serial DATA IN line is loaded

into serial register. The first bit clocked into
the serial register appears at DATA OUT 40
clocks later.

01 f D0. . . D4, NA in Parallel 1 1 The data on the parallel data lines, D0–D4, are

A0...A2 Mode loaded into the 40-bit serial shift register loca-

tion addressed by A0–A2.

0 0 X X X 1 X Data in the 40-bit shift register transfers into the

parallel latches that control the switch array.
Latches are transparent.

X X X X X 0 X Asynchronous operation. All outputs are disabled.

Remainder of logic is unchanged.

D

CLK

Q

3 TO 8 DECODER

A0
A1
A2

CLK

CE

UPDATE

8

128

DATA IN

(SERIAL)

(OUTPUT

ENABLE)

SER/PAR

RESET

(OUTPUT ENABLE)

OUT0 EN

DATA
OUT

PARALLEL

DATA

DQ
CLK

DQ

CLK

DQ
CLK

DQ
CLK

D1
D2
D3

DQ
CLK

DQ
CLK

DQ
CLK

DQ
CLK

D

Q

CLK

OUT1 EN

OUT2 EN

OUT3 EN

OUT4 EN

OUT5 EN

OUT6 EN

OUT7 EN

D

LE

QCLR

OUT7

EN

OUTPUT ENABLESWITCH MATRIX

S

D1

Q

D0

D0

S

D1

Q

D0

S

D1

Q

D0

S

D1

Q

D0

S

D1

Q

D0

S

D1

Q

D0

S

D1

Q

D0

S

D1

Q

D0

DQ
CLK

S

D1

Q

D0

D4

DECODE

D

LE

QCLR

OUT0

EN

D

LE

OUT0

B0

Q

D

LE

Q

OUT0

B1

D

LE

Q

OUT0

B2

D

LE

Q

OUT0

B3

D

LE
OUT1

B0

Q

D

LE

QCLR

OUT6

EN

D

LE
OUT7

B0

Q

D

LE

OUT7

B1

Q

D

LE
OUT7

B2

Q

DQ
CLK

S

D1

Q

D0

S

D1

Q

D0

D

LE
OUT7

B3

Q

S

D1

Q

D0

Figure 4. Logic Diagram

AD8110/AD8111

–7–REV. 0

PIN FUNCTION DESCRIPTIONS

Pin Name Pin Numbers Pin Description

INxx 66, 68, 70, 72, 74, 76, 78, Analog Inputs; xx = Channel Numbers 00 Through 15.

1, 3, 5, 7, 9, 11, 13, 15, 64
DATA IN 57 Serial Data Input, TTL Compatible.
CLK 58 Clock, TTL Compatible. Falling Edge Triggered.
DATA OUT 59 Serial Data Out, TTL Compatible.
UPDATE 56 Enable (Transparent) “Low.” Allows serial register to connect directly to switch

matrix. Data latched when “High.”

RESET 61 Disable Outputs, Active “Low.”
CE 60 Chip Enable, Enable “Low.” Must be “low” to clock in and latch data.

SER/PAR 55 Selects Serial Data Mode, “Low” or Parallel Data Mode, “High.” Must be connected.
OUTyy 41, 38, 35, 32, 29, 26, 23, 20 Analog Outputs yy = Channel Numbers 00 Through 07.
AGND 2, 4, 6, 8, 10, 12, 14, 16, 46 Analog Ground for Inputs and Switch Matrix.

65, 67, 69, 71, 73, 75, 77
DVCC 63, 79 +5 V for Digital Circuitry.
DGND 62, 80 Ground for Digital Circuitry.
AVEE 17, 45 –5 V for Inputs and Switch Matrix.
AVCC 18, 44 +5 V for Inputs and Switch Matrix.
AGNDxx 42, 39, 36, 33, 30, 27, 24, 21 Ground for Output Amp, xx = Output Channel Numbers 00 Through 07. Must be connected.
AVCCxx/yy 43, 37, 31, 25, 22, 19 +5 V for Output Amplifier that is shared by Channel Numbers xx and yy. Must be connected.
AVEExx/yy 40, 34, 28, 22 –5 V for Output Amplifier that is shared by Channel Numbers xx and yy. Must be connected.
A0 54 Parallel Data Input, TTL Compatible (Output Select LSB).
A1 53 Parallel Data Input, TTL Compatible (Output Select).
A2 52 Parallel Data Input, TTL Compatible (Output Select MSB).
D0 51 Parallel Data Input, TTL Compatible (Input Select LSB).
D1 50 Parallel Data Input, TTL Compatible (Input Select).
D2 49 Parallel Data Input, TTL Compatible (Input Select).
D3 48 Parallel Data Input, TTL Compatible (Input Select MSB).
D4 47 Parallel Data Input, TTL Compatible (Output Enable).

ESD

ESD

INPUT

V

CC

AV

EE

ESD

ESD

OUTPUT

V

CC

AV

EE

1kV
(AD8111 ONLY)

ESD

ESD

RESET

V

CC

20kV

DGND

ESD

ESD

INPUT

V

CC

DGND

ESD

ESD

OUTPUT

V

CC

2kV

DGND

d. Logic Input e. Logic Output

Figure 5. I/O Schematics

a. Analog Input c. Reset Input

b. Analog Output

AD8110/AD8111

–8– REV. 0

PIN CONFIGURATION

80

79787776757473727170696867

66

656463

62

61

56

57

58

59

54

55

52

53

50

51

60

45

46

47

48

43

44

42

49

41

5

4

3

2

7

6

9

8

1

11

10

16

15

14

13

18

17

20

19

12

PIN 1
IDENTIFIER

TOP VIEW

(PINS DOWN)

0.5mm LEAD PITCH

AD8110/AD8111

16 3 8

80L TQFP

(12mm 3 12mm)

40

39

38

37

35

34

33

32

31

30

29

28

27

26

25

24

23

22

21

36

DGND

DVCC

IN07

AGND

IN06

AGND

IN05

AGND

IN04

AGND

IN03

AGND

IN02

AGND

IN01

AGND

IN00

DVCC

DGND

RESET

AGND07

AVEE06/07

OUT06

AGND06

AVCC05/06

OUT05

AGND05

AVEE04/05

OUT04

AGND04

AVCC03/04

OUT03

AGND03

AVEE02/03

OUT02

AGND02

AVCC01/02

OUT01

AGND01

CE

DATA OUT
CLK
DATA IN

UPDATE
SER/PAR

A0
A1
A2
D0
D1
D2
D3
D4
AGND
AVEE
AVCC
AVCC00
AGND00
OUT00

IN08

AGND

IN09

AGND

IN10

AGND

IN11

AGND

IN12

AGND

IN13

AGND

IN14

AGND

IN15

AGND

AVEE

AVCC

AVCC07

OUT07

AVEE00/01

AD8110/AD8111

–9–REV. 0

Typical Characteristics–

FREQUENCY – Hz

GAIN – dB

–2

1

0

–1

–3

100k 1M 1G10M 100M

FLATNESS – dB

0.2

0.1

0

–0.1

–0.2

–0.3

GAIN

FLATNESS

2

3

0.3

4

5

200mV p-p

2V p-p

RL = 150V

Figure 6. AD8110 Frequency Response

FREQUENCY – MHz

CROSSTALK – dB

–30

–40

–100

0.3 1 20010 100

–50

–60

–70

–80

–90

ADJACENT

ALL HOSTILE

RL = 1kV

Figure 7. AD8110 Crosstalk vs. Frequency

FREQUENCY – Hz

DISTORTION – dB

100k

1M 100M10M

–100

–40

–50

–60

–70

–80

–90

2ND HARMONIC

3RD HARMONIC

RL = 150V
V

OUT

= 2V p-p

Figure 8. AD8110 Distortion vs. Frequency

50
25

0

225
250

25ns/DIV

25mV/DIV

RL = 150V

Figure 9. AD8110 Step Response, 100 mV Step

1

0.5

0

20.5
21

25ns/DIV

0.5V/DIV

RL = 150V

Figure 10. AD8110 Step Response, 2 V Step

2V STEP
RL = 150V

01020304050607080

10ns/DIV

0.1%/DIV

Figure 11. AD8110 Settling Time