ANALOG DEVICES AD811 Service Manual

–

www.BDTIC.com/ADI

High Performance Video Op Amp

FEATURES

High speed

140 MHz bandwidth (3 dB, G = +1)
120 MHz bandwidth (3 dB, G = +2)
35 MHz bandwidth (0.1 dB, G = +2)
2500 V/µs slew rate
25 ns settling time to 0.1% (for a 2 V step)
65 ns settling time to 0.01% (for a 10 V step)

Excellent video performance (R

0.01% differential gain, 0.01° differential phase

Voltage noise of 1.9 nV/√
Low distortion: THD = −74 dB @ 10 MHz
Excellent dc precision: 3 mV max input offset voltage
Flexible operation

Specified for ±5 V and ±15 V operation

±2.3 V output swing into a 75 Ω load (V

APPLICATIONS

Video crosspoint switchers, multimedia broadcast systems
HDTV compatible systems
Video line drivers, distribution amplifiers
ADC/DAC buffers
DC restoration circuits
Medical

Ultrasound

PET

Gamma

Counter applications

GENERAL DESCRIPTION

A wideband current feedback operational amplifier, the AD811
is optimized for broadcast-quality video systems. The −3 dB
bandwidth of 120 MHz at a gain of +2 and the differential gain
and phase of 0.01% and 0.01° (R
an excellent choice for all video systems. The AD811 is designed
to meet a stringent 0.1 dB gain flatness specification to a band­width of 35 MHz (G = +2) in addition to low differential gain
and phase errors. This performance is achieved whether driving
one or two back-terminated 75 Ω cables, with a low power
supply current of 16.5 mA. Furthermore, the AD811 is specified
over a power supply range of ±4.5 V to ±18 V.
(Continued on page 3)

=150 Ω)

L

Hz

= ±5 V)

S

= 150 Ω) make the AD811

L

AD811

CONNECTION DIAGRAMS

NC

AD811

NC

NC

NC

1232019

AD811

12 13

10 11

S

NC

NC

–V

AD811

NC

NC

8
7

+V

6

OUTPUT

5

NC

16

15

14

13

12

11

10

NC

NC

20

19
18

17

16

15

14

13

12

11

S

NC
NC
+V
NC

OUTPUT
NC

NC

9

NC

18

NC

17

NC

16

+V

15

NC

14

OUTPUT

NC
NC
NC
+V
NC
OUTPUT
NC
NC
NC
NC

00866-E-001

S

00866-E-002

S

00866-E-003

S

00866-E-004

1

NC

2

–IN

3

+IN

–V

4

S

AD811

NC = NO CONNECT

Figure 1. 8-Lead Plastic (N-8), CERDIP (Q-8), SOIC (R-8)

1

NC
NC

2

3

–IN

4

NC

+IN

5

NC

6

–V

7

S

8

NC

NC = NO CONNECT

Figure 2. 16-Lead SOIC (R-16)

NC

4

NC

5
6

–IN

NC

7
8

+IN

9

NC = NO CONNECT

Figure 3. 20-Terminal LCC (E-20A)

NC

1

2

NC

3

NC

4

–IN
NC

5

+IN

6

NC

7

8

V

S

NC

9

10

NC

NC = NO CONNECT

Figure 4. 20-Lead SOIC (R-20)

Rev. E

Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] © 2004 Analog Devices, Inc. All rights reserved.

AD811

www.BDTIC.com/ADI

TABLE OF CONTENTS

Specifications..................................................................................... 4

Absolute Maximum Ratings............................................................ 6

Maximum Power Dissipation ..................................................... 6

Metalization Photograph............................................................. 6

Typical Performance Characteristics............................................. 7

Applications..................................................................................... 12

General Design Considerations................................................ 12

REVISION HISTORY

7/04—Data Sheet Changed from Rev. D to Rev. E

U

pdated Format............................................................. Universal

Change to Maximum Power Dissipation Section ....................7

Changes to Ordering Guide......................................................20

Updated Outline Dimensions................................................... 20

Achieving the Flattest Gain Response at High Frequency.... 12

Operation as a Video Line Driver ............................................ 14

An 80 MHz Voltage-Controlled Amplifier Circuit................ 15

A Video Keyer Circuit................................................................ 16

Outline Dimensions....................................................................... 18

Ordering Guide .......................................................................... 20

Rev. E | Page 2 of 20

AD811

www.BDTIC.com/ADI

GENERAL DESCRIPTION (continued)

The AD811 is also excellent for pulsed applications where tran­sient response is critical. It can achieve a maximum slew rate of
greater than 2500 V/µs with a settling time of less than 25 ns to

0.1% on a 2 V step and 65 ns to 0.01% on a 10 V step.

The AD811 is ideal as an ADC or DAC buffer in data acquisi­tion systems due to its low distortion up to 10 MHz and its wide
unity gain bandwidth. Because the AD811 is a current feedback
amplifier, this bandwidth can be maintained over a wide range
of gains. The AD811 also offers low voltage and current noise of

1.9 nV/√

Hz

and 20 pA/√Hz, respectively, and excellent dc accu-

racy for wide dynamic range applications.

0.10

0.09

0.08

0.07

0.06

0.05

0.04

0.03

DIFFERENTIAL GAIN (%)

0.02

0.01

PHASE

GAIN

0

5 6 7 8 9 101112131415

SUPPLY VOLTAGE (±V)

RF = 649Ω
F

= 3.58MHz

C

100 IRE
MODULATED RAMP
R

= 150Ω

L

Figure 5. Differential Gain and Phase

0.20

0.18

0.16

0.14

0.12

0.10

0.08

0.06

0.04

0.02

0

DIFFERENTIAL PHASE (DEGREES)

00866-E-005

12

G = +2

9

R

= 150Ω

L

= R

R

G

FB

6

3

GAIN (dB)

0

–3

–6

1 10 100

FREQUENCY (MHz)

Figure 6. Frequency Response

V

= ±5V

S

VS = ±15V

00866-E-006

Rev. E | Page 3 of 20

AD811

www.BDTIC.com/ADI

SPECIFICATIONS

@ TA = +25°C, VS = ±15 V dc, R

Table 1.

AD811J/A
Parameter Conditions V

DYNAMIC PERFORMANCE

Small Signal Bandwidth (No Peaking)

−3 dB
G = +1 RFB = 562 Ω ±15 V 140 140 MHz
G = +2 RFB = 649 Ω ±15 V 120 120 MHz
G = +2 RFB = 562 Ω ±15 V 80 80 MHz
G = +10 RFB = 511 Ω ±15 V 100 100 MHz

0.1 dB Flat
G = +2 RFB = 562 Ω ±15 25 25 MHz

R

Full Power Bandwidth

3

Slew Rate V
V
Settling Time to 0.1% 10 V Step, AV = − 1 ±15 50 50 ns
Settling Time to 0.01% 10 V Step, AV = − 1 ±15 65 65 ns
Settling Time to 0.1% 2 V Step, AV = − 1 ±15 25 25 ns
Rise Time, Fall Time RFB = 649, AV = +2 ±15 3.5 3.5 ns
Differential Gain f = 3.58 MHz ±15 0.01 0.01 %
Differential Phase f = 3.58 MHz ±15 0.01 0.01 Degree
THD @ fC = 10 MHz V
Third-Order Intercept

4

±15 43 43 dBm
INPUT OFFSET VOLTAGE ±5 V, ±15 V 0.5 3 0.5 3 mV
T

Offset Voltage Drift 5 5 µV/°C

INPUT BIAS CURRENT

−Input ±5 V, ±15 V 2 5 2 5 µA

T

+Input ±5 V, ±1 5 V 2 10 2 10 µA
T
TRANSRESISTANCE T
V
R
R
V
R

1

The AD811JR is specified with ±5 V power supplies only, with operation up to ±12 V.

2

See the Analog Devices military data sheet for 883B tested specifications.

3

FPBW = slew rate/(2 π V

4

Output power level, tested at a closed-loop gain of two.

PEAK

).

= 150 Ω, unless otherwise noted.

LOAD

= 649 Ω ±15 35 35 MHz

FB

V

= 20 V p-p ±15 40 40 MHz

OUT

= 4 V p-p ±15 400 400 V/µs

OUT

= 20 V p-p ±15 2500 2500 V/µs

OUT

= 2 V p-p, AV = +2 ±15 −74 −74 dBc

OUT

@ fC = 10 MHz ±15 36 36 dBm

to T

MIN

MAX

to T

MIN

MAX

to T

MIN

MAX

to T

MIN

MAX

= ±10 V

OUT

= ∞ ±15 V 0.75 1.5 0.75 1.5 MΩ

L

= 200 Ω ±15 V 0.5 0.75 0.5 0.75 MΩ

L

= ±2.5 V

OUT

= 150 Ω ±5 V 0.25 0.4 0.125 0.4 MΩ

L

1

S

Min Typ Max Min Typ Max Unit

AD811S

2

5 5 mV

15 30 µA

20 25 µA

Rev. E | Page 4 of 20

AD811

www.BDTIC.com/ADI

AD811J/A
Parameter Conditions V

Min Typ Max Min Typ Max Unit

s

1

AD811S

COMMON-MODE REJECTION

VOS (vs. Common Mode)

T

to T

MIN

MAX

T

to T

MIN

MAX

Input Current (vs. Common Mode) T

VCM = ±2.5 V ±5 V 56 60 50 60 dB
VCM = ±10 V ±15 V 60 66 56 66 dB

MIN

to T

MAX

1 3 1 3 µA/V

POWER SUPPLY REJECTION VS = ±4.5 V to ±18 V

V

OS

+Input Current T

−Input Current T

T

MIN

MIN

MIN

to T
to T
to T

MAX

MAX

MAX

60 70 60 70 dB

0.3 2 0.3 2 µA/V

0.4 2 0.4 2 µA/V

INPUT VOLTAGE NOISE f = 1 kHz 1.9 1.9
INPUT CURRENT NOISE f = 1 kHz 20 20
OUTPUT CHARACTERISTICS

Voltage Swing, Useful Operating Range

3

±5 V ±2.9 ±2.9 V

±15 V ±12 ±12 V

Output Current TJ = 25°C 100 100 mA
Short-Circuit Current 150 150 mA

Output Resistance (Open Loop @ 5 MHz) 9 9 Ω

INPUT CHARACTERISTIC

+Input Resistance 1.5 1.5 MΩ

−Input Resistance 14 14 Ω
Input Capacitance +Input 7.5 7.5 pF

Common-Mode Voltage Range ±5 V ±3 ±3 V
±15 V ±13 ±13 V
POWER SUPPLY

Operating Range ±4.5 ±18 ±4.5 ±18 V

Quiescent Current ±5 V 14.5 16.0 14.5 16.0 mA
±15 V 16.5 18.0 16.5 18.0 mA
TRANSISTOR COUNT Number of Transistors 40 40

1

The AD811JR is specified with ±5 V power supplies only, with operation up to ±12 V.

2

See the Analog Devices military data sheet for 883B tested specifications.

3

Useful operating range is defined as the output voltage at which linearity begins to degrade.

2

nV/√
pA/√

Hz
Hz

Rev. E | Page 5 of 20

AD811

–

www.BDTIC.com/ADI

ABSOLUTE MAXIMUM RATINGS

Table 2.

Parameter Rating

Supply Voltage ±18 V

AD811JR Grade Only ±12 V

Internal Power Dissipation Observe Derating Curves

8-Lead PDIP Package θJA = 90°C/ W
8-Lead CERDIP Package θJA = 110°C/W
8-Lead SOIC Package θJA = 155°C/W
16-Lead SOIC Package θJA = 85°C/W
20-Lead SOIC Package θJA = 80°C/W

20-Lead LCC Package θJA = 70°C/W
Output Short-Circuit Duration Observe Derating Curves
Common-Mode Input Voltage ±V
Differential Input Voltage ±6 V
Storage Temperature Range (Q, E) −65°C to +150°C
Storage Temperature Range (N, R) −65°C to +125°C
Operating Temperature Range

AD811J 0°C to +70°C

AD811A −40°C to +85°C

AD811S −55°C to +125°C
Lead Temperature Range

(Soldering 60 sec)

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

S

300°C

MAXIMUM POWER DISSIPATION

The maximum power that can be safely dissipated by the
AD811 is limited by the associated rise in junction temper­ature. For the plastic packages, the maximum safe junction
temperature is 145°C. For the CERDIP and LCC packages, the
maximum junction temperature is 175°C. If these maximums
are exceeded momentarily, proper circuit operation is restored
as soon as the die temperature is reduced. Leaving the device in
the “overheated” condition for an extended period can result in
device burnout. To ensure proper operation, it is important to
observe the derating curves in Figure 22 and Figure 25.

While the AD811 is internally short-circuit protected, this may
not be sufficient to guarantee that the maximum junction
temperature is not exceeded under all conditions. An important
example is when the amplifier is driving a reverse-terminated
75 Ω cable and the cable’s far end is shorted to a power supply.
With power supplies of ±12 V (or less) at an ambient tempera­ture of +25°C or less, and the cable shorted to a supply rail, the
amplifier is not destroyed, even if this condition persists for an
extended period.

METALIZATION PHOTOGRAPH

Contact the factory for the latest dimensions.

V+

7

V

OUT

6

0.0618
(1.57)

2

INPUT

0.098 (2.49)

Figure 7. Metalization Photograph

Dimensions Shown in Inches and (Millimeters)

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the
human body and test equipment and can discharge without detection. Although this product features proprie­tary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic
discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of
functionality.

Rev. E | Page 6 of 20

3

+INPUT

AD811

4

V–

00866-E-007

AD811

www.BDTIC.com/ADI

TYPICAL PERFORMANCE CHARACTERISTICS

20

20

TA = 25°C

15

10

5

COMMON-MODE VOLTAGE RANGE (±V)

0

501015

SUPPLY VOLTAGE (±V)

Figure 8. Input Common-Mode Voltage Range vs. Supply Voltage

35

30

25

20

15

10

OUTPUT VOLTAGE (V p-p)

5

0

10 1k100 10k

VS = ±15V

V

= ±5V

S

LOAD RESISTANCE (Ω)

Figure 9. Output Voltage Swing vs. Resistive Load

10

5

0

–5

–10

–15

–20

MASTER CLOCK FREQUENCY (MHz)

–25

–30

–60 –40 –20 0 20 40 60 80 100 120 140

NONINVERTING INPUT

±5 TO ±15V

INVERTING INPUT

V

JUNCTION TEMPERATURE (°C)

= ±15V

S

V

= ±5V

S

Figure 10. Input Bias Current vs. Junction Temperature

MAGNITUDE OF THE OUTPUT VOLTAGE (±V)

20

00866-E-008

QUIESCENT SUPPLY CURRENT (mA)

00866-E-009

INPUT OFFSET VOLTAGE (mV)

00866-E-010

TA = 25°C

15

= 150

Ω

R

L

10

NO LOAD

5

0

501015

SUPPLY VOLTAGE (±V)

Figure 11. Output Voltage Swing vs. Supply Voltage

21

18

15

12

9

6

3

–60 –40 –20 0 20 40 60 80 100 120 140

VS = ±15V

= ±5V

V

S

JUNCTION TEMPERATURE (°C)

Figure 12. Quiescent Supply Current vs. Junction Temperature

10

8

6

4

2

0

–2

–4

–6

–8

–10

–60 –40 –20 0 20 40 60 80 100 120 140

JUNCTION TEMPERATURE (°C)

VS = ±15V

V

= ±5V

S

Figure 13. Input Offset Voltage vs. Junction Temperature

20

00866-E-011

00866-E-012

00866-E-013

Rev. E | Page 7 of 20

AD811

www.BDTIC.com/ADI

250

200

VS = ±15V

2.0

VS = ±15V

= 200

Ω

R

L

V

)

1.5

Ω

OUT

= ±10V

150

V

= ±5V

S

100

SHORT-CIRCUIT CURRENT (mA)

50

–60 –40 –20 0 20 40 60 80 100 120 140

JUNCTION TEMPERATURE (°C)

Figure 14. Short-Circuit Current vs. Junction Temperature

10

)

Ω

1

V

= ±5V

S

0.1

CLOSED-LOOP OUTPUT RESISTANCE (

0.01
100k10k 1M 10M 100M

FREQUENCY (Hz)

VS = ±15V

GAIN = –2

R

FB

Figure 15. Closed-Loop Output Resistance vs. Frequency

10

= 649

1.0

= ±5V

V

S

= 150

Ω

R

L

V

= ±2.5V

TRANSRESISTANCE (M

0.5

0

–60 –40 –20 0 20 40 60 80 100 120 140

00866-E-014

OUT

JUNCTION TEMPERATURE (°C)

00866-E-017

Figure 17. Transresistance vs. Junction Temperature

100

NONINVERTING CURRENT VS = ±5V TO ±15V

= ±15V

S

= ±5V

S

S

= ±5V TO ±15V

INVERTING CURRENT V

10

NOISE VOLTAGE (nV/ Hz)

VOLTAGE NOISE V

Ω

1

00866-E-015

VOLTAGE NOISE V

10010 1k 10k 100k

FREQUENCY (Hz)

100

10

1

NOISE CURRENT (pA/ Hz)

00866-E-018

Figure 18. Input Noise vs. Frequency

100

200

10

8

6

OVERSHOOT

4

RISE TIME (ns)

2

0

VALUE OF FEEDBACK RESISTOR [R

RISE TIME

V

= ±15V

S

= 1V p-p

V

O

= 150

R

L

GAIN = +2

0.8 1.00.4 0.6 1.2 1.4 1.6
] (kΩ)

FB

Figure 16. Rise Time and Overshoot vs. Value of Feedback Resistor, R

60

40

Ω

20

OVERSHOOT (%)

0

–20

00866-E-016

FB

160

120

80

–3dB BANDWIDTH (MHz)

40

0

BANDWIDTH

PEAKING

0.8 1.00.4 0.6 1.2 1.4 1.6

VALUE OF FEEDBACK RESISTOR [R

Figure 19. −3 dB Bandwidth and Peaking vs. Value of R

Rev. E | Page 8 of 20

= ±15V

V

S

= 1V p-p

V

O

= 150

R

L

GAIN = +2

] (kΩ)

FB

8

6

Ω

4

PEAKING (dB)

2

0

00866-E-019

FB

AD811

www.BDTIC.com/ADI

110

100

90

80

70

CMRR (dB)

60

50

40

649

Ω

649

Ω

V

IN

150

Ω

150

V

OUT

Ω

VS = ±15V

= ±5V

V

S

25

20

GAIN = +10
OUTPUT LEVEL

15

FOR 3% THD

10

OUTPUT VOLTAGE (V p-p)

5

V

= ±5V

S

VS = ±15V

30

10k1k 100k 1M 10M

FREQUENCY (Hz)

Figure 20. Common-Mode Rejection Ratio vs. Frequency

80

= 649

Ω

R

70

= ±5V

V

S

60

50

40

CURVES ARE FOR WORST
CASE CONDITION WHERE

PSRR (dB)

30

ONE SUPPLY IS VARIED
WHILE THE OTHER IS
HELD CONSTANT.

20

10

5

10k1k 100k 1M 10M

FREQUENCY (Hz)

F

AV = +2

VS = ±15V

Figure 21. Power Supply Rejection Ration vs. Frequency

2.5

16-LEAD SOIC

2.0

8-LEAD PDIP

1.5

1.0

TOTAL POWER DISSIPATION (W)

0.5
–50 –30–40 –20 –10 0 20 6010 30 40 50 70 80 90

8-LEAD SOIC

AMBIENT TEMPERATURE (°C)

20-LEAD SOIC

TJ MAX = –145°C

Figure 22. Maximum Power Dissipation vs. Temperature for Plastic Packages

0

100k 10M1M 100M

00866-E-020

FREQUENCY (Hz)

00866-E-023

Figure 23. Large Signal Frequency Response

–50

RL = 100

Ω

V

= 2V p-p

OUT

GAIN = +2

–70

–90

THIRD HARMONIC

–110

HARMONIC DISTORTION (dBc)

SECOND
HARMONIC

–130

00866-E-021

SECOND HARMONIC

THIRD HARMONIC

10k1k 100k 1M 10M

FREQUENCY (Hz)

±5V SUPPLIES

±15V SUPPLIES

00866-E-024

Figure 24. Harmonic Distortion vs. Frequency

3.4

3.2

3.0

2.8

2.6

2.4

2.2

2.0

1.8

1.6

8-LEAD CERDIP

1.4

1.2

1.0

TOTAL POWER DISSIPATION (W)

0.8

0.6

0.4
–60 –40 –20 0 20 40 60 80 100 120 140

00866-E-022

AMBIENT TEMPERATURE (°C)

20-LEAD LCC

TJ MAX = –175°C

00866-E-025

Figure 25. Maximum Power Dissipation vs.

Temperature for Hermetic Packages

Rev. E | Page 9 of 20

AD811

www.BDTIC.com/ADI

V

IN

HP8130
PULSE
GENERATOR

100

90

V

IN

R

FB

+V

S

V

OUT

0.1µF

R

G

–

2

7

AD811

3

50Ω

0.1µF

5

+

–V

S

TEKTRONIX
P6201 FET
PROBE

6

Figure 26. Noninverting Amplifier Connection

1V

10ns

TO

9

G = +1
R

= 150Ω

6

L

R

= ∞

G

3

0

R

L

00866-E-026

–3

GAIN (dB)

–6

–9

–12

1 10 100

FREQUENCY (MHz)

V

S

R

FB

VS = ±15V
R

FB

= ±5V

= 619Ω

= 750Ω

00866-E-029

Figure 29. Closed-Loop Gain vs. Frequency, Gain = +1

26

G = +1

= 150Ω

R

L

23

VS = ±15V
R

20

= 511Ω

FB

10

V

OUT

0%

1V

Figure 27. Small Signal Pulse Response, Gain = +1

100mV

100

90

V

IN

10

V

OUT

0%

1V

Figure 28. Small Signal Pulse Response, Gain = +10

10ns

17

GAIN (dB)

14

11

8

1 10 100

00866-E-027

FREQUENCY (MHz)

V
R

= ±5V

S

FB

= 442Ω

00866-E-030

Figure 30. Closed-Loop Gain vs. Frequency, Gain = +10

1V

100

V

90

IN

10

V

OUT

0%

20ns

10V

00866-E-028

Figure 31. Large Signal Pulse Response, Gain = +10

00866-E-031

Rev. E | Page 10 of 20

AD811

www.BDTIC.com/ADI

6

G = –1

= 150Ω

R

L

3

VS = ±15V
R

= 590Ω

V
R

= ±5V

S

FB

FB

= 562Ω

0

–3

GAIN (dB)

–6

V

IN

HP8130
PULSE
GENERATOR

R

FB

+V

S

0.1µF

R

G

2

7

–

AD811

3

+

4

6

V

TO

OUT

TEKTRONIX
P6201 FET
PROBE

R

L

0.1µF

–V

S

00866-E-032

Figure 32. Inverting Amplifier Connection

1V

100

90

V

IN

10

V

OUT

0%

10ns

–9

–12

1 10 100

FREQUENCY (MHz)

Figure 35. Closed-Loop Gain vs. Frequency, Gain = −1

26

G = –1

= 150Ω

R

L

23

20

17

GAIN (dB)

14

11

V
R

= ±5V

S
FB

VS = ±15V
R

= 442Ω

FB

= 511Ω

00866-E-035

1V

8

1 10 100

00866-E-033

Figure 33. Small Signal Pulse Response, Gain = −1

100mV

100

90

V

IN

10ns

Figure 36. Closed-Loop Gain vs. Frequency, Gain = −10

100

90

V

IN

1V

FREQUENCY (MHz)

20ns

00866-E-036

10

V

OUT

0%

1V

Figure 34. Small Signal Pulse Response, Gain = −10

00866-E-034

10

V

OUT

0%

10V

Figure 37. Large Signal Pulse Response, Gain = −10

Rev. E | Page 11 of 20

00866-E-037

AD811

www.BDTIC.com/ADI

APPLICATIONS

GENERAL DESIGN CONSIDERATIONS

The AD811 is a current feedback amplifier optimized for use in
high performance video and data acquisition applications.
Because it uses a current feedback architecture, its closed-loop

−3 dB bandwidth is dependent on the magnitude of the feed­back resistor. The desired closed-loop gain and bandwidth are
obtained by varying the feedback resistor (R
bandwidth and by varying the gain resistor (R
correct gain. Table 3 contains recommended resistor values for a
variety of useful closed-loop gains and supply voltages.

Table 3. −3 dB Bandwidth vs. Closed-Loop Gain and
Resistan

VS = ±15 V
Closed-Loop Gain RFB RG −3 dB BW (MHz)

+1 750 Ω 140
+2 649 Ω 649 Ω 120
+10 511 Ω 56.2 Ω 100

−1

−10 511 Ω 51.1 Ω 95

VS = ±5 V
Closed-Loop Gain RFB R

+1 619 Ω 80
+2 562 Ω 562 Ω 80
+10 442 Ω 48.7 Ω 65

−1

−10
VS = ±10 V
Closed-Loop Gain RFB R

+1 649 Ω 105
+2 590 Ω 590 Ω 105
+10 499 Ω 49.9 Ω 80

−1 590 Ω 590 Ω 105

−10 499 Ω 49.9 Ω 80

Figure 18 and Figure 19 illustrate the relationship between the
feedback resistor and the frequency and time domain response
characteristics for a closed-loop gain of +2. (The response at
other gains is similar.)

The 3 dB bandwidth is somewhat dependent on the power
su
the magnitude of the internal junction capacitances is increased,
causing a reduction in closed-loop bandwidth. To compensate
for this, smaller values of feedback resistor are used at lower
supply voltages.

ce Values

590 Ω 590 Ω 115

G

562 Ω 562 Ω 75
442 Ω 44.2 Ω 65

G

pply voltage. As the supply voltage is decreased, for example,

) to tune the

FB

) to obtain the

G

−3 dB BW (MHz)

−3 dB BW (MHz)

ACHIEVING THE FLATTEST GAIN RESPONSE AT HIGH FREQUENCY

Achieving and maintaining gain flatness of better than 0.1 dB at
frequencies above 10 MHz requires careful consideration of
several issues.

Choice of Feedback and Gain Resistors

Because of the previously mentioned relationship between the
3 dB bandwidth and the feedback resistor, the fine scale gain
flatness varies, to some extent, with feedback resistor tolerance.
Therefore, it is recommended that resistors with a 1% tolerance
be used if it is desired to maintain flatness over a wide range of
production lots. In addition, resistors of different construction
have different associated parasitic capacitance and inductance.
Metal film resistors were used for the bulk of the character­ization for this data sheet. It is possible that values other than
those indicated are optimal for other resistor types.

Printed Circuit Board Layout Considerations

As is expected for a wideband amplifier, PC board parasitics can
affect the overall closed-loop performance. Of concern are stray
capacitances at the output and the inverting input nodes. If a
ground plane is used on the same side of the board as the signal
traces, a space (3/16" is plenty) should be left around the signal
lines to minimize coupling. Additionally, signal lines connecting
the feedback and gain resistors should be short enough so that
their associated inductance does not cause high frequency gain
errors. Line lengths less than 1/4" are recommended.

Quality of Coaxial Cable

Optimum flatness when driving a coax cable is possible only
when the driven cable is terminated at each end with a resistor
matching its characteristic impedance. If the coax is ideal, then
the resulting flatness is not affected by the length of the cable.
While outstanding results can be achieved using inexpensive
cables, note that some variation in flatness due to varying cable
lengths may occur.

Power Supply Bypassing

Adequate power supply bypassing can be critical when optimiz­ing the performance of a high frequency circuit. Inductance in
the power supply leads can form resonant circuits that produce
peaking in the amplifier’s response. In addition, if large current
transients must be delivered to the load, then bypass capacitors
(typically greater than 1 µF) are required to provide the best
settling time and lowest distortion. Although the recommended

0.1 µF power supply bypass capacitors are sufficient in many
applications, more elaborate bypassing (such as using two
paralleled capacitors) may be required in some cases.

Rev. E | Page 12 of 20

AD811

V

www.BDTIC.com/ADI

Driving Capacitive Loads

The feedback and gain resistor values in Table 3 result in very
flat closed-loop responses in applications where the load capaci­tances are below 10 pF. Capacitances greater than this result in
increased peaking and overshoot, although not necessarily in a
sustained oscillation.

There are at least two very effective ways to compensate for this
effect. One way is to increase the magnitude of the feedback
resistor, which lowers the 3 dB frequency. The other method is
to include a small resistor in series with the output of the ampli­fier to isolate it from the load capacitance. The results of these
two techniques are illustrated in Figure 39. Using a 1.5 kΩ
feedback resistor, the output ripple is less than 0.5 dB when
driving 100 pF. The main disadvantage of this method is that it
sacrifices a little bit of gain flatness for increased capacitive load
drive capability. With the second method, using a series resistor,
the loss of flatness does not occur.

R

FB

+V

S

0.1µF

R

G

IN

R

T

2

3

0.1µF

–

AD811

+

7

RS (OPTIONAL)

6

C

4

L

V

OUT

R

L

100

90

80

70

)

Ω

(

60

S

50

40

VALUE OF R

30

20

10

0

10 100 1000

LOAD CAPACITANCE (pF)

GAIN = +2
V

= ±15V

S

R

VALUE SPECIFIED

S

IS FOR FLATTEST
FREQUENCY RESPONSE

Figure 40. Recommended Value of Series Resistor vs.

the Amount of Capacitive Load

Figure 40 shows recommended resistor values for different load
capacitances. Refer again to Figure 39 for an example of the
results of this method. Note that it may be necessary to adjust
the gain setting resistor, R
results due to the divider formed by the series resistor, R

, to correct for the attenuation which

G

, and

S

the load resistance.

Applications that require driving a large load capacitance at a
high slew rate are often limited by the output current available
from the driving amplifier. For example, an amplifier limited to
25 mA output current cannot drive a 500 pF load at a slew rate
greater than 50 V/µs. However, because of the AD811’s 100 mA
output current, a slew rate of 200 V/µs is achievable when driv­ing the same 500 pF capacitor, as shown in Figure 41.

00866-E-040

–V

S

Figure 38. Recommended Connection for Driving a Large Capacitive Load

12

9

6

3

GAIN (dB)

VS = ±15V
C

= 100pF

L

0

R

= 10kΩ

L

GAIN = +2

–3

–6

1 10 100

FREQUENCY (MHz)

R
R

= 649Ω

FB

= 30Ω

S

R
R

= 1.5kΩ

FB

= 0

S

Figure 39. Performance Comparison of Two Methods

for Driving a Capacitive Load

00866-E-038

100

V

90

IN

10

V

OUT

0%

2V

100ns

5V

00866-E-041

Figure 41. Output Waveform of an AD811 Driving a 500 pF Load.

Gain = +2, R

00866-E-039

= 649 Ω, RS = 15 Ω, RS = 10 kΩ

FB

Rev. E | Page 13 of 20

AD811

V

www.BDTIC.com/ADI

OPERATION AS A VIDEO LINE DRIVER

The AD811 has been designed to offer outstanding perform­ance at closed-loop gains of +1 or greater, while driving
multiple reverse-terminated video loads. The lowest differential
gain and phase errors are obtained when using ±15 V power
supplies. With ±12 V supplies, there is an insignificant increase
in these errors and a slight improvement in gain flatness.
Due to power dissipation considerations, ±12 V supplies are
recommended for optimum video performance. Excellent
performance can be achieved at much lower supplies as well.

The closed-loop gain versus the frequency at different supply
voltages is shown in Figure 43. Figure 44 is an oscilloscope
photograph of an AD811 line driver’s pulse response with ±15 V
supplies. The differential gain and phase error versus the supply
are plotted in Figure 45 and Figure 46, respectively.

Another important consideration when driving multiple cables
is the high frequency isolation between the outputs of the
cables. Due to its low output impedance, the AD811 achieves
better than 40 dB of output-to-output isolation at 5 MHz
driving back-terminated 75 Ω cables.

649Ω649Ω

+V

S

0.1µF

–

+

7

AD811

4

–V

S

75Ω CABLE

IN

2

3

75Ω

0.1µF

Figure 42. A Video Line Driver Operating at a Gain of +2

12

G = +2

9

R

= 150Ω

L

= R

R

G

FB

6

3

GAIN (dB)

0

–3

–6

1 10 100

FREQUENCY (MHz)

Figure 43. Closed-Loop Gain vs. Frequency, Gain = +2

75Ω CABLE

75Ω

75Ω CABLE

6

75Ω

= ±5V

V

S

= 562Ω

R

FB

75Ω

75Ω

VS = ±15V

= 649Ω

R

FB

V

No. 1

OUT

V

No. 2

OUT

00866-E-042

00866-E-043

V

V

OUT

1V

100

90

IN

10
0%

10ns

1V

00866-E-044

Figure 44. Small Signal Pulse Response, Gain = +2, V

0.10

0.09

0.08

0.07

0.06

0.05

0.04

0.03

DIFFERENTIAL GAIN (%)

0.02
b

a

0.01

0

56789101112131415

a. DRIVING A SINGLE, BACK­ TERMINATED, 75Ω COAX CABLE
b. DRIVING TWO PARALLEL, BACK­ TERMINATED, COAX CABLES

SUPPLY VOLTAGE (V)

RF = 649Ω

= 3.58MHz

F

C

100 IRE
MODULATED RAMP

= ±15 V

S

00866-E-045

Figure 45. Differential Gain Error vs. Supply Voltage for

the Video Line Driver of Figure 42

0.20

0.18

0.16

DIFFERENTIAL PHASE (DEGREES)

0.14

0.12

0.10

0.08

0.06

0.04

0.02

0

b

a. DRIVING A SINGLE, BACK­ TERMINATED, 75Ω COAX CABLE

a

56789101112131415

b. DRIVING TWO PARALLEL, BACK­ TERMINATED, COAX CABLES

SUPPLY VOLTAGE (V)

RF = 649Ω

= 3.58MHz

F

C

100 IRE
MODULATED RAMP

00866-E-046

Figure 46. Differential Phase Error vs. Supply Voltage for

the Video Line Driver of Figure 42

Rev. E | Page 14 of 20

AD811

www.BDTIC.com/ADI

AN 80 MHZ VOLTAGE-CONTROLLED AMPLIFIER CIRCUIT

The voltage-controlled amplifier (VCA) circuit of Figure 48
shows the AD811 being used with the AD834, a 500 MHz,
4-quadrant multiplier. The AD834 multiplies the signal
input by the dc control voltage, V
the form of differential currents from a pair of open collectors,
ensuring that the full bandwidth of the multiplier (which
exceeds 500 MHz) is available for certain applications. Here, the
AD811 op amp provides a buffered, single-ended, ground­referenced output. Using feedback resistors R8 and R9 of 511 Ω,
the overall gain ranges from −70 dB for V
(a numerical gain of +4) when V
function of the VCA is V
reduces to V

= 4 VG VIN using the labeling conventions

OUT

OUT

shown in Figure 47. The circuit’s −3 dB bandwidth of 80 MHz is
maintained essentially constant—that is, independent of gain.
The response can be maintained flat to within ±0.1 dB from dc
to 40 MHz at full gain with the addition of an optional capacitor
of about 0.3 pF across the feedback resistor R8. The circuit
produces a full-scale output of ±4 V for a ±1 V input and can
drive a reverse-terminated load of 50 Ω or 75 Ω to ±2 V.

. The AD834 outputs are in

G

= 0 dB to +12 dB

G

= 1 V. The overall transfer

G

= 4 (X1 − X2)(Y1 − Y2), which

The gain can be increased to 20 dB (×10) by raising R8 and R9
to 1.27 kΩ, with a corresponding decrease in −3 dB bandwidth
to approximately 25 MHz. The maximum output voltage under
these conditions is increased to ±9 V using ±12 V supplies.

The gain-control input voltage, V

, may be a positive or negative

G

ground-referenced voltage, or fully differential, depending on
the choice of connections at Pins 7 and 8. A positive value of V
results in an overall noninverting response. Reversing the sign

simply causes the sign of the overall response to invert. In

of V

G

fact, although this circuit has been classified as a voltage­controlled amplifier, it is also quite useful as a general-purpose,
four-quadrant multiplier, with good load driving capabilities
and fully symmetrical responses from the X and Y inputs.

The AD811 and AD834 can both be operated from power
supply voltages of ±5 V. While it is not necessary to power them
from the same supplies, the common-mode voltage at W1 and
W2 must be biased within the common-mode range of the
AD811’s input stage. To achieve the lowest differential gain and
phase errors, it is recommended that the AD811 be operated
from power supply voltages of ±10 V or greater. This VCA
circuit operates from a ±12 V dual power supply.

G

FB

C1

0.1µF

+

V

G

–

V

IN

R1 100Ω

R2 100Ω

8765

X2

X1 +V

AD834

Y1 Y2 W2

1234

249Ω

W1

S

U1

–V

S

R3

*R8 = R9 = 511Ω FOR ×4 GAIN

R8 = R9 = 1.27kΩ FOR ×10 GAIN

182Ω

182Ω

R4

R5

294Ω

294Ω

R6

R7

R8*

R9*

–

+

7

U3

AD811

4

C2

0.1µF

6

R

FB

2

3

Figure 47. An 80 MHz Voltage-Controlled Amplifier

+12V

V

OUT

L

–12V

00866-E-047

Rev. E | Page 15 of 20

AD811

www.BDTIC.com/ADI

A VIDEO KEYER CIRCUIT

By using two AD834 multipliers, an AD811, and a 1 V dc source,
a special form of a two-input VCA circuit called a video keyer
can be assembled. Keying is the term used in reference to blend­ing two or more video sources under the control of a third
signal or signals to create such special effects as dissolves and
overlays. The circuit shown in Figure 48 is a two-input keyer,
with video inputs V
transfer function (with V

= GVA + (1−G)V

V

OUT

where G is a dimensionless variable (actually, just the gain of the
A signal path) that ranges from 0 when V
1 V. Thus, V

OUT

varies from 0 to 1.

Circuit operation is straightforward. Consider first the signal
path through U1, which handles video input V
clearly 0 when V
a unity value when V
the transfer function. On the other hand, the V
taken to the inverting input X2 while X1 is biased at an accurate

V

G

(0 TO +1V dc)

(±1V FS)

V

A

and VB, and a control input VG. The

A

at the load) is given by

OUT

B

= 0 to 1 when VG =

G

varies continuously between VA and VB as G

. Its gain is

A

= 0, and the scaling chosen ensures that it has

G

= 1 V; this takes care of the first term of

G

input to U2 is

G

+5V

R7

X1 +V

U1

AD834

–5V

X1 +V

U1

AD834

45.3Ω

S

–V

S

S

R5

113Ω

1.87kΩ

174Ω

100Ω

1.02kΩ

R6

226Ω

8765

+5V

R1

U4

AD589

R2

R3

R4

X2

Y1 Y2 W2

1234

8765

X2

W1

W1

1 V. Thus, when V
at its full-scale value of unity, whereas when V

= 0, the response to video input VB is already

G

= 1 V, the differ-

G

ential input X1−X2 is 0. This generates the second term.

The bias currents required at the output of the multipliers are
provided by R8 and R9. A dc level-shifting network comprising
R10/R12 and R11/R13 ensures that the input nodes of the
AD811 are positioned at a voltage within its common-mode
range. At high frequencies, C1 and C2 bypass R10 and R11,
respectively. R14 is included to lower the HF loop gain and is
needed because the voltage-to-current conversion in the
AD834s, via the Y2 inputs, results in an effective value of the
feedback resistance of 250 Ω; this is only about half the value
required for optimum flatness in the AD811’s response. (Note
that this resistance is unaffected by G: when G = +1, all the
feedback is via U1, while when G = 0 it is all via U2). R14
reduces the fractional amount of output current from the
multipliers into the current-summing inverting input of the
AD811 by sharing it with R8. This resistor can be used to adjust
the bandwidth and damping factor to best suit the application.

C1

2.49kΩ

R8

29.4Ω

R9

29.4Ω

0.1µF

R10

+5V

C2

R14

SEE TEXT

R12

6.98kΩ

R13

6.98kΩ

–5V

SETUP FOR DRIVING
REVERSE-TERMINATED LOAD

Z

200Ω

200Ω

C3

0.1µF

C4

0.1µF

O

2

3

TO PIN 6

AD811

TO Y2

FB

–

AD811

+

+5V

7

U3

4

6

LOAD

GND

V

OUT

Z

O

INSET

V

OUT

0.1µF

FB

V

(±1V FS)

B

–V

Y1 Y2 W2

1234

S

–5V

R11

2.49kΩ

Figure 48. A Practical Video Keyer Circuit

Rev. E | Page 16 of 20

–5V

LOAD

GND

00866-E-048

AD811

www.BDTIC.com/ADI

To generate the 1 V dc needed for the 1−G term, an AD589
reference supplies 1.225 V ± 25 mV to a voltage divider consist­ing of resistors R2 through R4. Potentiometer R3 should be
adjusted to provide exactly 1 V at the X1 input.

In this case, an arrangement is shown using dual supplies of
±5 V for both the AD834 and the AD811. Also, the overall gain
is arranged to be unity at the load when it is driven from a
reverse-terminated 75 Ω line. This means that the dual VCA has
to operate at a maximum gain of +2, rather than +4 as in the
VCA circuit of Figure 47. However, this cannot be achieved by
lowering the feedback resistor because below a critical value
(not much less than 500 Ω) the AD811’s peaking may be
unacceptable. This is because the dominant pole in the open­loop ac response of a current feedback amplifier is controlled

by
this feedback resistor. It would be possible to operate at a gain of
×4 and then attenuate the signal at the output. Instead, the
signals have been attenuated by 6 dB at the input to the AD811;
this is the function of R8 through

R11.

Figure 49 is a plot of the ac response of the feedback keyer when
driving a reverse-terminated 50 Ω cable. Output noise and
adjacent channel feedthrough, with either channel fully off and
the other fully on, is about −50 dB to 10 MHz. The feedthrough

at 100 MHz is limited primarily by board layout. For V
the −3 dB bandwidth is 15 MHz when using a 137 Ω resistor for
R14 and 70 MHz with R14 = 49.9 Ω. For more information on
the design and operation of the VCA and video keyer circuits,
refer to the application note “Video VCAs and Keyers: Using the
AD834 and AD811” by Brunner, Clarke, and Gilbert, available
on the Analog Devices, Inc. website at www.analog.com.

10

0

–10

–20

–30

–40

–50

–60

CLOSED-LOOP GAIN (dB)

–70

–80

–90

Figure 49. A Plot of the AC Response of the Video Keyer

GAIN

ADJACENT CHANNEL

FEEDTHROUGH

100k10k 1M 10M 100M

FREQUENCY (Hz)

R14 = 49.9Ω

R14 = 137Ω

= 1 V,

G

00866-E-049

Rev. E | Page 17 of 20

AD811

Y

www.BDTIC.com/ADI

OUTLINE DIMENSIONS

0.375 (9.53)

0.365 (9.27)

0.355 (9.02)

8

1

0.100 (2.54)

0.180
(4.57)

MAX

0.150 (3.81)

0.130 (3.30)

0.110 (2.79)

0.022 (0.56)

0.018 (0.46)

0.014 (0.36)

CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN

COMPLIANT TO JEDEC STANDARDS MO-095AA

BSC

5

4

0.295 (7.49)

0.285 (7.24)

0.275 (6.98)

0.015
(0.38)

MIN

SEATING
PLANE

0.060 (1.52)

0.050 (1.27)

0.045 (1.14)

0.325 (8.26)

0.310 (7.87)

0.300 (7.62)

0.150 (3.81)

0.135 (3.43)

0.120 (3.05)

0.015 (0.38)

0.010 (0.25)

0.008 (0.20)

5.00 (0.1968)

4.80 (0.1890)

4.00 (0.1574)

3.80 (0.1497)

0.25 (0.0098)

0.10 (0.0040)

COPLANARIT

0.10

CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN

85

1.27 (0.0500)

SEATING

PLANE

COMPLIANT TO JEDEC STANDARDS MS-012AA

BSC

6.20 (0.2440)

5.80 (0.2284)

41

1.75 (0.0688)

1.35 (0.0532)

0.51 (0.0201)

0.31 (0.0122)

0.25 (0.0098)

0.17 (0.0067)

0.50 (0.0196)

0.25 (0.0099)

8°

1.27 (0.0500)

0°

0.40 (0.0157)

×

45°

Figure 52. 8-Lead Standard Small Outline Package [SOIC]

Narrow Body (R-8)

Dimensions shown in millimeters and (inches)

Figure 50. 8-Lead Plastic Dual In-Line Package [PDIP]

(N-8)

Dimensions shown in inches and (millimeters)

0.005 (0.13)

PIN 1

0.200 (5.08)
MAX

0.200 (5.08)

0.125 (3.18)

0.023 (0.58)

0.014 (0.36)

CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN

0.055 (1.40)

MIN

0.100 (2.54) BSC

0.405 (10.29) MAX

MAX

85

0.310 (7.87)

4

0.070 (1.78)

0.030 (0.76)

0.220 (5.59)

0.060 (1.52)

0.015 (0.38)

1

0.150 (3.81)
MIN

SEATING
PLANE

0.320 (8.13)

0.290 (7.37)

15°

0°

0.015 (0.38)

0.008 (0.20)

Figure 51. 8-Lead Ceramic Dual In-Line Package [CERDIP]

(Q-8)

Dimensions shown in inches and (millimeters)

20

1

VIEW

0.150 (3.81)
BSC

0.200 (5.08)
REF

0.100 (2.54) REF

0.015 (0.38)
MIN

3

4

0.028 (0.71)

0.022 (0.56)

0.050 (1.27)

8

BSC

9

45° TYP

0.075 (1.91)

0.095 (2.41)

0.075 (1.90)

0.011 (0.28)

0.007 (0.18)
R TYP

0.075 (1.91)
REF

0.055 (1.40)

0.045 (1.14)

REF

19

18

14

13

BOTTOM

0.100 (2.54)

0.064 (1.63)

0.358 (9.09)

0.342 (8.69)
SQ

CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN

0.358
(9.09)

MAX

0.088 (2.24)

0.054 (1.37)

SQ

Figure 53. 20-Terminal Ceramic Leadless Chip Carrier [LCC]

(E-20A)

Dimensions shown in inches and (millimeters)

Rev. E | Page 18 of 20

AD811

www.BDTIC.com/ADI

10.50 (0.4134)

10.10 (0.3976)

13.00 (0.5118)

12.60 (0.4961)

16

1

1.27 (0.0500)
BSC

0.30 (0.0118)

0.10 (0.0039)

COPLANARITY

0.10

CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN

0.51 (0.0201)

0.31 (0.0122)

COMPLIANT TO JEDEC STANDARDS MS-013AA

9

7.60 (0.2992)

7.40 (0.2913)

8

2.65 (0.1043)

2.35 (0.0925)

SEATING
PLANE

10.65 (0.4193)

10.00 (0.3937)

0.33 (0.0130)

0.20 (0.0079)

8°
0°

Figure 54. 16-Lead Standard Small Outline Package [SOIC]

Wide Body (R-16)

Dimensions shown in millimeters and (inches)

0.75 (0.0295)

0.25 (0.0098)

1.27 (0.0500)

0.40 (0.0157)

× 45°

20 11

1

0.30 (0.0118)

0.10 (0.0039)

1.27

COPLANARITY

0.10

COMPLIANT TO JEDEC STANDARDS MS-013AC
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN

(0.0500)

BSC

0.51 (0.0201)

0.31 (0.0122)

7.60 (0.2992)

7.40 (0.2913)

10

2.65 (0.1043)

2.35 (0.0925)

SEATING
PLANE

10.65 (0.4193)

10.00 (0.3937)

0.33 (0.0130)

0.20 (0.0079)

0.75 (0.0295)

0.25 (0.0098)

8°
0°

× 45°

1.27 (0.0500)

0.40 (0.0157)

Figure 55. 20-LeadStandard Small Outline Package [SOIC]

Wide Body (R-20)

Dimensions shown in millimeters and (inches)

Rev. E | Page 19 of 20

AD811

www.BDTIC.com/ADI

ORDERING GUIDE

Model Temperature Range Package Description Package Option

AD811AN −40°C to +85°C 8-Lead Plastic Dual In-Line Package (PDIP) N-8
AD811ANZ
AD811AR-16 −40°C to +85°C 16-LeadStandard Small Outline Package (SOIC) R-16
AD811AR-16-REEL −40°C to +85°C 16-LeadStandard Small Outline Package (SOIC) R-16
AD811AR-16-REEL7 −40°C to +85°C 16-LeadStandard Small Outline Package (SOIC) R-16
AD811AR-20 −40°C to +85°C 20-LeadStandard Small Outline Package (SOIC) R-20
AD811AR-20-REEL −40°C to +85°C 20-LeadStandard Small Outline Package (SOIC) R-20
AD811JR 0°C to +70°C 8-LeadStandard Small Outline Package (SOIC) R-8
AD811JR-REEL 0°C to +70°C 8-LeadStandard Small Outline Package (SOIC) R-8
AD811JR-REEL7 0°C to +70°C 8-LeadStandard Small Outline Package (SOIC) R-8
AD811JRZ1 0°C to +70°C 8-LeadStandard Small Outline Package (SOIC) R-8
AD811SQ/883B −55°C to +125°C 8-Lead Ceramic Dual In-Line Package (CERDIP) Q-8
5962-9313101MPA −55°C to +125°C 8-Lead Ceramic Dual In-Line Package (CERDIP) Q-8
AD811SE/883B −55°C to +125°C 20-Terminal Ceramic Leadless Chip Carrier (LCC) E-20A
5962-9313101M2A −55°C to +125°C 20-Terminal Ceramic Leadless Chip Carrier (LCC) E-20A
AD811ACHIPS −40°C to +85°C DIE
AD811SCHIPS −55°C to +125°C DIE

1

Z = Pb-free part.

1

−40°C to +85°C 8-Lead Plastic Dual In-Line Package (PDIP) N-8

© 2004 Analog Devices, Inc. All rights reserved. Trademarks and regis­tered trademarks are the property of their respective owners.

C00866–0–7/04(E)

Rev. E | Page 20 of 20