ANALOG DEVICES AD8106, AD8107 Service Manual

260 MHz, 16 × 5 Buffered

FEATURES

16 × 5 high speed, nonblocking switch arrays

AD8106: G = 1, AD8107: G = 2

Pin compatible with AD8110/AD8111, 16 × 8 switch arrays

For a 16 × 16 array, see
For a 16 x 8 array, see AD8110/AD8111

Complete solution

Buffered inputs
Five output amplifiers
Drives 150

Ω loads

Excellent video performance

60 MHz 0.1 dB gain flatness

0.02% differential gain error (R

0.028 differential phase error (RL = 150 Ω)

Excellent ac performance

−3 dB bandwidth > 260 MHz

500 V/μs slew rate
Low power of 50 mA
Low all-hostile crosstalk of −78 dB @ 5 MHz
Output disable allows connection of multiple device outputs
Reset pin allows disabling of all outputs
Excellent ESD rating: Exceeds 4000 V human body model
80-lead LQFP (12 mm × 12 mm)

APPLICATIONS

Routing of high speed signals including:

Composite video (NTSC, PAL, S, SECAM)

Component video (YUV, RGB)

Compressed video (MPEG, Wavelet)

3-level digital video (HDB3)

AD8114/AD8115

= 150 Ω)

L

Video Crosspoint Switches

AD8106/AD8107

FUNCTIONAL BLOCK DIAGRAM

D0 D1 D2 D3 D4

CLK

25-BIT REGISTER

(RANK 1)

UPDATE

CE

RESET

5 × 5:16 DECODERS

AD8106/AD8107

16 INPUTS

25

PARALLEL LATCH

(RANK 2)

25

DECODE

80

SWITCH

MATRIX

Figure 1.

SET INDI VIDUAL
OR RESET ALL
OUTPUTS
TO OFF

OUTPUT
BUFFER

G = 1,

G = 2

5

A0
A1

A2

5 OUTPUTS

ENABLE/DISABLE

05774-001

GENERAL DESCRIPTION

The AD8106 and AD8107 are high speed, 16 × 5 video crosspoint
switch matrices. They offer a −3 dB signal bandwidth greater
than 260 MHz, and channel switch times of less than 25 ns
with 1% settling. With −78 dB of crosstalk and
(@ 5 MHz), the AD8106/AD8107 are useful in many high speed
applications. The differential gain and differential phase of
greater than 0.02% and 0.02° respectively, along with 0.1 dB
flatness out to 60 MHz, make the AD8106/AD8107 ideal for
video signal switching.

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

−97 dB isolation

The AD8106 and AD8107 include five independent output
buffers that can be placed into a high impedance state for parallel­ing crosspoint outputs, preventing off channels from loading the
output bus. The AD8106 has a gain of 1, while the AD8107
offers a gain of 2. Both operate on voltage supplies of ±5 V while
consuming only 30 mA of idle current. The channel switching is
performed via a parallel control, allowing updating of an
individual output without reprogramming the entire array.

The AD8106/AD8107 are offered in an 80-lead LQFP and are
available over the extended industrial temperature range of

−40°C to +85°C.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] ©2006 Analog Devices, Inc. All rights reserved.

AD8106/AD8107

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications....................................................................................... 1

Functional Block Diagram .............................................................. 1

General Description......................................................................... 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

Timing Characteristics ................................................................ 5

Absolute Maximum Ratings............................................................ 6

Maximum Power Dissipation ..................................................... 6

ESD Caution.................................................................................. 6

Pin Configuration and Function Descriptions............................. 8

I/O Schematics.................................................................................. 9

Typical Performance Characteristics ........................................... 10

REVISION HISTORY

Theory of Operation ...................................................................... 16

Power-On Reset .......................................................................... 16

Initialization ................................................................................ 16

Gain Selection............................................................................. 16

Creating Larger Crosspoint Arrays.......................................... 16

Crosstalk ...................................................................................... 18

PCB Layout ................................................................................. 19

Evaluation Board ............................................................................ 21

Controlling the Evaluation Board from a PC ......................... 25

Data-Line Overshoot on Printer Ports.................................... 25

Outline Dimensions ....................................................................... 27

Ordering Guide .......................................................................... 27

3/06—Revision 0: Initial Version

Rev. 0 | Page 2 of 28

AD8106/AD8107

SPECIFICATIONS

VS = ±5 V, TA = 25°C, RL = 1 kΩ, unless otherwise noted.

Table 1.

Parameter Conditions Min Typ Max Unit Reference

DYNAMIC PERFORMANCE

−3 dB Bandwidth 200 mV p-p, RL = 150 Ω 300/190 390/260 MHz Figure 10, Figure 16
2 V p-p, RL = 150 Ω 150 MHz Figure 10, Figure 16
Propagation Delay 2 V p-p, RL = 150 Ω 5 ns
Slew Rate 2 V step, RL = 150 Ω 500 V/μs
Settling Time 0.1%, 2 V step, RL = 150 Ω 40 ns Figure 15, Figure 21
Gain Flatness 0.05 dB, 200 mV p-p, RL = 150 Ω 60/40 MHz Figure 10, Figure 16

0.05 dB, 2 V p-p, RL = 150 Ω 65/40 MHz Figure 10, Figure 16

0.1 dB, 200 mV p-p, RL = 150 Ω 80/57 MHz Figure 10, Figure 16

0.1 dB, 2 V p-p, RL = 150 Ω 70/57 MHz Figure 10, Figure 16
NOISE/DISTORTION PERFORMANCE

Differential Gain Error NTSC or PAL, RL = 1 kΩ 0.01 %
NTSC or PAL, RL = 150 Ω 0.02 %
Differential Phase Error NTSC or PAL, RL = 1 kΩ 0.01 Degrees
NTSC or PAL, RL = 150 Ω 0.02 Degrees
Crosstalk, All Hostile f = 5 MHz 78/85 dB Figure 11, Figure 17
f = 10 MHz 70/80 dB Figure 11, Figure 17
Off Isolation, Input/Output f = 10 MHz, RL = 150 Ω, one channel 93/99 dB Figure 26, Figure 32
Input Voltage Noise 0.01 MHz to 50 MHz 15 nV/√Hz Figure 23, Figure 29

DC PERFORMANCE

Gain Error RL = 1 kΩ 0.04/0.1 0.07/0.5 %
R
Gain Matching No load, channel-to-channel 0.02/1.0 %

R

Gain Temperature Coefficient 0.5/8 ppm/°C

OUTPUT CHARACTERISTICS

Output Impedance DC, enabled 0.2 Ω Figure 27, Figure 33
Disabled 10/0.001 MΩ Figure 24, Figure 30
Output Disable Capacitance Disabled 2 pF
Output Leakage Current Disabled, AD8106 only 1/NA μA
Output Voltage Range No load ±2.5 ±3 V
Output Current 20 40 mA
Short-Circuit Current 65 mA

INPUT CHARACTERISTICS

Input Offset Voltage Worst case (all configurations) 5 20 mV Figure 38, Figure 44
Temperature coefficient 12 μV/°C Figure 39, Figure 45
Input Voltage Range ±2.5/±1.25 ±3/±1.5 V
Input Capacitance Any switch configuration 2.5 pF
Input Resistance 1 10 MΩ
Input Bias Current Per output selected 2 5 μA

SWITCHING CHARACTERISTICS

Enable On Time 60 ns
Switching Time, 2 V Step

Switching Transient (Glitch) Measured at output 20/30 mV p-p Figure 25, Figure 31

= 150 Ω 0.15/0.25 %

L

= 1 kΩ, channel-to-channel 0.09/1.0 %

L

50%

UPDATE

to 1% settling

25 ns

Rev. 0 | Page 3 of 28

AD8106/AD8107

Parameter Conditions Min Typ Max Unit Reference

POWER SUPPLIES

Supply Current AVCC, outputs enabled, no load 30 mA

AVCC, outputs disabled 15 mA

AVEE, outputs enabled, no load 30 mA

AVEE, outputs disabled 15 mA

DVCC 11 mA

Supply Voltage Range ±4.5 to ±5.5 V

PSRR f = 100 kHz 75/78 dB Figure 22, Figure 28
f = 1 MHz −55/−58 dB
OPERATING TEMPERATURE

Temperature Range Operating (still air) −40 to +85 °C

θJA

Operating (still air) 48 °C/W

Rev. 0 | Page 4 of 28

AD8106/AD8107

TIMING CHARACTERISTICS

Table 2.

Parameter Limit at T

t1 20 ns min Data setup time
t 100 ns min CLK pulse width

2

t 20 ns min Data hold time

3

t 100 ns min CLK pulse separation

4

t5 0 ns min
t6 50 ns min
– 8 ns max
– 100 ns max
– 200 ns min

, T Unit Description

MIN

MAX

UPDATE delay

CLK to
UPDATE pulse width
Propagation delay,

UPDATE rise and fall times

CLK,
RESET time

UPDATE to switch on or off

CLK

D0 TO D4
A0 TO A2

1 = LATCHED

0 = TRANSPARENT

UPDATE

t

1

0

1

0

t

1

2

t

3

t

4

Figure 2. Timing Diagram

Table 3. Logic Levels

VIH V I

RESET, CLK, D0, D1, D2, D3, D4,
A0, A1, A2, CE, UPDATE

IL IH

RESET, CLK, D0, D1, D2, D3, D4,
A0, A1, A2, CE, UPDATE

I

RESET, CLK, D0, D1, D2, D3, D4,
A0, A1, A2,

2.0 V min 0.8 V max 20 μA max

t

5

IL

t

6

05774-002

RESET, CLK, D0, D1, D2, D3, D4,
A0, A1, A2, CE, UPDATE CE, UPDATE

−400 μA min

Rev. 0 | Page 5 of 28

AD8106/AD8107

A

ABSOLUTE MAXIMUM RATINGS

Table 4.

Parameter Rating

Supply Voltage 12.0 V
Internal Power Dissipation

AD8106/AD8107 80-Lead LQFP (ST-80-1) 2.6 W
Input Voltage ±V
Output Short-Circuit Duration

θJA 48°C/W
Operating Temperature Range −40°C to 85°C
Storage Temperature Range −65°C to +125°C
Lead Temperature (Soldering 10 sec) 300°C

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

S

Observe power
derating curves

MAXIMUM POWER DISSIPATION

The maximum power that can be safely dissipated by the
AD8106/AD8107 is limited by the associated rise in junction
temperature. The maximum safe junction temperature for
plastic encapsulated devices is determined by the glass
transition temperature of the plastic, approximately 150°C.
Temporarily exceeding this limit can cause a shift in parametric
performance due to a change in the stresses exerted on the die
by the package.

Exceeding a junction temperature of 175°C for an extended
period can result in device failure.

While the AD8106/AD8107 is internally short-circuit
protected, this may not be sufficient to guarantee that the
maximum junction temperature (150°C) is not exceeded under
all conditions. To ensure proper operation, it is necessary to
observe the maximum power derating curves shown in

5

4

TION (W)

3

Figure 3.

TJ = 150°C

2

1

MAXIMUM POWER DISSIP

0

–50 80–40 –30 –20 –10 0 10 20 30 40 50 60 70

Figure 3. Maximum Power Dissipation vs. Temperature

AMBIENT TEMPERATURE (°C)

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.

05774-003

90

Rev. 0 | Page 6 of 28

AD8106/AD8107

Table 5. Operation Truth Table

CE UPDATE

CLK DATA IN DATA OUT

RESET

1 X X X X X No change in logic.
0 1 1

f

D0 … D4
A0 … A2

NA in parallel
mode

0 0 X X X 1

X X X X X 0

D0

DATA

D1
D2
D3
D4

PARALLEL

(OUTPUT
ENABLE)

Operation/Comment

The data on the parallel data lines, D0 to D4, are loaded into
the 40-bit serial shift register location addressed by A0 to A2.

Data in the 40-bit shift register transfers into the parallel
latches that control the switch array. Latches are transparent.

Asynchronous operation. All outputs are disabled.
Remainder of logic is unchanged.

CLK

CE

UPDATE

A0

A1

A2

3 TO 5 DECODER

(OUTPUT DI SABLE)

OUT0 EN

OUT1 EN

OUT2 EN

OUT3 EN

OUT4 EN

RESET

D

CLK

OUT0

D

D

CLK

OUT0

D

Q

Q

CLK

DLE

B2

Q

OUT0

B3

DLE

Q

Q

Q

CLK

DLE

DLE

OUT0

B0

B1

Q

Q

D

D

CLK

OUT0

EN

SWITCH MATRIX

Q

Q

CLK

DLE

OUT1

B0

QCLR

80

D

CLK

DLE

OUT3

Q

DECODE

EN

D

Q

CLK

DLE

QCLR

Q

OUT4

B0

D

CLK

DLE

Q

Q

DLE

OUT4

B1

Q

OUTPUT ENABL E

D

CLK

OUT4

D

Q

CLK

DLE

B2

Q

5

Q

OUT4

B3

D

Q

CLK

DLE

Q

OUT4

CLR

EN

DLE

Q

05774-004

Figure 4. Logic Diagram

Rev. 0 | Page 7 of 28

AD8106/AD8107

A

A

A

A

A

A

A

A

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

IN06

IN07

AGND

DVCC

IN08

GND

IN09

GND

IN10

GND

IN11

GND

IN12

GND

IN13

GND

IN14

GND

IN15

GND

AVE E

AVC C

AVC C

NC

DGND

80

79787776757473727170696867

1

2

PIN 1

3

INDICATO R

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

22

21

AVE E

AGND

23

NC

AGND

24

26

25

NC

AVC C

AGND

Figure 5. 80-Lead Plastic LQFP

Table 6. Pin Function Descriptions

Pin No. Mnemonic Description

64 , 66, 68, 70, 72, 74, 76, 78, 1,

INxx Analog Inputs; xx = Channel Numbers 00 through 15.

3, 5, 7, 9, 11, 13, 15,
58 CLK Clock, TTL Compatible. Falling edge triggered.
56

UPDATE

Enable (Transparent) Low. Allows serial register to connect directly to switch matrix. Data

latched when high.
61
60

RESET
CE

Disable Outputs, Active Low.

Chip Enable, Enable Low. Must be low to clock in and latch data.
41, 38, 35, 32, 29 OUTyy Analog Outputs; yy = Channel Numbers 00 Through 04.
2, 4, 6, 8, 10, 12, 14, 16, 21, 24, 27,

AGND Analog Ground for Inputs and Switch Matrix.

46, 65, 67, 69, 71, 73, 75, 77
63, 79 DVCC 5 V for Digital Circuitry.
62, 80 DGND Ground for Digital Circuitry.
17, 22, 45 AVEE −5 V for Inputs and Switch Matrix.
18, 19, 25, 44 AVCC +5 V for Inputs and Switch Matrix.
42, 39, 36, 33, 30 AGNDxx Ground for Output Amp; xx = Output Channel Numbers 00 Through 07. Must be connected.
43, 37, 31, 22 AVCCxx/yy +5 V for Output Amplifier. Shared by channel numbers xx and yy. Must be connected.
40, 34, 28 AVEExx/yy −5 V for Output Amplifier. Shared by channel numbers xx and yy. Must be connected.
54 A0 Parallel Data Input, TTL Compatible (Output Select LSB).
53 A1 Parallel Data Input, TTL Compatible (Output Select).
52 A2 Parallel Data Input, TTL Compatible (Output Select MSB).
51 D0 Parallel Data Input, TTL Compatible (Input Select LSB).
50 D1 Parallel Data Input, TTL Compatible (Input Select).
49 D2 Parallel Data Input, TTL Compatible (Input Select).
48 D3 Parallel Data Input, TTL Compatible (Input Select MSB).
47 D4 Parallel Data Input, TTL Compatible (Output Enable).

AGND

IN03

IN04

IN05

AGND

AD8106/AD8107

80L LQFP

(12mm × 12mm)

TOP VIEW

(PINS DOWN)

0.5mm LEAD PITCH

27

28

AGND

AVE E04

16 × 5

29

OUT04

AGND

31

30

32

OUT03

AGND04

VCC03/04

IN02

66

33

35

34

OUT02

AGND03

AVEE02/03

656463

37

36

AGND02

VCC01/02

DGND

RESET

62

61

60

CE

59

RESERVED

58

CLK

57

RESERVED

56

UPDATE

55

RESERVED

54

A0

53

A1

52

A2

51

D0

50

D1

49

D2

48

D3

47

D4

46

AGND

45

AVE E

44

AVC C

43

AVCC00

42

AGND00

41

OUT00

40

38

39

OUT01

AGND01

AVEE00/01

05774-010

IN00

DVCC

IN01

AGND

AGND

Rev. 0 | Page 8 of 28

AD8106/AD8107

V

V

V

V

I/O SCHEMATICS

CC

ESD

INPUT

ESD

RESET

CC

ESD

ESD

20kΩ

AV

EE

05774-005

Figure 6. Analog Input

CC

ESD

OUTPUT

1kΩ

ESD

(AD8107 ONLY)

AV

EE

05774-006

INPUT

Figure 7. Analog Output

DGND

RESET

Figure 8.

ESD

ESD

Input

CC

DGND

Figure 9. Logic Input

05774-007

05774-008

Rev. 0 | Page 9 of 28