ANALOG DEVICES AD8045 Service Manual

3 nV/√Hz Ultralow Distortion,

K

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FEATURES

Ultralow distortion SFDR

−101 dBc @ 5 MHz

−90 dBc @ 20 MHz

−63 dBc @ 70 MHz

Third-order intercept

43 dBm @ 10 MHz

Low noise

3 nV/√Hz 3 pA/√Hz

High speed

1 GHz, −3 dB bandwidth (G = +1) 1350 V/µs slew rate

7.5 ns settling time to 0.1%

Standard and low distortion pinout Supply current: 15 mA Offset voltage: 1.0 mV max Wide supply voltage range: 3.3 V to 12 V

GENERAL DESCRIPTION

The AD8045 is a unity gain stable voltage feedback amplifier with ultralow distortion, low noise, and high slew rate. With a spurious-free dynamic range of −90 dBc @ 20 MHz, the AD8045 is an ideal solution in a variety of applications, including ultrasound, ATE, active filters, and ADC drivers. ADI’s proprietary next generation XFCB process and innovative architecture enables such high performance amplifiers.

The AD8045 features a low distortion pinout for the LFCSP, which improves second harmonic distortion and simplifies the layout of the circuit board.

The AD8045 has 1 GHz bandwidth, 1350 V/µs slew rate, and settles to 0.1% in 7.5 ns. With a wide supply voltage range (3.3 V to 12 V) and low offset voltage (200 µV), the AD8045 is an ideal candidate for systems that require high dynamic range, precision, and high speed.

High Speed Op Amp

AD8045

APPLICATIONS

Instrumentation IF and baseband amplifiers Active filters ADC drivers DAC buffers

The AD8045 amplifier is available in a 3 mm × 3 mm LFCSP and the standard 8-lead SOIC. Both packages feature an exposed paddle that provides a low thermal resistance path to the PCB. This enables more efficient heat transfer, and increases reliability. The AD8045 works over the extended industrial temperature range (−40°C to +125°C).

–20

G = +1 V

–30

V R

–40

R

–50

–60

–70

–80

–90

–100

HARMONIC DISTORTION (dBc)

–110

–120

Figure 3. Harmonic Distortion vs. Frequency for Various Packages

CONNECTION DIAGRAMS

1

NC

–IN +IN

2 3 4

FEEDBAC

Figure 1. 8-Lead AD8045 LFCSP (CP-8)

FEEDBACK

1

2

–IN

3

+IN

4

–V

S

Figure 2. 8-Lead AD8045 SOIC/EP (RD-8)

=±5V

S

= 2V p-p

OUT

= 1kΩ

L

= 100Ω

S

HD3 LFCSP

FREQUENCY (MHz)

8 7 6 5

8

7

6

5

+V

S

OUTPUT NC –V

S

NC

+

V

S

OUTPUT

NC

04814-0-001

HD2 LFCSP

1000.1 1 10

04814-0-079

Rev. A

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

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SPECIFICATIONS WITH ±5 V SUPPLY

TA = 25°C, G = +1, RS = 100 Ω, RL = 1 kΩ to ground, unless noted otherwise. Exposed paddle must be floating or connected to −VS.

Table 1.

Parameter Conditions Min Typ Max Unit

DYNAMIC PERFORMANCE

–3 dB Bandwidth G = +1, V G = +1, V G = +2, V Bandwidth for 0.1 dB Flatness G = +2, V Slew Rate G = +1, V Settling Time to 0.1% G = +2, V

NOISE/HARMONIC PERFORMANCE

Harmonic Distortion (dBc) HD2/HD3 fC = 5 MHz, V LFCSP −102/−101 dBc SOIC −106/−101 dBc f LFCSP −98/−90 dBc SOIC −97/−90 dBc f LFCSP −71/−71 dBc SOIC −60/−71 dBc Input Voltage Noise f = 100 kHz 3 nV/√Hz Input Current Noise f = 100 kHz 3 pA/√Hz Differential Gain Error NTSC, G = +2, RL = 150 Ω 0.01 % Differential Phase Error NTSC, G = +2, R

DC PERFORMANCE

Input Offset Voltage 0.2 1.0 mV Input Offset Voltage Drift See Figure 54 8 µV/°C Input Bias Current Input Bias Current Drift 8 nA/°C Input Bias Offset Current 0.2 1.3 µA Open-Loop Gain V

INPUT CHARACTERISTICS

Input Resistance Common-mode/differential 3.6/1.0 MΩ Input Capacitance Common-mode 1.3 pF Input Common-Mode Voltage Range ±3.8 V Common-Mode Rejection VCM = ±1 V −83 −91 dB

OUTPUT CHARACTERISTICS

Output Overdrive Recovery Time VIN = ±3 V, G = +2 8 ns Output Voltage Swing RL = 1 kΩ −3.8 to +3.8 −3.9 to +3.9 V R Output Current 70 mA Short-Circuit Current Sinking/sourcing 90/170 mA Capacitive Load Drive 30% overshoot, G = +2 18 pF

POWER SUPPLY

Operating Range ±1.65 ±5 ±6 V Quiescent Current 16 19 mA Positive Power Supply Rejection +VS = +5 V to +6 V, −VS = −5 V −61 −68 dB Negative Power Supply Rejection +VS = +5 V, −VS = −5 V to −6 V −66 −73 dB

= 20 MHz, V

C

= 70 MHz, V

C

2 6.3 µA

OUT

= 100 Ω −3.4 to +3.5 −3.6 to +3.6 V

L

= 0.2 V p-p 1000 MHz

OUT

= 2 V p-p 300 350

OUT

= 0.2 V p-p 320 400 MHz

OUT

= 2 V p-p, RL = 150 Ω 55 MHz

OUT

= 4 V step 1000 1350 V/µs

OUT

= 2 V step 7.5 ns

OUT

= 2 V p-p

OUT

= 2 V p-p

OUT

= 2 V p-p

OUT

= 150 Ω 0.01 Degrees

L

= −3 V to +3 V 62 64 dB

Rev. A | Page 3 of 24

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SPECIFICATIONS WITH +5 V SUPPLY

TA = 25°C, G = +1, RS = 100 Ω, RL = 1 kΩ to midsupply, unless otherwise noted. Exposed paddle must be floating or connected to −VS.

Table 2.

Parameter Conditions Min Typ Max Unit

DYNAMIC PERFORMANCE

–3 dB Bandwidth G = +1, V

G = +1, V

G = +2, V

Bandwidth for 0.1 dB Flatness G = +2, V

Slew Rate G = +1, V

Settling Time to 0.1% G = +2, V NOISE/HARMONIC PERFORMANCE

Harmonic Distortion (dBc) HD2/HD3 fC = 5 MHz, V

LFCSP −89/−83 dBc

SOIC −92/−83 dBc

f

LFCSP −81/−70 dBc

SOIC −83/−70 dBc

f

LFCSP −57/−46 dBc

SOIC −57/−46 dBc

Input Voltage Noise f = 100 kHz 3 nV/√Hz

Input Current Noise f = 100 kHz 3 pA/√Hz

Differential Gain Error NTSC, G = +2, RL = 150 Ω 0.01 %

Differential Phase Error NTSC, G = +2, RL = 150 Ω 0.01 Degrees DC PERFORMANCE

Input Offset Voltage 0.5 1.4 mV

Input Offset Voltage Drift See Figure 54 7 µV/°C

Input Bias Current

Input Bias Current Drift 7 nA/°C

Input Bias Offset Current 0.2 1.3 µA

Open-Loop Gain V INPUT CHARACTERISTICS

Input Resistance Common-mode/differential 3/0.9 MΩ

Input Capacitance Common-mode 1.3 pF

Input Common-Mode Voltage Range 1.2 to 3.8 V

Common-Mode Rejection VCM = 2 V to 3 V −78 −94 dB OUTPUT CHARACTERISTICS

Output Overdrive Recovery Time VIN = −0.5 V to +3 V, G = +2 10 ns

Output Voltage Swing RL = 1 kΩ 2.2 to 3.7 1.1 to 4.0 V

R

Output Current 55 mA

Short-Circuit Current Sinking/sourcing 70/140 mA

Capacitive Load Drive 30% overshoot, G = +2 15 pF POWER SUPPLY

Operating Range 3.3 5 12 V

Quiescent Current 15 18 mA

Positive Power Supply Rejection +VS = +5 V to +6 V, −VS = 0 V −65 −67 dB

Negative Power Supply Rejection +VS = +5 V, −VS = 0 V to −1 V −70 −73 dB

= 20 MHz, V

C

= 70 MHz, V

C

2 6.6 µA

OUT

= 100 Ω 2.5 to 3.5 1.2 to 3.8 V

L

= 0.2 V p-p 900 MHz

OUT

= 2 V p-p 160 200 MHz

OUT

= 0.2 V p-p 320 395 MHz

OUT

= 2 V p-p, RL = 150 Ω 60 MHz

OUT

= 2 V step 480 1060 V/µs

OUT

= 2 V step 10 ns

OUT

= 2 V p-p

OUT

= 2 V p-p

OUT

= 2 V p-p

OUT

= 2 V to 3 V 61 63 dB

Rev. A | Page 4 of 24

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ABSOLUTE MAXIMUM RATINGS

Table 3.

Parameter Rating

Supply Voltage 12.6 V Power Dissipation See Figure 4 Common-Mode Input Voltage −VS − 0.7 V to +VS + 0.7 V Differential Input Voltage

Exposed Paddle Voltage −V

±V

S

Storage Temperature −65°C to +125°C Operating Temperature Range −40°C to +125°C Lead Temperature Range

300°C

(Soldering 10 sec)

Junction Temperature 150°C

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

THERMAL RESISTANCE

θJA is specified for the worst-case conditions, i.e., θJA is specified for device soldered in circuit board for surface-mount packages.

Table 4. Thermal Resistance

Package Type θ

JA

θ

JC

Unit

SOIC 80 30 °C/W LFCSP 93 35 °C/W

Maximum Power Dissipation

The maximum safe power dissipation for the AD8045 is limited by the associated rise in junction temperature (T

) on the die. At

J

approximately 150°C, which is the glass transition temperature, the properties of the plastic change. Even temporarily exceeding this temperature limit may change the stresses that the package exerts on the die, permanently shifting the parametric performance of the AD8045. Exceeding a junction temperature of 175°C for an extended period of time can result in changes in silicon devices, potentially causing degradation or loss of functionality.

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation and loss of functionality.

The power dissipated in the package (P

) is the sum of the qui-

D

escent power dissipation and the power dissipated in the die due to the AD8045 drive at the output. The quiescent power is the voltage between the supply pins (V current (I

).

S

= Quiescent Power + (Total D riv e Pow e r – Load Power)

P

D

⎛

V

()

D

⎜

IVP

SS

⎜ ⎝

OUTS

×+×=

R

2

L

RMS output voltages should be considered. If

−

V

, as in single-supply operation, the total drive power is VS ×

S

. If the rms signal levels are indeterminate, consider the

I

OUT

worst case, when

D

V

= VS/4 for RL to midsupply.

OUT

2

)

4

/V

()

+×=

IVP

SS

S

R

L

In single-supply operation with R

= VS/2.

is V

OUT

Airflow increases heat dissipation, effectively reducing θ

) times the quiescent

S

⎞ ⎟

⎟ ⎠

L

2

V

OUT

–

R

L

R

is referenced to

L

referenced to −VS, worst case

.

JA

Also, more metal directly in contact with the package leads and exposed paddle from metal traces, through holes, ground, and power planes reduce θ

.

JA

Figure 4 shows the maximum safe power dissipation in the package versus the ambient temperature for the exposed paddle SOIC (80°C/W) and LFCSP (93°C/W) package on a JEDEC standard 4-layer board. θ

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

MAXIMUM POWER DISSIPATION (Watts)

0.0

Figure 4. Maximum Power Dissipation vs. Temperature for a 4-Layer Board

values are approximations.

JA

LFCSP

AMBIENT TEMPERATURE (°C)

SOIC

120–40 –20 0 20 40 60 80 100

04814-0-080

Rev. A | Page 5 of 24

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PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

NC

+V

OUTPUT

NC

8

7

S

6

BOTTOM VIEW

5

(Not to Scale)

NC = NO CONNECT

AD8045

FEEDBACK

1

–IN

2

+IN

3

4

–V

S

04814-0-003

Figure 5. SOIC Pin Configuration

Note: The exposed paddle must be connected to −VS or it must be electrically isolated (floating).

Table 5. 8-Lead SOIC Pin Function Descriptions

Pin No. Mnemonic Description

1 FEEDBACK Feedback Pin 2 −IN Inverting Input 3 +IN Noninverting Input 4 −V

S

Negative Supply 5 NC NC 6 OUTPUT Output 7 +V

S

Positive Supply 8 NC NC 9 Exposed Paddle

Must Be Connected to −V

or

S

Electrically Isolated

+V

OUTPUT

NC

–V

8

S

BOTTOM

7

VIEW

6

(Not to Scale)

54

1

NC

2

FEEDBACK

3

–IN +IN

NC = NO CONNECT

04814-0-004

Figure 6 . 8-Lead LFCSP Pin Configuration

Table 6. 8-Lead LFCSP Pin Function Descriptions

Pin No. Mnemonic Description

1 NC No Connect 2 FEEDBACK Feedback Pin 3 −IN Inverting Input 4 +IN Noninverting Input 5 −V

S

Negative Supply 6 NC No Connect 7 OUTPUT Output 8 +V

S

9 Exposed Paddle

Positive Supply

Must Be Connected to −V

or

S

Electrically Isolated

Rev. A | Page 6 of 24

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TYPICAL PERFORMANCE CHARACTERISTICS

1

V

=±5V

S

= 1kΩ

R

L

0

–1

–2

–3

–4

–5

–6

NORMALIZED CLOSED-LOOP GAIN (dB)

–7

G = +10

FREQUENCY (MHz)

G = +2

G = –1

Figure 7. Small Signal Frequency Response for Various Gains

10001 10 100

04814-0-049

12

G = +2

11

=±5V

V

S

= 1kΩ

R

L

10

= 499Ω

R

F

9 8 7 6 5 4 3

CLOSED-LOOP GAIN (dB)

2 1 0

FREQUENCY (MHz)

18pF

10pF

5pF

0pF

100010 100

Figure 10. Small Signal Frequency Response for Various Capacitive Loads

04814-0-048

4

G = +1

=±5V

V

3

S

= 100Ω

R

S

2

1

0

–1

–2

–3

CLOSED-LOOP GAIN (dB)

–4

–5

–6

FREQUENCY (MHz)

R

L

R

= 1kΩ

L

= 500Ω

R

L

= 100Ω

100010 100

Figure 8. Small Signal Frequency Response for Various Loads

5

G = +1 R

= 1kΩ

L

4

= 100Ω

R

S

3

2

1

0

–1

–2

CLOSED-LOOP GAIN (dB)

–3

–4

–5

V

= ±2.5V

S

VS = ±5V

FREQUENCY (MHz)

100010 100

Figure 9. Small Signal Frequency Response for Various Supplies

04814-0-050

04814-0-051

4

G = +1

=±5V

V

S

3

= 1kΩ

R

L

2

1

0

–1

–2

–3

CLOSED-LOOP GAIN (dB)

–4

–5

–6

FREQUENCY (MHz)

+125°C

+25°C

–40°C

100010 100

Figure 11. Small Signal Frequency Response for Various Temperatures

6.3 G = +2

=±5V

V

S

= 499Ω

R

F

6.2

= 150Ω

R

L

6.1

6.0

5.9

CLOSED-LOOP GAIN (dB)

5.8

5.7

V

= 2V p-p

OUT

V

= 200mV p-p

OUT

1 10 100

FREQUENCY (MHz)

Figure 12. 0.1 dB Flatness vs. Frequency for Various Output Voltages

04814-0-052

04814-0-039

Rev. A | Page 7 of 24

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2 1

0 –1 –2 –3 –4 –5 –6 –7

CLOSED-LOOP GAIN (dB)

–8 –9

–10

V

= ±2.5V

S

FREQUENCY (MHz)

Figure 13. Large Signal Frequency Response for Various Supplies

V

OUT

G = +1

= 1kΩ

R

L

= 100Ω

R

S

= 2V p-p

V

=±5V

S

70

60

50

40

30

20

OPEN-LOOP GAIN (dB)

10

0

100010 100

04814-0-043

–10

FREQUENCY (MHz)

VS=±5V

= 1kΩ

R

L

10000.01 0.1 1 10 100

0

–45

–90

–135

–180

–225

–270

–315

–360

OPEN-LOOP PHASE (Degrees)

04814-0-064

Figure 16. Open-Loop Gain and Phase vs. Frequency

2

V

R

OUT

V

S

= 100Ω

S

= 2V p-p

R

L

1

0 –1 –2 –3 –4 –5 –6 –7

CLOSED-LOOP GAIN (dB)

–8 –9

–10

FREQUENCY (MHz)

R

L

= 100Ω

Figure 14. Large Signal Frequency Response for Various Loads

2

1

0

–1

–2

–3

–4

–5

–6

–7

NORMALIZED CLOSED-LOOP GAIN (dB)

–8

VS = ±5V

= 499Ω

R

F

= 1kΩ

R

L

= 2V p-p

V

OUT

G = +10

FREQUENCY (MHz)

G = +2

G = –1

Figure 15. Large Signal Frequency Response for Various Gains

G = +1 = ±5V

= 1kΩ

–20

G = +1

=±5V

V

S

–30

= 2V p-p

V

OUT

= 1kΩ

R

L

–40

= 100Ω

R

S

–50

–60

–70

–80

–90

–100

HARMONIC DISTORTION (dBc)

–110

100010 100

04814-0-042

–120

HD3 SOIC AND LFCSP

FREQUENCY (MHz)

HD2 LFCSP

HD2 SOIC

1000.1 1 10

04814-0-030

Figure 17. Harmonic Distortion vs. Frequency for Various Packages

–30

G = +1

=±5V

V

S

–40

= 4V p-p

V

OUT

= 1kΩ

R

L

–50

–60

–70

–80

–90

–100

HARMONIC DISTORTION (dBc)

–110

10001 10 100

04814-0-041

–120

0.1 1 10 100

HD3 LFCSP AND SOIC

FREQUENCY (MHz)

HD2 SOIC

HD2 LFCSP

04814-0-028

Figure 18. Harmonic Distortion vs. Frequency for Various Packages

Rev. A | Page 8 of 24

ANALOG DEVICES AD8045 Service Manual

FEATURES

GENERAL DESCRIPTION

APPLICATIONS

CONNECTION DIAGRAMS

TABLE OF CONTENTS

SPECIFICATIONS WITH ±5 V SUPPLY

SPECIFICATIONS WITH +5 V SUPPLY

ABSOLUTE MAXIMUM RATINGS

THERMAL RESISTANCE

Maximum Power Dissipation

ESD CAUTION

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

TYPICAL PERFORMANCE CHARACTERISTICS