Analog Devices AD802, AD800 Datasheet

VCO

DATA

INPUT

AD800/AD802

RETIMED DATA OUTPUT

FRAC OUTPUT

LOOP

FILTER

DET

∑

COMPENSATING

ZERO

RECOVERED CLOCK OUTPUT

RETIMING

DEVICE

Clock Recovery and Data Retiming

FEATURES Standard Products

44.736 Mbps—DS-3

51.84 Mbps—STS-1

155.52 Mbps—STS-3 or STM-1 Accepts NRZ Data, No Preamble Required Recovered Clock and Retimed Data Outputs Phase-Locked Loop Type Clock Recovery—No Crystal

Required Random Jitter: 208 Peak-to-Peak Pattern Jitter: Virtually Eliminated 10KH ECL Compatible Single Supply Operation: –5.2 V or +5 V Wide Operating Temperature Range: –408C to +858C

PRODUCT DESCRIPTION

The AD800 and AD802 employ a second order phase-locked loop architecture to perform clock recovery and data retiming on Non-Return to Zero, NRZ, data. This architecture is capable of supporting data rates between 20 Mbps and 160 Mbps. The products described here have been defined to work with standard telecommunications bit rates. 45 Mbps DS-3 and 52 Mbps STS-1 are supported by the AD800-45 and AD800-52 respectively. 155 Mbps STS-3 or STM-1 are supported by the AD802-155.

Unlike other PLL-based clock recovery circuits, these devices do not require a preamble or an external VCXO to lock onto input data. The circuit acquires frequency and phase lock using two control loops. The frequency acquisition control loop initially acquires the clock frequency of the input data. The phase-lock loop then acquires the phase of the input data, and ensures that the phase of the output signals track changes in the phase of the input data. The loop damping of the circuit is dependent on the value of a user selected capacitor; this defines jitter peaking performance and impacts acquisition time. The devices exhibit 0.08 dB jitter peaking, and acquire lock on random or scrambled data within 4 × 10 using a damping factor of 5.

bit periods when

Phase-Locked Loop

AD800/AD802*

FUNCTIONAL BLOCK DIAGRAM

During the process of acquisition the frequency detector provides a Frequency Acquisition (FRAC) signal which indicates that the device has not yet locked onto the input data. This signal is a series of pulses which occur at the points of cycle slip between the input data and the synthesized clock signal. Once the circuit has acquired frequency lock no pulses occur at the FRAC output.

The inclusion of a precisely trimmed VCO in the device eliminates the need for external components for setting center frequency, and the need for trimming of those components. The VCO provides a clock output within ± 20% of the device center frequency in the absence of input data.

The AD800 and AD802 exhibit virtually no pattern jitter, due to the performance of the patented phase detector. Total loop jitter is 20° peak-to-peak. Jitter bandwidth is dictated by mask programmable fractional loop bandwidth. The AD800, used for data rates < 90 Mbps, has been designed with a nominal loop bandwidth of 0.1% of the center frequency. The AD802, used for data rates in excess of 90 Mbps, has a loop bandwidth of

0.08% of center frequency. All of the devices operate with a single +5 V or –5.2 V supply.

*Protected by U.S. Patent No. 5,027,085.

REV. B

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 617/329-4700 Fax: 617/326-8703

AD800/AD802–SPECIFICATIONS

(VEE = V

MIN

to V

, VCC = GND, TA = T

MAX

Factor = 5, unless otherwise noted)

MIN

to T

MAX

, Loop Damping

Parameter

Condition Min Typ Max Min Typ Max Min Typ Max Units

AD800-45BQ AD800-52BR AD802-155KR/BR

NOMINAL CENTER FREQUENCY 44.736 51.84 155.52 MHz OPERATING TEMPERATURE K Grade 0 70 °C

RANGE (T

MIN

to T

) B Grade –40 85 –40 85 –40 85 °C

MAX

TRACKING RANGE 43 45.5 49 53 155 156 Mbps CAPTURE RANGE 43 45.5 49 53 155 156 Mbps STATIC PHASE ERROR ρ = 1, TA = +25°C,

VEE = –5.2 V 2 10 2 10 14 30 Degrees ρ = 1 3 11.5 3 11.5 18 37 Degrees

RECOVERED CLOCK SKEW t

(Figure 1) 0.2 0.6 1 0.2 0.6 1 0.2 0.8 1 ns

RCS

SETUP TIME tSU (Figure 1) 2.06 2.37 ns TRANSITIONLESS DATA RUN 240 240 240 Bit Periods OUTPUT JITTER ρ = 1 2 2 3.5 Degrees rms

27–1 PRN Sequence 2.5 4.7 2.5 4.7 5.4 9.7 Degrees rms 223–1 PRN Sequence 2.5 4.7 2.5 4.7 5.4 9.7 Degrees rms

JITTER TOLERANCE f = 10 Hz 2,500 2,500 3,000 Unit Intervals

f = 2.3 kHz 6.5 Unit Intervals f = 30 kHz 0.47 Unit Intervals f = 1 MHz 0.47 Unit Intervals f = 30 Hz 830 Unit Intervals f = 300 Hz 83 Unit Intervals f = 2 kHz 7.4 Unit Intervals f = 20 kHz 0.47 Unit Intervals f = 6.5 kHz 2.0 7.6 Unit Intervals f = 65 kHz 0.26 0.9 Unit Intervals

JITTER TRANSFER

Damping Factor

Capacitor, C

ζ = 1, Nominal 8.2 6.8 2.2 nF

ζ = 5, Nominal 0.22 0.15 0.047 µF ζ = 10, Nominal 0.82 0.68 0.22 µF

Peaking

ζ = 1, Nominal TA = +25°C, VEE = –5.2 V 2 2 2 dB ζ = 5, Nominal TA = +25°C, VEE = –5.2 V 0.08 0.08 0.08 dB ζ = 10, Nominal TA = +25°C, VEE = –5.2 V 0.02 0.02 0.02 dB

Bandwidth 45 52 130 kHz

ACQUISITION TIME

ρ = 1/2 ζ = 1 1 × 10 TA = +25°C ζ = 5 3 × 1058 × 10 VEE = –5.2 V ζ = 10 8 × 10

1 × 10 3 × 1058 × 10

8 × 10

1.5 × 10 4 × 1058 × 105Bit Periods

1.4 × 10

Bit Periods Bit Periods

POWER SUPPLY

Voltage (V Current TA = +25°C, VEE = –5.2 V 125 170 125 170 140 180 mA

MIN

to V

MAX

= +25°C –4.5 –5.2 –5.5 –4.5 –5.2 –5.5 –4.5 –5.2 –5.5 Volts

180 180 205 mA

INPUT VOLTAGE LEVELS TA = +25°C

Input Logic High, V Input Logic Low, V

–1.084 –0.72 –1.084 –0.72 –1.084 –0.72 Volts –1.95 –1.594 –1.95 –1.594 –1.95 –1.594 Volts

OUTPUT VOLTAGE LEVELS TA = +25°C

Output Logic High, V Output Logic Low, V

–1.084 –0.72 –1.084 –0.72 –1.084 –0.72 Volts –1.95 –1.60 –1.95 –1.60 –1.95 –1.60 Volts

INPUT CURRENT LEVELS TA = +25°C

Input Logic High, I Input Logic Low, I

125 125 125 µA 80 80 80 µA

OUTPUT SLEW TIMES TA = +25°C

Rise Time (tR) 20%–80% 0.75 1.5 0.75 1.5 0.75 1.5 ns Fall Time (tF) 80%–20% 0.75 1.5 0.75 1.5 0.75 1.5 ns

SYMMETRY ρ = 1/2, TA = +25°C

Recovered Clock Output VEE = –5.2 V 45 55 45 55 45 55 %

NOTES

Refer to Glossary for parameter definition.

Specifications subject to change without notice.

–2–

REV. B

AD800/AD802

ABSOLUTE MAXIMUM RATINGS*

Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –6 V

Input Voltage (Pin 16 or Pin 17 to V

) . . . . VEE to +300 mV

Maximum Junction Temperature

SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+150°C

Ceramic DIP Package . . . . . . . . . . . . . . . . . . . . . . +175°C

Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C

Lead Temperature Range (Soldering 60 sec) . . . . . . . +300°C

ESD Rating

AD800 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1500 V

AD802 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000 V

*Stresses above those listed under “Absolute Maximum Ratings” may cause

permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to an absolute maximum rating condition for an extended period may adversely affect device reliability.

DATAOUT 50%

(PIN 2)

CLKOUT 50%

(PIN 5)

SETUP TIME

RECOVERED CLOCK

SKEW,

RCS

Figure 1. Recovered Clock Skew and Setup (See Previous Page)

PIN DESCRIPTIONS

Number Mnemonic Description

DATAOUT Differential Retimed Data Output 2 DATAOUT Differential Retimed Data Output 3V 4

CC2

CLKOUT Differential Recovered Clock Output

Digital Ground

5 CLKOUT Differential Recovered Clock Output 6V

7VEEDigital V 8V 9AV

CC1

Digital V

EE EE

Digital Ground Analog V

10 ASUBST Analog Substrate 11 CF 12 CF 13 AV 14 V 15 V

2 1

CC CC1 EE

Loop Damping Capacitor Input Loop Damping Capacitor Input Analog Ground Digital Ground Digital V

16 DATAIN Differential Data Input 17

DATAIN Differential Data Input 18 SUBST Digital Substrate 19

FRAC Differential Frequency Acquisition

Indicator Output

20 FRAC Differential Frequency Acquisition

Indicator Output

THERMAL CHARACTERISTICS

SOIC Package 22°C/W 75°C/W Cerdip Package 25°C/W 90°C/W

Use of a heatsink may be required depending on operating environment.

GLOSSARY Maximum and Minimum Specifications

Maximum and minimum specifications result from statistical analyses of measurements on multiple devices and multiple test systems. Typical specifications indicate mean measurements. Maximum and minimum specifications are calculated by adding or subtracting an appropriate guardband from the typical specification. Device-to-device performance variation and test system-to-test system variation contribute to each guardband.

Nominal Center Frequency

This is the frequency that the VCO will operate at with no input signal present and the loop damping capacitor, C

, shorted.

Tracking Range

This is the range of input data rates over which the PLL will remain in lock.

Capture Range

This is the range of input data rates over which the PLL can acquire lock.

Static Phase Error

This is the steady-state phase difference, in degrees, between the recovered clock sampling edge and the optimum sampling instant, which is assumed to be halfway between the rising and falling edges of a data bit. Gate delays between the signals that define static phase error, and IC input and output signals prohibit direct measurement of static phase error.

Data Transition Density, r

This is a measure of the number of data transitions, from “0” to “1” and from “1” to “0,” over many clock periods. ρ is the ratio (0 ≤ ρ ≤ 1) of data transitions to clock periods.

Jitter

This is the dynamic displacement of digital signal edges from their long term average positions, measured in degrees rms, or Unit Intervals (UI). Jitter on the input data can cause dynamic phase errors on the recovered clock sampling edge. Jitter on the recovered clock causes jitter on the retimed data.

Output Jitter

This is the jitter on the retimed data, in degrees rms, due to a specific pattern or some psuedo-random input data sequence (PRN Sequence).

Jitter Tolerance

Jitter tolerance is a measure of the PLL’s ability to track a jittery input data signal. Jitter on the input data is best thought of as phase modulation, and is usually specified in unit intervals.

ORDERING GUIDE

Fractional Loop

Device Center Frequency Bandwidth Description Operating Temperature Package Option

AD800-45BQ 44.736 MHz 0.1% 20-Pin Cerdip –40°C to +85°C Q-20 AD800-52BR 51.84 MHz 0.1% 20-Pin Plastic SOIC –40°C to +85°C R-20 AD802-155BR 155.52 MHz 0.08% 20-Pin Plastic SOIC –40°C to +85°C R-20 AD802-155KR 155.52 MHz 0.08% 20-Pin Plastic SOIC 0°C to +70°C R-20

REV. B

–3–

AD800/AD802

∑

POWER COMBINER

∑

0.47µF

50Ω

0.47µF

POWER COMBINER

75Ω

1.0µF

180Ω

POWER

SPLITTER

FILTER

NOISE

SOURCE

100MHz – AD802-155 33MHz – AD800-52

GND

–5.2V

D.U.T. AD800/AD802

DATA IN

DIFFERENTIAL SIGNAL SOURCE

The PLL must provide a clock signal which tracks this phase modulation in order to accurately retime jittered data. In order for the VCO output to have a phase modulation which tracks the input jitter, some modulation signal must be generated at the output of the phase detector (see Figure 21). The modulation output from the phase detector can only be produced by a phase error between the data input and the clock input. Hence, the PLL can never perfectly track jittered data. However, the magnitude of the phase error depends on the gain around the loop. At low frequencies the integrator provides very high gain, and thus very large jitter can be tracked with small phase errors between input data and recovered clock. At frequencies closer to the loop bandwidth, the gain of the integrator is much smaller, and thus less input jitter can be tolerated. The PLL data output will have a bit error rate less than 1 3 10

–10

when in lock and retiming input data that has the

specified jitter applied to it.

Jitter Transfer

The PLL exhibits a low-pass filter response to jitter applied to its input data.

Bandwidth

This describes the frequency at which the PLL attenuates sinusoidal input jitter by 3 dB.

Peaking

This describes the maximum jitter gain of the PLL in dB.

Damping Factor,

describes how the PLL will track an input signal with a phase step. A greater value of PLL response to a phase step.

corresponds to less overshoot in the

is a standard constant in second

order feedback systems.

Acquisition Time

This is the transient time, measured in bit periods, required for the PLL to lock on input data from its free-running state.

Symmetry

Symmetry is calculated as (100 3 on time)/period, where on time equals the time that the clock signal is greater than the midpoint between its “0” level and its “1” level.

Bit Error Rate vs. Signal-to-Noise Ratio

The AD800 and AD802 were designed to operate with standard ECL signal levels at the data input. Although not recommended, smaller input signals are tolerable. Figure 8, 14, and 20 show the bit error rate performance versus input signal-tonoise ratio for input signal amplitudes of full 900 mV ECL, and decreased amplitudes of 80 mV and 20 mV. Wideband amplitude noise is summed with the data signals as shown in Figure

2. The full ECL and 80 mV signals give virtually indistinguishable results. The 20 mV signals also provide adequate performance when in lock, but signal acquisition may be impaired.

Figure 2. Bit Error Rate vs. Signal-to-Noise Ratio Test: Block Diagram

USING THE AD800 AND THE AD802 SERIES Ground Planes

Use of one ground plane for connections to both analog and digital grounds is recommended. Output signal sensitivity to power supply noise (PECL configuration, Figure 22) is less using one ground plane than when using separate analog and digital ground planes.

Power Supply Connections

Use of a 10 µF tantalum capacitor between VEE and ground is recommended.

Use of 0.1 µF ceramic capacitors between IC power supply or substrate pins and ground is recommended. Power supply decoupling should take place as close to the IC as possible. Refer to schematics, Figure 22 and Figure 26, for advised connections.

Sensitivity of IC output signals (PECL configuration, Figure 22) to high frequency power supply noise (at 2 3 the nominal data rate) can be reduced through the connection of signals AV The type of bypass network to consider depends on the noise tolerance required. The more complex bypass network schemes tolerate greater power supply noise levels. Refer to Figures 23 and 24 for bypassing schemes and power supply sensitivity curves.

and V

, and the addition of a bypass network.

CC1

Transmission Lines

Use of 50 Ω transmission lines are recommended for DATAIN, CLKOUT, DATAOUT, and FRAC signals.

Terminations

Termination resistors should be used for DATAIN, CLKOUT, DATAOUT, and FRAC signals. Metal, thick film, 1% tolerance resistors are recommended. Termination resistors for the DATAIN signals should be placed as close as possible to the DATAIN pins.

Connections from V

to lead resistors for DATAIN, DATA-

OUT, FRAC, and CLKOUT signals should be individual, not daisy chained. This will avoid crosstalk on these signals.

Loop Damping Capacitor, C

A ceramic capacitor may be used for the loop damping capacitor.

Input Buffer

Use of an input buffer, such as a 10H116 Line Receiver IC, is suggested for an application where the DATAIN signals do not come directly from an ECL gate, or where noise immunity on the DATAIN signals is an issue.

–4–

REV. B

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