ANALOG DEVICES AD7933 Service Manual

V

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4-Channel, 1.5 MSPS, 12-Bit and 10-Bit

Preliminary Technical Data

FEATURES

Fast throughput rate: 1.5 MSPS
Specified for V
Low power

8 mW max at 1.5 MSPS with 3 V supplies

16 mW max at 1.5 MSPS with 5 V supplies
4 analog input channels with a sequencer
Software configurable analog inputs

4-channel single-ended inputs

2-channel fully differential inputs

2-channel pseudo-differential inputs
Accurate on-chip 2.5 V reference
Wide input bandwidth

70 dB SNR at 50 kHz input frequency
No pipeline delays
High speed parallel interface—word/byte modes
Full shutdown mode: 1 µA max
28 lead TSSOP package

of 2.7 V to 5.25 V

DD

Parallel ADCs with a Sequencer

AD7933/AD7934

FUNCTIONAL BLOCK DIAGRAM

V

AGND

DD

V

REFIN/

REFOUT

VIN0

VIN3

2.5V

VREF

I/P

T/H

MUX

SEQUENCER

PARALLEL INTERFACE/CONTROL REGISTER

DB0 DB11

Figure 1.

AD7933/AD7934

12-/10-BIT
SAR ADC

AND

CONTROL

CS DGNDRD WR W/B

CLKIN

CONVST

BUSY

V

DRIVE

03713-0-001

GENERAL DESCRIPTION

The AD7933/AD7934 are 12-bit and 10-bit, high speed, low
power, successive approximation (SAR) ADCs. The parts
operate from a single 2.7 V to 5.25 V power supply and feature
throughput rates to 1.5 MSPS. The parts contain a low noise,
wide bandwidth, differential track-and-hold amplifier that can
handle input frequencies up to 20 MHz.

The AD7933/AD7934 feature 4 analog input channels with a
channel sequencer to allow a consecutive sequence of channels
to be converted on. These parts can accept either single-ended,
fully differential, or pseudo-differential analog inputs.

The conversion process and data acquisition are controlled
using standard control inputs, which allows for easy interfacing
to microprocessors and DSPs. The input signal is sampled on
the falling edge of

CONVST

at this point.

The AD7933/AD7934 has an accurate on-chip 2.5 V reference
that can be used as the reference source for the analog-to-digital
conversion. Alternatively, this pin can be overdriven to provide
an external reference.

and the conversion is also initiated

These parts use advanced design techniques to achieve very low
power dissipation at high throughput rates. They also feature
flexible power management options. An on-chip control register
allows the user to set up different operating conditions,
including analog input range and configuration, output coding,
power management, and channel sequencing.

PRODUCT HIGHLIGHTS

1. High throughput with low power consumption.

2. Four analog inputs with a channel sequencer.

3. Accurate on-chip 2.5 V reference.

4. Software configurable analog inputs. Single-ended, pseudo-

differential, or fully differential analog inputs that are
software selectable.

5. Single-supply operation with V

function. The V

DRIVE

function allows the parallel interface to connect directly to
3 V, or 5 V processor systems independent of V

DD

6. No pipeline delay.

7. Accurate control of the sampling instant via a

CONVST

input and once off conversion control.

DRIVE

.

PrG

Rev.

Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
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registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] © 2004 Analog Devices, Inc. All rights reserved.

AD7933/AD7934 Preliminary Technical Data

TABLE OF CONTENTS

AD7933—Specifications.................................................................. 3

Analog Input Structure.............................................................. 19

AD7934—Specifications.................................................................. 5

Timing Specifications....................................................................... 7

Absolute Maximum Ratings............................................................ 8

ESD Caution.................................................................................. 8

Pin Configuration and Function Descriptions............................. 9

Terminology ....................................................................................11

Typical Performance Characteristics ...........................................13

Control Register.......................................................................... 16

Sequencer Operation ................................................................. 17

Circuit Information........................................................................ 18

Converter Operation.................................................................. 18

ADC Transfer Function............................................................. 18

Typical Connection Diagram ................................................... 19

REVISION HISTORY

Analog Inputs.............................................................................. 20

Analog Input Selection.............................................................. 22

Reference Section ....................................................................... 22

Parallel Interface ......................................................................... 24

Power Modes of Operation ....................................................... 27

Power vs. Throughput Rate....................................................... 28

Microprocessor Interfacing....................................................... 28

Application Hints ........................................................................... 30

Grounding and Layout .............................................................. 30

Evaluating the AD7933/AD7934 Performance...................... 30

Outline Dimensions....................................................................... 31

Ordering Guide .......................................................................... 31

8/04—Revision PrG: Preliminary Version

Rev. PrG | Page 2 of 32

Preliminary Technical Data AD7933/AD7934

AD7933—SPECIFICATIONS

VDD = V
T

MAX

Table 1.

Parameter B Version1 Unit Test Conditions/Comments

DYNAMIC PERFORMANCE FIN = 50 kHz sine wave

Signal-to-Noise + Distortion (SINAD)2 60 dB min

Signal-to-Noise Ratio (SNR)2 60 dB min

Total Harmonic Distortion (THD)2 −73 dB max

Peak Harmonic or Spurious Noise (SFDR)2 −73 dB max

Intermodulation Distortion (IMD)2 fa = 40.1 kHz, fb = 51.5 kHz

Aperture Delay2 5 ns typ

Aperture Jitter2 50 ps typ

Full Power Bandwidth

2.5 MHz typ @ 0.1 dB
DC ACCURACY

Resolution 10 Bits

Integral Nonlinearity2 ±0.5 LSB max

Differential Nonlinearity2 ±0.5 LSB max Guaranteed no missed codes to 10 bits

Total Unadjusted Error TBD LSB max

Single-Ended and Pseudo Differential Input Straight binary output coding

Fully Differential Input Twos complement output coding offset

ANALOG INPUT

Single-Ended Input Range 0 to V

Pseudo-Differential Input Range: V

Fully Differential Input Range: V

DC Leakage Current5 ±1 µA max

Input Capacitance 45 pF typ When in track

10 pF typ When in hold
REFERENCE INPUT/OUTPUT

V

REF

DC Leakage Current5 ±1 µA max

V

REF

V

REFOUT

V

REFOUT

V

REF

130 µV typ 0.1 Hz to 1 MHz bandwidth

=2.7 V to 5.25 V, Internal/External V

DRIVE

= 2.5 V, unless otherwise noted, F

REF

= 24 MHz, F

CLKIN

= 1.5 MSPS; TA = T

SAMPLE

, unless otherwise noted.

Second-Order Terms −75 dB typ
Third-Order Terms −75 dB typ
Channel-to-Channel Isolation −75 dB typ

2, 3

20 MHz typ @ 3 dB

Offset Error2 ±4.5 LSB max
Offset Error Match2 ±0.5 LSB max
Gain Error2 ±2 LSB max
Gain Error Match2 ±0.6 LSB max

Positive Gain Error2 ±2 LSB max
Positive Gain Error Match2 ±0.6 LSB max
Zero-Code Error2 ±3 LSB max
Zero-Code Error Match2 ±1 LSB max
Negative Gain Error2 ±2 LSB max
Negative Gain Error Match2 ±0.6 LSB max

or 0 to 2 × V

REF

0 to V

IN+

V

−0.1 to +0.4 V

IN−

V

IN+

IN+

and V

and V

VCM ± V

IN−

VCM ± V

IN−

or 2 × V

REF

/2 V VCM = common-mode voltage4 = V

REF

V VCM = V

REF

V Depending on RANGE bit setting

REF

V Depending on RANGE bit setting

REF

, V

or V

REF

IN+

must remain within GND/VDD

IN−

Input Voltage6 2.5 V ±1% specified performance

Input Impedance 10 kΩ

Output Voltage 2.5 V ±0.1% @ 25°C

Temperature Coefficient 15 ppm/°C typ

Noise 10 µV typ 0.1 Hz to 10 Hz bandwidth

REF

/2

MIN

to

Rev. PrG | Page 3 of 32

AD7933/AD7934 Preliminary Technical Data

Parameter B Version1 Unit Test Conditions/Comments

V

Output Impedance 10 Ω typ

REF

V

Input Capacitance 15 pF typ When in track

REF

25 pF typ When in hold

LOGIC INPUTS

Input High Voltage, V
Input Low Voltage, V
Input Current, IIN ±1 µA max Typically 10 nA, VIN = 0 V or V
Input Capacitance, C

LOGIC OUTPUTS

Output High Voltage, VOH 2.4 V min I
Output Low Voltage, VOL 0.4 V max I
Floating-State Leakage Current ±10 µA max
Floating-State Output Capacitance5 10 pF max
Output Coding CODING bit = 0

CONVERSION RATE

Conversion Time t2 + 13
Track-and-Hold Acquisition Time 135 ns max Full scale step input
Throughput Rate 1.5 MSPS max

POWER REQUIREMENTS

VDD 2.7/5.25 V min/max
V

2.7 /5.25 V min/max

DRIVE

7

I

Digital I/Ps = 0 V or V

DD

Normal Mode(Static) 0.5 mA typ VDD = 2.7 V to 5.25 V, SCLK on or off
Normal Mode (Operational) 3.2 mA max VDD = 4.75 V to 5.25 V

2.6 mA max VDD = 2.7 V to 3.6 V
Auto StandBy Mode 1.55 mA typ F
90 µA max (Static)
Auto Shutdown Mode 1 mA typ F
1 µA max (Static)
Full Shutdown Mode 1 µA max SCLK on or off

Power Dissipation

Normal Mode (Operational) 16 mW max VDD = 5 V
8 mW max VDD = 3 V
Auto Standby Mode (Static) 450 µW max VDD = 5 V
270 µW max VDD = 3 V
Auto Shutdown Mode (Static) 5 µW max VDD = 5 V
3 µW max VDD = 3 V
Full Shutdown Mode 5 µW max VDD = 5 V

3 µW max VDD = 3 V

1

Temperature range is as follows: B Versions: −40°C to +85°C.

2

See Terminology section.

3

Analog inputs with slew rates exceeding 27 V/µs (full-scale input sine wave >3.5 MHz) within the acquisition time may cause an incorrect conversion result to be

returned by the converter.

4

For full common-mode range see

5

Sample tested during initial release to ensure compliance.

6

This device is operational with an external reference in the range 0.1 V to 3.5 V differential mode and 0.1 V to VDD in pseudo-differential and single-ended modes.

7

Measured with a midscale dc input.

2.4 V min

INH

0.8 V max

INL

5

10 pF max

IN

= 200 µA;

SOURCE

= 200 µA

SINK

Straight (Natural) Binary

Twos Complement CODING bit = 1

+ t20 ns

tclk

= 250 kSPS

SAMPLE

= 250 kSPS

SAMPLE

DRIVE

DRIVE

Rev. PrG | Page 4 of 32

Preliminary Technical Data AD7933/AD7934

AD7934—SPECIFICATIONS

VDD = V
T

MAX

Table 2.

Parameter B Version1 Unit Test Conditions/Comments

DYNAMIC PERFORMANCE FIN = 50 kHz sine wave

Signal-to-Noise + Distortion (SINAD)2 70 dB min
Signal-to-Noise Ratio (SNR)2 70 dB min
Total Harmonic Distortion (THD)2 −75 dB max −80 dB typ
Peak Harmonic or Spurious Noise (SFDR)2 −75 dB max −82 dB typ
Intermodulation Distortion (IMD)2 fa = 40.1 kHz, fb = 51.5 kHz

Aperture Delay2 5 ns typ
Aperture Jitter2 50 ps typ
Full Power Bandwidth

2.5 MHz typ @ 0.1 dB
DC ACCURACY

Resolution 12 Bits
Integral Nonlinearity2 ±1 LSB max
Differential Nonlinearity2 ±0.95 LSB max Guaranteed no missed codes to 12 bits
Total Unadjusted Error TBD LSB max
Single-Ended and Pseudo-Differential Input Straight binary output coding

Fully Differential Input Twos complement output coding

ANALOG INPUT

Single-Ended Input Range 0 to V
Pseudo-Differential Input Range: V

Fully Differential Input Range: V

DC Leakage Current5 ±1 µA max
Input Capacitance 45 pF typ When in track
10 pF typ When in hold

REFERENCE INPUT/OUTPUT

V

REF

DC Leakage Current ±1 µA max
V

REF

V

REFOUT

V

REFOUT

V

REF

130 µV typ 0.1 Hz to 1 MHz bandwidth

= 2.7 V to 5.25 V, Internal/External V

DRIVE

= 2.5 V, unless otherwise noted, F

REF

= 24 MHz, F

CLKIN

= 1.5 MSPS; TA = T

SAMPLE

, unless otherwise noted.

Second-Order Terms −85 dB typ
Third-Order Terms −85 dB typ
Channel-to-Channel Isolation −85 dB typ

2, 3

20 MHz typ @ 3 dB

Offset Error2 ±4.5 LSB max
Offset Error Match2 ±0.5 LSB max
Gain Error2 ±2 LSB max
Gain Error Match2 ±0.6 LSB max

Positive Gain Error2 ±2 LSB max
Positive Gain Error Match2 ±0.6 LSB max
Zero-Code Error2 ±3 LSB max
Zero-Code Error Match2 ±1 LSB max
Negative Gain Error2 ±2 LSB max
Negative Gain Error Match2 ±0.6 LSB max

or 0 to 2 × V

REF

0 to V

IN+

V

−0.1 to +0.4 V

IN−

V

IN+

IN+

and V

and V

VCM ± V

IN−

VCM ± V

IN−

or 2 × V

REF

/2 V VCM = common-mode voltage4 = V

REF

V VCM = V

REF

V Depending on RANGE bit setting

REF

V Depending on RANGE bit setting

REF

, V

or V

REF

IN+

must remain within GND/VDD

IN−

Input Voltage6 2.5 V ±1% specified performance

Input Impedance 10 kΩ typ

Output Voltage 2.5 V ±0.1% @ 25°C
Temperature Coefficient 15 ppm/°C typ

Noise 10 µV typ 0.1 Hz to 10 Hz bandwidth

REF

/2

MIN

to

Rev. PrG | Page 5 of 32

AD7933/AD7934 Preliminary Technical Data

Parameter B Version1 Unit Test Conditions/Comments

V

Output Impedance 10 Ω typ

REF

V

Input Capacitance 15 pF typ When in track-and-hold

REF

25 pF typ When in track-and-hold

LOGIC INPUTS

Input High Voltage, V
Input Low Voltage, V
Input Current, IIN ±1 µA max Typically 10 nA, VIN = 0 V or V
Input Capacitance, C

LOGIC OUTPUTS

Output High Voltage, VOH 2.4 V min I
Output Low Voltage, VOL 0.4 V max I
Floating-State Leakage Current ±10 µA max
Floating-State Output Capacitance5 10 pF max
Output Coding CODING bit = 0

CONVERSION RATE

Conversion Time t2 + 13
Track-and-Hold Acquisition Time 135 ns max Full scale step input
Throughput Rate 1.5 MSPS max

POWER REQUIREMENTS

VDD 2.7/5.25 V min/max
V

2.7 /5.25 V min/max

DRIVE

7

I

Digital I/Ps = 0 V or V

DD

Normal Mode(Static) 0.5 mA typ VDD = 2.7 V to 5.25 V, SCLK on or off
Normal Mode (Operational) 3.2 mA max VDD = 4.75 V to 5.25 V

2.6 mA max VDD = 2.7 V to 3.6 V
Auto StandBy Mode 1.55 mA typ F
90 µA max (Static)
Auto Shutdown Mode 1 mA typ F
1 µA max (Static)
Full Shutdown Mode 1 µA max SCLK on or off

Power Dissipation

Normal Mode (Operational) 16 mW max VDD = 5 V
8 mW max VDD = 3 V
Auto Standby Mode (Static) 450 µW max VDD = 5 V
270 µW max VDD = 3 V
Auto Shutdown Mode (Static) 5 µW max VDD = 5 V
3 µW max VDD = 3 V
Full Shutdown Mode 5 µW max VDD = 5 V

3 µW max VDD = 3 V

1

Temperature ranges is as follows: B Versions: −40°C to +85°C.

2

See Terminology section.

3

Analog inputs with slew rates exceeding 27 V/µs (full-scale input sine wave > 3.5 MHz) within the acquisition time may cause an incorrect result to be returned by the

converter.

4

For full common mode range see

5

Sample tested during initial release to ensure compliance.

6

This device is operational with an external reference in the range 0.1 V to 3.5 V in differential mode and 0.1 V to VDD in pseudo-differential and single-ended modes.

See the Reference Section for more information.

7

Measured with a midscale dc input.

2.4 V min

INH

0.8 V max

INL

5

10 pF max

IN

= 200 µA;

SOURCE

= 200 µA

SINK

Straight (Natural) Binary

Twos Complement

+ t20 ns

tclk

CODING bit = 1

= 250 kSPS

SAMPLE

= 250 kSPS

SAMPLE

DRIVE

DRIVE

Rev. PrG | Page 6 of 32

Preliminary Technical Data AD7933/AD7934

TIMING SPECIFICATIONS1

VDD = V
T

MAX

Table 3.

Limit at T
Parameter AD7933 AD7934 Unit Description

2

f

CLKIN

24 24

t

QUIET

t1 10 10 ns min
t2 20 20 ns min
t3 TBD TBD ns min CLKIN Falling Edge to BUSY Rising Edge.
t4 0 0 ns min
t5 0 0 ns min
t6 25 25 ns min
t7 10 10 ns min
t8 5 5 ns min
t9 0.5 t
t10 0 0 ns min
t11 0 0 ns min
t12 55 55 ns min

3

t

50 50 ns max

13

4

t

5 5 ns min

14

40 40 ns max
t15 15 15 ns min
t16 5 5 ns min
t17 10 10 ns min Minimum Time between Reads/Writes.
t18 0 0 ns min
t19 5 5 ns min
t20 TBD TBD ns min CLKIN Falling Edge to BUSY Rising Edge.

1

Sample tested during initial release to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of VDD) and timed from a voltage level of 1.6 V.

All timing specifications given above are with a 25 pF load capacitance. See
(W/ = 1) Figure 38 Figure 39 Figure 40

2

Mark/space ratio for CLKIN is 40/60 to 60/40.

3

The time required for the output to cross TBD.

4

t14 is derived from the measured time taken by the data outputs to change 0.5 V. The measured number is then extrapolated back to remove the effects of charging or

discharging the 25 pF capacitor. This means that the time, t14, quoted in the timing characteristics is the true bus relinquish time of the part and is independent of the
bus loading.

=2.7 V to 5.25 V, Internal/External V

DRIVE

, unless otherwise noted.

, T

MIN

10 10

MAX

kHz
min

MHz
max

10 10 ns min

0.5 t

CLKIN

, , , and .

ns min New Data Valid before Falling Edge of BUSY.

CLKIN

= 2.5 V, unless otherwise noted, F

REF

= 24 MHz, F

CLKIN

= 1.5 MSPS; TA = T

SAMPLE

MIN

to

Minimum time between end of read and start of next conversion, i.e., time from when the
data bus goes into three-state until the next falling edge of CONVST.

CONVST
CONVST

CS
CS
WR
Data Setup Time before WR
Data Hold after WR

CS
CS
RD
Data Access Time after RD
Bus Relinquish Time after RD
Bus Relinquish Time after RD
HBEN to RD
HBEN to RD

HBEN to WR
HBEN to WR

Pulse Width.
Falling Edge to CLKIN Falling Edge Setup Time.

to WR Setup Time.
to WR Hold Time.

Pulse Width.

.

.

to RD Setup Time.
to RD Hold Time.

Pulse Width.

.

.

.
Setup Time.
Hold Time.

Setup Time.
Hold Time.

Figure 37. AD7933/AD7934 Parallel Interface—Conversion and Read Cycle in Word Mode

Rev. PrG | Page 7 of 32

AD7933/AD7934 Preliminary Technical Data

ABSOLUTE MAXIMUM RATINGS

T

= 25°C, unless otherwise noted.

A

Table 4.

Parameter Rating

VDD to AGND/DGND −0.3 V to +7 V
V

to AGND/DGND −0.3 V to VDD +0.3 V

DRIVE

Analog Input Voltage to AGND −0.3 V to VDD + 0.3 V
Digital Input Voltage to DGND −0.3 V to +7 V
V

to VDD −0.3 V to VDD + 0.3 V

DRIVE

Digital Output Voltage to AGND −0.3 V to V
V

to AGND −0.3 V to VDD + 0.3 V

REFIN

DRIVE

+ 0.3 V

AGND to DGND −0.3 V to +0.3 V
Input Current to Any Pin Except Supplies1 ±10 mA
Operating Temperature Range

Commercial (B Version) −40°C to +85°C
Storage Temperature Range −65°C to +150°C
Junction Temperature 150°C
θJA Thermal Impedance 97.9°C/W (TSSOP)
θJC Thermal Impedance 14°C/W (TSSOP)

Lead Temperature, Soldering

Reflow Temperature (10 sec to 30 sec) 255°C

ESD 2 kV

1

Transient currents of up to 100 mA will not cause SCR latch-up.

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate
on the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.

Rev. PrG | Page 8 of 32

Preliminary Technical Data AD7933/AD7934

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

Table 5. Pin Function Description

Pin No. Mnemonic Description

1 VDD

Power Supply Input. The V
decoupled to AGND with a 0.1 µF capacitor and a 10 µF tantalum capacitor.

2

Word/Byte Input. When this input is logic high, word transfer mode is enabled and data is transferred to and

W/B

from the AD7933/AD7934 in 12-/10-bit words on Pins DB0/DB2 to DB11. When this pin is logic low, byte
transfer mode is enabled. Data and the channel ID is transferred on Pins DB0 to DB7 and Pin DB8/HBEN
assumes its HBEN functionality.

3 to 10 DB0 to DB7

Data Bits 0 to 7. Three-state parallel digital I/O pins that provide the conversion result and also allow the
control register to be programmed. These pins are controlled by CS, RD, and WR. The logic high/low voltage
levels for these pins are determined by the V
DB1) are always 0 and the LSB of the conversion result is available on DB2.

11 V

DRIVE

Logic Power Supply Input. The voltage supplied at this pin determines at what voltage the parallel interface of
the AD7933/AD7934 will operate. This pin should be decoupled to DGND. The voltage at this pin may be
different to that at V

12 DGND

Digital Ground. This is the ground reference point for all digital circuitry on the AD7933/AD7934. The DGND
and AGND voltages should ideally be at the same potential and must not be more than 0.3 V apart, even on a
transient basis.

13 DB8/HBEN

Data Bit 8/High Byte Enable. When W/B

, RD, and WR. When W/B is low, this pin acts as the high byte enable pin. When HBEN is low, the low byte

by CS
of data written to or read from the AD7933/AD7934 is on DB0 to DB7. When HBEN is high, the top four bits of
the data being written to or read from the AD7933/AD7934 are on DB0 to DB3 When reading from the device,
DB4 of the high byte is always 0 and DB5 and DB6 will contain the ID of the channel for which the conversion
result corresponds (see Channel Address Bits in Table 9). When writing to the device, DB4 to DB7 of the high
byte must be all 0s. Note that when reading from the AD7933, the two LSBs in the low byte are 0s and the
remaining 6 bits, conversion data.

14 to 16 DB9 to DB11

Data Bits 9 to 11. Three-state parallel digital I/O pins that provide the conversion result and also allow the
control register to be programmed in word mode. These pins are controlled by CS, RD, and WR. The logic
high/low voltage levels for these pins are determined by the V

17 BUSY

Busy Output. Logic output indicating the status of the conversion. The BUSY output goes high following the
falling edge of CONVST and stays high for the duration of the conversion. Once the conversion is complete and
the result is available in the output register, the BUSY output will go low. The track-and-hold returns to track
mode just prior to the falling edge of BUSY, and the acquisition time for the part begins when BUSY goes low.

18 CLKIN

Master Clock Input. The clock source for the conversion process is applied to this pin. Conversion time for the
AD7933/AD7934 takes 13.5 clock cycles. The frequency of the master clock input therefore determines the
conversion time and achievable throughput rate.

19

CONVST

Conversion Start Input. A falling edge on CONVST is used to initiate a conversion. The track-and-hold goes from

track to hold mode on the falling edge of CONVST
Following power-down, when operating in the auto shutdown or auto standby mode, a rising edge on
CONVST

is used to power up the device.

1

V

DD

2

W/B

3

DB0

4

DB1

DB2

DB3

DB4

DB5

DB6

DB7

V

DRIVE

DGND

DB8/HBEN DB11

DB9

5

6

(Not to Scale)

7

8

9

10

11

12

13

14

AD7933/

AD7934

TOP VIEW

28

VIN3

27

VIN2

26

VIN1

25

V

IN

24

V

REFIN/VREFOUT

23

AGND

22

CS

21

RD

20

WR

19

CONVST

18

CLKIN

17

BUSY

16

15

DB10

0

03713-0-006

Figure 2. Pin Configuration

range for the AD7933/AD7934 is from 2.7 V to 5.25 V. The supply should be

DD

input. When reading from the AD7933, the two LSBs (DB0 and

DRIVE

but should never exceed VDD by more than 0.3 V.

DD

is high, this pin acts as Data Bit 8, a three-state I/O pin that is controlled

DRIVE

and the conversion process is initiated at this point.

input.

Rev. PrG | Page 9 of 32

AD7933/AD7934 Preliminary Technical Data

Pin No. Mnemonic Description

20
21

22

23 AGND

24 V

25 to 28 VIN0 to VIN3

Write Input. Active low logic input used in conjunction with CS to write data to the control register.

WR

Read Input. Active low logic input used in conjunction with CS to access the conversion result. The conversion

RD

result is placed on the data bus following the falling edge of RD

Chip Select. Active low logic input used in conjunction with RD and WR to read conversion data or write data to

CS

read while CS is low.

the control register.
Analog Ground. This is the ground reference point for all analog circuitry on the AD7933/AD7934. All analog

input signals and any external reference signal should be referred to this AGND voltage. The AGND and DGND
voltages should ideally be at the same potential and must not be more than 0.3 V apart, even on a transient
basis.

REFIN/VREFOUT

Reference Input/Output. This pin is connected to the internal reference and is the reference source for the ADC.
The nominal internal reference voltage is 2.5 V and this appears at this pin. This pin can be overdriven by an
external reference. The input voltage range for the external reference is 0.1 V to 3.5 V for differential mode and
is 0.1 V to V

in single-ended and pseudo-differential mode, depending on VDD.

DD

Analog Input 0 to Analog Input 3. Four analog input channels that are multiplexed into the on-chip track-and­hold. The analog inputs can be programmed to be four single ended inputs, two fully differential pairs or two
pseudo-differential pairs by setting the MODE bits in the control register appropriately (see Table 9). The
analog input channel to be converted can either be selected by writing to the address bits (ADD1 and ADD0) in
the control register prior to the conversion, or the on-chip sequencer can be used. The input range for all input
channels can either be 0 V to V

or 0 V to 2 × V

REF

and the coding can be binary or twos complement,

REF

depending on the states of the RANGE and CODING bits in the control register. Any unsed input channels
should be connected to AGND to avoid noise pickup.

Rev. PrG | Page 10 of 32