ANALOG DEVICES AD7924-KGD Service Manual
4-Channel, 1 MSPS, 12-Bit ADC with
A
V
Known Good Die
FEATURES
Fast throughput rate: 1 MSPS
Specified for AV
Low power
6 mW maximum at 1 MSPS with 3 V supplies
13.5 mW maximum at 1 MSPS with 5 V supplies
4 single-ended inputs with sequencer
Wide input bandwidth: 70 dB SNR at 50 kHz input frequency
Flexible power/serial clock speed management
No pipeline delays
High speed serial interface: SPI/QSPI™/MICROWIRE™/DSP
compatible
Shutdown mode: 0.5 μA maximum
16-lead TSSOP package
Qualified for automotive applications
Known good die (KGD): these die are fully guaranteed to
data sheet specifications.
GENERAL DESCRIPTION
The AD7924-KGD is a 12-bit, high speed, low power, 4-channel
successive approximation ADCs. The parts operate from a single
2.7 V to 5.25 V power supply and feature throughput rates up to
1 MSPS. The part contains a low noise, wide bandwidth track-andhold amplifier that can handle input frequencies in excess of 8 MHz.
The conversion process and data acquisition are controlled using
CS
and the serial clock signal, allowing the device to easily interface
with microprocessors or DSPs. The input signal is sampled on
the falling edge of
There are no pipeline delays associated with the part.
The AD7924-KGD uses advanced design techniques to achieve
very low power dissipation at maximum throughput rates. At
maximum throughput rates, the AD7924-KGD consumes 2 mA
maximum with 3 V supplies; with 5 V supplies, the current
consumption is 2.7 mA maximum.
Through the configuration of the control register, the analog input
range for the part can be selected as 0 V to REF
REF
, with either straight binary or twos complement output
IN
coding. The AD7924-KGD features four single-ended analog
inputs with a channel sequencer to allow a preprogrammed
selection of channels to be converted sequentially.
The conversion time for the AD7924-KGD is determined by the
SCLK frequency, which is also used as the master clock to control
the conversion.
Additional application and technical information can be found
in the AD7924 data sheet.
of 2.7 V to 5.25 V
DD
CS
and conversion is initiated at this point.
or 0 V to 2 ×
IN
Sequencer in 16-Lead TSSOP
AD7924-KGD
FUNCTIONAL BLOCK DIAGRAM
DD
REF
IN
VIN0
VIN1
VIN2
VIN3
I/P
MUX
AD7924-KGD
PRODUCT HIGHLIGHTS
1. High Throughput with Low Power Consumption.
The AD7924-KGD offers throughput rates up to 1 MSPS.
At the maximum throughput rate with 3 V supplies, the
AD7924-KGD dissipates only 6 mW of power maximum.
2. Four Single-Ended Inputs with Channel Sequencer.
A consecutive sequence of channels can be selected,
through which the ADC will cycle and convert on.
3. Single-Supply Operation with V
The AD7924-KGD operates from a single 2.7 V to 5.25 V
supply. The V
connect directly to 3 V or 5 V processor systems,
independent of V
4. Flexible Power/Serial Clock Speed Management.
The conversion rate is determined by the serial clock,
allowing the conversion time to be reduced by increasing
the serial clock speed. The part also features two shutdown
modes to maximize power efficiency at lower throughput
rates. Current consumption is 0.5 μA maximum when in
full shutdown.
5. No Pipeline Delay.
The part features a standard successive approximation
ADC with accurate control of the sampling instant via
CS
the
input and once-off conversion control.
T/H
SEQUENCER
AGND
Figure 1.
function allows the serial interface to
DRIVE
.
DD
12-BIT
SUCCESSIVE
APPROXIMATION
ADC
CONTROL LOGIC
Function.
DRIVE
SCLK
DOUT
DIN
CS
V
DRIVE
10106-001
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 www.analog.com
Fax: 781.461.3113 ©2011 Analog Devices, Inc. All rights reserved.
AD7924-KGD Known Good Die
TABLE OF CONTENTS
Features.............................................................................................. 1
General Description ......................................................................... 1
Functional Block Diagram .............................................................. 1
Product Highlights ........................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Timing Specifications .................................................................. 5
REVISION HISTORY
10/11—Revision 0: Initial Version
Absolute Maximum Ratings ............................................................6
ESD Caution...................................................................................6
Pad Configuration and Function Descriptions.............................7
Outline Dimensions..........................................................................8
Die Specifications and Assembly Recommendations ..............8
Ordering Guide .............................................................................8
Rev. 0 | Page 2 of 8
Known Good Die AD7924-KGD
SPECIFICATIONS
AVDD = V
Table 1.
Parameter Min Typ Max Unit Test Conditions/Comments
DYNAMIC PERFORMANCE f
Signal-to-(Noise + Distortion), SINAD 70 dB @ 5 V
69 dB @ 3 V, typically 69.5 dB
Signal-to-Noise Ratio, SNR 70 dB
Total Harmonic Distortion, THD −77 dB @ 5 V, typically −84 dB
−73 dB @ 3 V, typically −77 dB
Peak Harmonic or Spurious Noise, SFDR −78 dB @ 5 V, typically −86 dB
Intermodulation Distortion, IMD fa = 40.1 kHz, fb = 41.5 kHz
Second-Order Terms −90 dB
Third-Order Terms −90 dB
Aperture Delay 10 ns
Aperture Jitter 50 ps
Channel-to-Channel Isolation −85 dB fIN = 400 kHz
Full Power Bandwidth 8.2 MHz @ 3 dB
1.6 MHz @ 0.1 dB
DC ACCURACY
Resolution 12 Bits
Integral Nonlinearity, INL ±1 LSB
Differential Nonlinearity, DNL −0.9/+1.5 LSB Guaranteed no missed codes to 12 bits
0 V to REFIN Input Range Straight binary output coding
Offset Error ±8 LSB Typically ±0.5 LSB
Offset Error Match ±0.5 LSB
Gain Error ±1.5 LSB
Gain Error Match ±0.5 LSB
0 V to 2 × REFIN Input Range
Positive Gain Error ±1.5 LSB
Positive Gain Error Match ±0.5 LSB
Zero Code Error ±8 LSB Typically ±0.8 LSB
Zero Code Error Match ±0.5 LSB
Negative Gain Error ±1 LSB
Negative Gain Error Match ±0.5 LSB
ANALOG INPUT
Input Voltage Range 0 REFIN V RANGE bit set to 1
0 2 × REFIN V RANGE bit set to 0, AVDD/V
DC Leakage Current ±1 μA
Input Capacitance 20 pF
REFERENCE INPUT
REFIN Input Voltage 2.5 V ±1% specified performance
DC Leakage Current ±1 μA
REFIN Input Impedance 36 kΩ f
LOGIC INPUTS
Input High Voltage, V
Input Low Voltage, V
Input Current, IIN ±1 μA Typically 10 nA, VIN = 0 V or V
Input Capacitance, C
= 2.7 V to 5.25 V, REFIN = 2.5 V, f
DRIVE
0.7 × V
INH
0.3 × V
INL
1
10 pF
IN
= 20 MHz, TA = T
SCLK
V
DRIVE
to T
MIN
MAX
, unless otherwise noted. Temperature range is −40°C to +85°C.
V
DRIVE
= 50 kHz sine wave, f
IN
to +REFIN biased about REFIN with
−REF
IN
twos complement output coding
= 1 MSPS
SAMPLE
= 20 MHz
SCLK
= 4.75 V to 5.25 V
DRIVE
DRIVE
Rev. 0 | Page 3 of 8
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