4-Channel, 1 MSPS, 12-Bit ADC with
A
V
Known Good Die
FEATURES
Fast throughput rate: 1 MSPS
Specified for AV
Low power
6 mW maximum at 1 MSPS with 3 V supplies
13.5 mW maximum at 1 MSPS with 5 V supplies
4 single-ended inputs with sequencer
Wide input bandwidth: 70 dB SNR at 50 kHz input frequency
Flexible power/serial clock speed management
No pipeline delays
High speed serial interface: SPI/QSPI™/MICROWIRE™/DSP
compatible
Shutdown mode: 0.5 μA maximum
16-lead TSSOP package
Qualified for automotive applications
Known good die (KGD): these die are fully guaranteed to
data sheet specifications.
GENERAL DESCRIPTION
The AD7924-KGD is a 12-bit, high speed, low power, 4-channel
successive approximation ADCs. The parts operate from a single
2.7 V to 5.25 V power supply and feature throughput rates up to
1 MSPS. The part contains a low noise, wide bandwidth track-andhold amplifier that can handle input frequencies in excess of 8 MHz.
The conversion process and data acquisition are controlled using
CS
and the serial clock signal, allowing the device to easily interface
with microprocessors or DSPs. The input signal is sampled on
the falling edge of
There are no pipeline delays associated with the part.
The AD7924-KGD uses advanced design techniques to achieve
very low power dissipation at maximum throughput rates. At
maximum throughput rates, the AD7924-KGD consumes 2 mA
maximum with 3 V supplies; with 5 V supplies, the current
consumption is 2.7 mA maximum.
Through the configuration of the control register, the analog input
range for the part can be selected as 0 V to REF
REF
, with either straight binary or twos complement output
IN
coding. The AD7924-KGD features four single-ended analog
inputs with a channel sequencer to allow a preprogrammed
selection of channels to be converted sequentially.
The conversion time for the AD7924-KGD is determined by the
SCLK frequency, which is also used as the master clock to control
the conversion.
Additional application and technical information can be found
in the AD7924 data sheet.
of 2.7 V to 5.25 V
DD
CS
and conversion is initiated at this point.
or 0 V to 2 ×
IN
Sequencer in 16-Lead TSSOP
AD7924-KGD
FUNCTIONAL BLOCK DIAGRAM
DD
REF
IN
VIN0
VIN1
VIN2
VIN3
I/P
MUX
AD7924-KGD
PRODUCT HIGHLIGHTS
1. High Throughput with Low Power Consumption.
The AD7924-KGD offers throughput rates up to 1 MSPS.
At the maximum throughput rate with 3 V supplies, the
AD7924-KGD dissipates only 6 mW of power maximum.
2. Four Single-Ended Inputs with Channel Sequencer.
A consecutive sequence of channels can be selected,
through which the ADC will cycle and convert on.
3. Single-Supply Operation with V
The AD7924-KGD operates from a single 2.7 V to 5.25 V
supply. The V
connect directly to 3 V or 5 V processor systems,
independent of V
4. Flexible Power/Serial Clock Speed Management.
The conversion rate is determined by the serial clock,
allowing the conversion time to be reduced by increasing
the serial clock speed. The part also features two shutdown
modes to maximize power efficiency at lower throughput
rates. Current consumption is 0.5 μA maximum when in
full shutdown.
5. No Pipeline Delay.
The part features a standard successive approximation
ADC with accurate control of the sampling instant via
CS
the
input and once-off conversion control.
T/H
SEQUENCER
AGND
Figure 1.
function allows the serial interface to
DRIVE
.
DD
12-BIT
SUCCESSIVE
APPROXIMATION
ADC
CONTROL LOGIC
Function.
DRIVE
SCLK
DOUT
DIN
CS
V
DRIVE
10106-001
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 www.analog.com
Fax: 781.461.3113 ©2011 Analog Devices, Inc. All rights reserved.
AD7924-KGD Known Good Die
TABLE OF CONTENTS
Features.............................................................................................. 1
General Description ......................................................................... 1
Functional Block Diagram .............................................................. 1
Product Highlights ........................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Timing Specifications .................................................................. 5
REVISION HISTORY
10/11—Revision 0: Initial Version
Absolute Maximum Ratings ............................................................6
ESD Caution...................................................................................6
Pad Configuration and Function Descriptions.............................7
Outline Dimensions..........................................................................8
Die Specifications and Assembly Recommendations ..............8
Ordering Guide .............................................................................8
Rev. 0 | Page 2 of 8
Known Good Die AD7924-KGD
SPECIFICATIONS
AVDD = V
Table 1.
Parameter Min Typ Max Unit Test Conditions/Comments
DYNAMIC PERFORMANCE f
Signal-to-(Noise + Distortion), SINAD 70 dB @ 5 V
69 dB @ 3 V, typically 69.5 dB
Signal-to-Noise Ratio, SNR 70 dB
Total Harmonic Distortion, THD −77 dB @ 5 V, typically −84 dB
−73 dB @ 3 V, typically −77 dB
Peak Harmonic or Spurious Noise, SFDR −78 dB @ 5 V, typically −86 dB
Intermodulation Distortion, IMD fa = 40.1 kHz, fb = 41.5 kHz
Second-Order Terms −90 dB
Third-Order Terms −90 dB
Aperture Delay 10 ns
Aperture Jitter 50 ps
Channel-to-Channel Isolation −85 dB fIN = 400 kHz
Full Power Bandwidth 8.2 MHz @ 3 dB
1.6 MHz @ 0.1 dB
DC ACCURACY
Resolution 12 Bits
Integral Nonlinearity, INL ±1 LSB
Differential Nonlinearity, DNL −0.9/+1.5 LSB Guaranteed no missed codes to 12 bits
0 V to REFIN Input Range Straight binary output coding
Offset Error ±8 LSB Typically ±0.5 LSB
Offset Error Match ±0.5 LSB
Gain Error ±1.5 LSB
Gain Error Match ±0.5 LSB
0 V to 2 × REFIN Input Range
Positive Gain Error ±1.5 LSB
Positive Gain Error Match ±0.5 LSB
Zero Code Error ±8 LSB Typically ±0.8 LSB
Zero Code Error Match ±0.5 LSB
Negative Gain Error ±1 LSB
Negative Gain Error Match ±0.5 LSB
ANALOG INPUT
Input Voltage Range 0 REFIN V RANGE bit set to 1
0 2 × REFIN V RANGE bit set to 0, AVDD/V
DC Leakage Current ±1 μA
Input Capacitance 20 pF
REFERENCE INPUT
REFIN Input Voltage 2.5 V ±1% specified performance
DC Leakage Current ±1 μA
REFIN Input Impedance 36 kΩ f
LOGIC INPUTS
Input High Voltage, V
Input Low Voltage, V
Input Current, IIN ±1 μA Typically 10 nA, VIN = 0 V or V
Input Capacitance, C
= 2.7 V to 5.25 V, REFIN = 2.5 V, f
DRIVE
0.7 × V
INH
0.3 × V
INL
1
10 pF
IN
= 20 MHz, TA = T
SCLK
V
DRIVE
to T
MIN
MAX
, unless otherwise noted. Temperature range is −40°C to +85°C.
V
DRIVE
= 50 kHz sine wave, f
IN
to +REFIN biased about REFIN with
−REF
IN
twos complement output coding
= 1 MSPS
SAMPLE
= 20 MHz
SCLK
= 4.75 V to 5.25 V
DRIVE
DRIVE
Rev. 0 | Page 3 of 8
AD7924-KGD Known Good Die
Parameter Min Typ Max Unit Test Conditions/Comments
LOGIC OUTPUTS
Output High Voltage, VOH V
Output Low Voltage, VOL 0.4 V I
Floating-State Leakage Current ±1 μA
Floating-State Output Capacitance1 10 pF
Output Coding Straight (natural) binary CODING bit set to 1
Twos complement CODING bit set to 0
CONVERSION RATE
Conversion Time 800 ns 16 SCLK cycles with SCLK at 20 MHz
Track-and-Hold Acquisition Time 300 ns Sine wave input
300 ns Full-scale step input
Throughput Rate 1 MSPS
POWER REQUIREMENTS
VDD 2.7 5.25 V
V
2.7 5.25 V
DRIVE
IDD Digital inputs = 0 V or V
Normal Mode (Static) 600 μA AVDD = 2.7 V to 5.25 V, SCLK on or off
Normal Mode (Operational) 2.7 mA AVDD = 4.75 V to 5.25 V, f
2 mA AVDD = 2.7 V to 3.6 V, f
Auto Shutdown Mode 960 μA f
0.5 μA Static
Full Shutdown Mode 0.5 μA SCLK on or off (20 nA typ)
Power Dissipation
Normal Mode (Operational) 13.5 mW AVDD = 5 V, f
6 mW AVDD = 3 V, f
Auto Shutdown Mode (Static) 2.5 μW AVDD = 5 V
1.5 μW AVDD = 3 V
Full Shutdown Mode 2.5 μW AVDD = 5 V
1.5 μW AVDD = 3 V
1
Sample tested @ 25°C to ensure compliance.
− 0.2 V I
DRIVE
= 200 μA, AVDD = 2.7 V to 5.25 V
SOURCE
= 200 μA
SINK
DRIVE
SCLK
= 20 MHz
SCLK
= 250 kSPS
SAMPLE
= 20 MHz
SCLK
= 20 MHz
SCLK
= 20 MHz
Rev. 0 | Page 4 of 8
Known Good Die AD7924-KGD
TIMING SPECIFICATIONS
AVDD = 2.7 V to 5.25 V, V
Table 2.
Parameter1
2
f
10 10 kHz min
SCLK
AV
= 3 V AVDD = 5 V Unit
DD
20 20 MHz max
t
16 × t
CONVER T
t
50 50 ns min
QUIET
SCLK
t2 10 10 ns min
3
t
35 30 ns max
3
3
t
40 40 ns max Data access time after SCLK falling edge
4
t5 0.4 × t
t6 0.4 × t
SCLK
SCLK
t7 10 10 ns min SCLK to DOUT valid hold time
4
t
15/45 15/35 ns min/ns max SCLK falling edge to DOUT high impedance
8
t9 10 10 ns min DIN setup time prior to SCLK falling edge
t10 5 5 ns min DIN hold time after SCLK falling edge
t11 20 20 ns min
t12 1 1 s max Power-up time from full shutdown/auto shutdown modes
1
Sample tested @ 25°C to ensure compliance. All input signals are specified with tR = tF = 5 ns (10% to 90% of AVDD) and timed from a voltage level of 1.6 V (see Figure 2).
The 3 V operating range spans from 2.7 V to 3.6 V. The 5 V operating range spans from 4.75 V to 5.25 V.
2
Mark/space ratio for the SCLK input is 40/60 to 60/40.
3
Measured with the load circuit of Figure 2 and defined as the time required for the output to cross 0.4 V or 0.7 × V
4
t8 is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 2. The measured number is then extrapolated
back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t8, quoted in the timing characteristics is the true bus relinquish
time of the part and is independent of the bus loading.
≤ AVDD, REFIN = 2.5 V, TA = T
DRIVE
Limit at T
16 × t
0.4 × t
0.4 × t
, T
MIN
MAX
SCLK
ns min SCLK low pulse width
SCLK
ns min SCLK high pulse width
SCLK
MIN
to T
, unless otherwise noted.
MAX
Description
Minimum quiet time required between the CS
rising edge and the start
of the next conversion
to SCLK setup time
CS
Delay from CS
16th SCLK falling edge to CS
200µA
I
until DOUT three-state disabled
high
DRIVE
OL
.
TO
OUTPUT
PIN
50pF
C
L
200µA
I
OH
1.6V
10106-002
Figure 2. Load Circuit for Digital Output Timing Specifications
Rev. 0 | Page 5 of 8
AD7924-KGD Known Good Die
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 3.
Parameter Rating
AVDD to AGND −0.3 V to +7 V
V
to AGND −0.3 V to AVDD + 0.3 V
DRIVE
Analog Input Voltage to AGND −0.3 V to AVDD + 0.3 V
Digital Input Voltage to AGND −0.3 V to +7 V
Digital Output Voltage to AGND −0.3 V to AVDD + 0.3 V
REFIN to AGND −0.3 V to AVDD + 0.3 V
Input Current to Any Pin Except
Supplies
Operating Temperature Range −40°C to +85°C
Storage Temperature Range −65°C to +150°C
Junction Temperature 150°C
Lead Temperature, Soldering
Vapor Phase (60 secs) 215°C
Infrared (15 secs) 220°C
ESD 1.5 kV
1
Transient currents of up to 100 mA do not cause SCR latch-up.
1
±10 mA
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
Rev. 0 | Page 6 of 8
Known Good Die AD7924-KGD
PAD CONFIGURATION AND FUNCTION DESCRIPTIONS
24
1
2
3
4
5
6
7
8
9
11 12 13
10
Figure 3. Pad Configuration
23
22
21
20
19
18
17
16
15
14
10106-003
Table 4. Pad Function Descriptions
Pad No. X-Axis (μm) Y-Axis (μm) Mnemonic Pad Type Description
1 −580.3 +965.95 SCLK Single Serial Clock
2 −815.4 +932.75 DIN Single Data In, Logic Input.
3 −815.4 +677.6
CS
Single Chip Select.
4A −850.85 +416 AGND Double Analog Ground.
4B −850.85 +316 AGND Double Analog Ground.
5 −854.15 +50.35 AVDD Double Analog Power Supply Input.
6 −854.4 −258.7 AVDD Double Analog Power Supply Input.
7A −850.45 −546 VREF Double Reference Input.
7B −850.45 −646 VREF Double Reference Input.
8 −854.2 −877.9 NC Single No Connect. Do not connect to this pin.
9 −854.2 −1070.1 AGND Single Analog Ground.
10 −712.45 −1070.1 AGND Single Analog Ground.
11 −458.95 −1054.1 NC Single No Connect. Do not connect to this pin.
12 −108.95 −1054.1 NC Single No Connect. Do not connect to this pin.
13 +200.85 −1054.1 NC Single No Connect. Do not connect to this pin.
14 +550.85 −1054.1 NC Single No Connect. Do not connect to this pin.
15 +916.2 −1021.15 VIN3 Single Analog Input 0.
16 +916.2 −671.15 VIN2 Single Analog Input 1.
17 +916.2 −510.75 VIN1 Single Analog Input 2.
18 +916.2 −160.75 VIN0 Single Analog Input 3.
19A 880.85 144 AGND Double Analog Ground.
19B 880.85 244 AGND Double Analog Ground.
20 896.05 537.15 DOUT Single Data Output.
21 865.35 885.8 VDRIVE Single Logic Power Supply Input.
22 865.35 1025.8 VDRIVE Single Logic Power Supply Input.
23 725.35 1025.8 NC Single No Connect. Do not connect to this pin.
24A −191 +997.4 AGND Double Analog Ground.
24B −291 +997.4 AGND Double Analog Ground.
Rev. 0 | Page 7 of 8
AD7924-KGD Known Good Die
OUTLINE DIMENSIONS
2.300
0.500
14
23
15
22
21
20
19
18
17
16
0.092 × 0.092
2.620
SIDE VIEW
09-12-2011-A
2
3
4
5
6
7
8
9
1
11 12 13
10
24
TOP VIEW
(CIRCUIT SI DE)
Figure 4. 24-Pad Bare Die [CHIP]
(C-24-1)
Dimensions shown in millimeters
DIE SPECIFICATIONS AND ASSEMBLY RECOMMENDATIONS
Table 5. Die Specifications
Parameter Value Unit
Chip Size 2180 (x) × 2450 (y) µm
Scribe Line Width 120 (x) × 170 (y) µm
Die Size 2300 (x) × 2620 (y) µm
Thickness 500 µm
Backside Silicon Not applicable
Passivation Nitride Not applicable
Bond Pads (Minimum) 92 × 92 µm
Bond Pad Composition 98.5% Al, 1% Si, 0.5% Cu %
ESD 1.5 kV
Table 6. Assembly Recommendations
Assembly Component Recommendation
Die Attach No special recommendations
Bonding Method Gold ball or aluminum wedge
Bonding Sequence 9 and 10
ORDERING GUIDE
Model Temperature Range Package Description Package Option
AD7924-KGD-DF −40°C to +85°C 24-Pad Bare Die [CHIP] C-24-1
©2011 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D10106-0-10/11(0)
Rev. 0 | Page 8 of 8
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