with Sequencer in 16-Lead TSSOP
AD7923-EP
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
Trademarks and registered trademarks are the property of their respective owners.
Fax: 781.461.3113 ©2011 Analog Devices, Inc. All rights reserved.
•
•
•
•
•
•
•
•
•
•
•
•
•
V
IN
3
T/H
INPUT
MUX
SEQUENCER
CONTROL LOGIC
12-BIT
SUCCESSIVE
APPROXIMATION
ADC
GND
SCLK
DOUT
DIN
CS
V
DRIVE
AV
DD
AD7923-EP
REF
IN
VIN0
10190-001
Enhanced Product
FEATURES
Fast throughput rate: 200 kSPS
Specified for AV
Low power
3.6 mW max at 200 kSPS with 3 V supply
7.5 mW max at 200 kSPS with 5 V supply
4 (single-ended) inputs with sequencer
Wide input bandwidth
70 dB min SNR at 50 kHz input frequency
Flexible power/serial clock speed management
No pipeline delays
High speed serial interface SPI
MICROWIRE™-/DSP-compatible
Shutdown mode: 0.5 µA max
16-lead TSSOP package
Support defense and aerospace applications (AQEC)
Military temperature range (−55°C to +125°C)
Controlled manufacturing baseline
One assembly/test site
One fabrication site
Enhanced product change notification
Qualification data available on request
of 2.7 V to 5.25 V
DD
®-/QSPI™-/
4-Channel, 200 kSPS 12-Bit ADC
clock to control the conversion. The conversion time can be as
short as 800 ns with a 20 MHz SCLK.
Additional application and technical information can be found
in the AD7923 data sheet.
FUNCTIONAL BLOCK DIAGRAM
GENERAL DESCRIPTION
The AD7923-EP is a 12-bit, high speed, low power, 4-channel,
successive approximation (SAR) ADC. It operates from a single
2.7 V to 5.25 V power supply and features throughput rates up to
200 kSPS. It contains a low noise, wide bandwidth track-and-hold
amplifier that can handle input frequencies in excess of 8 MHz.
The conversion process and data acquisition are controlled by
CS
and the serial clock, allowing the device to easily interface
with microprocessors or DSPs. The input signal is sampled on
the falling edge of
The AD7923-EP uses advanced design techniques to achieve
very low power dissipation at maximum throughput rates. At
maximum throughput rates, it consumes 1.2 mA maximum
with 3 V supplies and 1.5 mA maximum with 5 V supplies.
Through the configuration of the control register, the analog
input range can be selected as 0 V to REF
with either straight binary or twos complement output coding.
The AD7923-EP features four single-ended analog inputs with a
channel sequencer to allow a preprogrammed selection of
channels to be converted sequentially.
The conversion time for the AD7923-EP is determined by the
serial clock, SCLK, frequency, since this is used as the master
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
CS
; the conversion is also initiated at this point.
or 0 V to 2 × REFIN,
IN
PRODUCT HIGHLIGHTS
1. High Throughput with Low Power Consumption.
2. Four Single-Ended Inputs with a Channel Sequencer.
3. Single-Supply Operation with V
4. Flexible Power/Serial Clock Speed Management.
5. No Pipeline Delay.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Figure 1.
The AD7923-EP offers up to 200 kSPS throughput rates.
At the maximum throughput rate with 3 V supplies, the
AD7923-EP dissipates just 3.6 mW of power.
Function.
DRIVE
The V
function allows the serial interface to connect
DRIVE
directly to either 3 V or 5 V processor systems independent
of AV
DD
.
The conversion rate is determined by the serial clock,
allowing the conversion time to be reduced through the
serial clock speed increase. The part also features various
shutdown modes to maximize power efficiency at lower
throughput rates. Current consumption is 0.5 µA maximum
when in full shutdown.
The part features a SAR ADC with accurate control of the
sampling instant via a
CS
input and once off conversion
control.
www.analog.com
AD7923-EP Enhanced Product
TABLE OF CONTENTS
Features .............................................................................................. 1
General Description ......................................................................... 1
Functional Block Diagram .............................................................. 1
Product Highlights ........................................................................... 1
Specifications ..................................................................................... 3
Timing Specifications .................................................................. 5
REVISION HISTORY
10/11—Revision 0: Initial Version
Absolute Maximum Ratings ............................................................6
ESD Caution...................................................................................6
Pin Configuration and Function Description ...............................7
Typical Performance Characteristics ..............................................8
Outline Dimensions ..........................................................................9
Ordering Guide .............................................................................9
Rev. 0 | Page 2 of 12
Enhanced Product AD7923-EP
DYNAMIC PERFORMANCE
fIN = 50 kHz sine wave, f
= 20 MHz
Total Harmonic Distortion (THD)
−77
dB max
@ 5 V typ, −84 dB
Integral Nonlinearity
±1
LSB max
SPECIFICATIONS
AVDD = V
version): −55°C to +125°C.
Table 1.
Parameter EP Version1 Unit Test Conditions/Comments
Signal-to-(Noise + Distortion) (SINAD) 70 dB min @ 5 V, –40°C to +85°C
69 dB min @ 5 V, 85°C to 125°C, typ 70 dB
69 dB min @ 3 V typ 70 dB, –40°C to +125°C
Signal-to-Noise (SNR) 70 dB min
−73 dB max @ 3 V typ,−77 dB
Peak Harmonic or Spurious Noise −78 dB max @ 5 V typ, −86 dB
(SFDR) −76 dB max @ 3 V typ, −80 dB
Intermodulation Distortion (IMD) fA = 40.1 kHz, fB = 41.5 kHz
Second Order Terms −90 dB typ
Third Order Terms −90 dB typ
Aperture Delay 10 ns typ
Aperture Jitter 50 ps typ
Channel-to-Channel Isolation −85 dB typ fIN = 400 kHz
Full Power Bandwidth 8.2 MHz typ @ 3 dB
1.6 MHz typ @ 0.1 dB
DC ACCURACY
Resolution 12 Bits
= 2.7 V to 5.25 V, REFIN = 2.5 V, f
DRIVE
= 20 MHz, TA = T
SCLK
MIN
to T
, unless otherwise noted. Temperature range (EP
MAX
SCLK
Differential Nonlinearity −0.9/+1.5 LSB max Guaranteed no missed codes to 12 bits
0 V to REFIN Input Range Straight binary output coding
Offset Error ±8 LSB max Typ ±0.5 LSB
Offset Error Match ±0.5 LSB max
Gain Error ±1.5 LSB max
Gain Error Match ±0.5 LSB max
0 V to 2 × REFIN Input Range −REFIN to +REFIN biased about REFIN with twos
complement output coding
Positive Gain Error ±1.5 LSB max
Positive Gain Error Match ±0.5 LSB max
Zero-Code Error ±8 LSB max Typ ±0.8 LSB
Zero-Code Error Match ±0.5 LSB max
Negative Gain Error ±1 LSB max
Negative Gain Error Match ±0.5 LSB max
ANALOG INPUT
Input Voltage Range 0 to REFIN V Range bit set to 1
0 to 2 × REFIN V Range bit set to 0, AVDD = 4.75 V to 5.25 V
DC Leakage Current ±1 µA max
Input Capacitance 20 pF typ
REFERENCE INPUT
REFIN Input Voltage 2.5 V ±1% specified performance
DC Leakage Current ±1 µA max
REFIN Input Impedance 36 kΩ typ f
= 200 kSPS
SAMPLE
Rev. 0 | Page 3 of 12
AD7923-EP Enhanced Product
Input Capacitance, C
10
pF max
Auto Shutdown (Static)
2.5
µW max
AVDD = 5 V
Parameter EP Version1 Unit Test Conditions/Comments
LOGIC INPUTS
Input High Voltage, V
Input Low Voltage, V
Input Current, IIN ±1 µA max Typ 10 nA, VIN = 0 V or V
LOGIC OUTPUTS
Output High Voltage, VOH V
Output Low Voltage, VOL 0.4 V max I
Floating-State Leakage Current ±1 µA max
Floating-State Output Capacitance2 1 pF max
Output Coding Twos Complement Coding bit set to 0
Straight (Natural)
CONVERSION RATE
Conversion Time
Track-and-Hold Acquisition Time 800 ns max 16 SCLK cycles with SCLK at 20 MHz
300 ns max Sinewave input
300 ns max Full-scale step Input
Throughput Rate 200 kSPS max
POWER REQUIREMENTS
AVDD 2.7/5.25 V min/max
V
2.7/5.25 V min/max
DRIVE
IDD Digital I/Ps = 0 V or V
During Conversion 2.7 mA max AVDD = 4.75 V to 5.25 V, f
2.0 mA max AVDD = 2.7 V to 3.6 V, f
Normal Mode (Static) 600 µA typ AVDD = 2.7 V to 5.25 V, SCLK on or off
Normal Mode (Operational) f
1.2 mA max AVDD = 2.7 V to 3.6 V, f
Using Auto Shutdown Mode f
650 µA typ AVDD = 2.7 V to 3.6 V, f
Auto Shutdown (Static) 0.5 µA max SCLK on or off (20 nA typ)
Full Shutdown Mode 0.5 µA max SCLK on or off (20 nA typ)
Power Dissipation
Normal Mode (Operational) f
3.6 mW max AVDD = 3 V, f
0.7 × V
INH
0.3 × V
INL
2
IN
Binary
= 200 kSPS 1.5 mA max AVDD = 4.75 V to 5.25 V, f
SAMPLE
= 200 kSPS 900 µA typ AVDD = 4.75 V to 5.25 V, f
SAMPLE
= 200 kSPS 7.5 mW max AVDD = 5 V, f
SAMPLE
V min
DRIVE
V max
DRIVE
– 0.2 V min I
DRIVE
Coding bit set to 1
DRIVE
= 200 µA, AVDD = 2.7 V to 5.25 V
SOURCE
= 200 µA
SINK
DRIVE
SCLK
= 20 MHz
SCLK
SCLK
= 20 MHz
SCLK
SAMPLE
SAMPLE
= 20 MHz
SCLK
= 20 MHz
SCLK
= 20 MHz
= 20 MHz
= 200 kSPS
= 200 kSPS
1.5 µW max AVDD = 3 V
Full Shutdown Mode 2.5 µW max AVDD = 5 V
1.5 µW max AVDD = 3 V
1
Temperature range: EP Version: −55°C to +125°C.
2
Sample tested @ 25°C to ensure compliance.
Rev. 0 | Page 4 of 12
Enhanced Product AD7923-EP
200µA I
OL
200µA I
OH
1.6V
TO OUTPUT
PIN
C
L
50pF
10190-002
TIMING SPECIFICATIONS
AVDD = 2.7 V to 5.25 V, V
Table 2.
Limit at T
Parameter AVDD = 3 V AVDD = 5 V Unit Description
2
f
10 10 kHz min
SCLK
20 20 MHz max
t
16 × t
CONVERT
t
50 50 ns min
QUIET
SCLK
t2 10 10 ns min
3
t
35 30 ns max
3
3
t
40 40 ns max Data access time after SCLK falling edge
4
t5 0.4 × t
t6 0.4 × t
SCLK
SCLK
t7 10 10 ns min SCLK to DOUT valid hold time
4
t
15/45 15/35 ns min/max SCLK falling edge to DOUT high impedance
8
t9 10 10 ns min DIN set-up time prior to SCLK falling edge
t10 5 5 ns min DIN hold time after SCLK falling edge
t11 20 20 ns min
t12 1 1 µs max Power-Up time from full power-down/auto shutdown mode
1
Sample tested at 25°C to ensure compliance. All input signals are specified with tR = tF = 5 ns (10% to 90% of AVDD) and timed from a voltage level of 1.6 V. See Figure 2.
The 3 V operating range spans from 2.7 V to 3.6 V. The 5 V operating range spans from 4.75 V to 5.25 V.
2
The mark/space ratio for the SCLK input is 40/60 to 60/40.
3
Measured with the load circuit of Figure 2 and defined as the time required for the output to cross 0.4 V or 0.7 × V
4
t8 is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 2. The measured number is then extrapolated
back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, quoted in the timing characteristics t
time of the part and is independent of the bus loading.
≤ AVDD, REFIN = 2.5 V, TA = T
DRIVE
, T
MIN
MAX
16 × t
0.4 × t
0.4 × t
SCLK
ns min SCLK low pulse width
SCLK
ns min SCLK high pulse width
SCLK
to T
MIN
Minimum quiet time required between
, unless otherwise noted.1
MAX
CS
rising edge and start of next
conversion
CS
to SCLK set-up time
Delay from CS until DOUT three-state disabled
Sixteenth SCLK falling edge to CS high
.
DRIVE
, is the true bus relinquish
8
Figure 2. Load Circuit for Digital Output Timing Specification
Rev. 0 | Page 5 of 12
AD7923-EP Enhanced Product
Input Current to Any Pin Except
±10 mA
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 3.
Parameter Rating
AVDD to AGND
V
to AGND
DRIVE
Analog Input Voltage to AGND −0.3 V to AVDD + 0.3 V
Digital Input Voltage to AGND −0.3 V to +7 V
Digital Output Voltage to AGND −0.3 V to AVDD + 0.3 V
REFIN to AGND
−0.3 V to +7 V
−0.3 V to AVDD + 0.3 V
−0.3 V to AVDD + 0.3 V
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or
any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
Supplies
Operating Temperature Range(EP
Version)
Storage Temperature Range −65°C to +150°C
Junction Temperature 150°C
TSSOP Package, Power Dissipation 450 mW
θJA Thermal Impedance
θJC Thermal Impedance
Lead Temperature, Soldering
Vapor Phase (60 sec) 215°C
Infrared (15 sec) 220°C
Pb-free Temperature, Soldering
Reflow 260(+0)°C
ESD 1.5 kV
1
Transient currents of up to 100 mA do not cause SCR latchup.
1
−55°C to +125°C
150.4°C/W (TSSOP)
27.6°C/W (TSSOP)
Rev. 0 | Page 6 of 12
Enhanced Product AD7923-EP
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
DIN
CS
AGND
REF
IN
AV
DD
AV
DD
SCLK
V
DRIVE
DOUT
AGND
V
IN
2
AGND V
IN
3
V
IN
1
V
IN
0
AGND
AD7923-EP
TOP VIEW
(Not to S cale)
10190-003
No.
Mnemonic
Function
13, 16
external reference signal should be referred to this AGND voltage. All AGND pins should be connected together.
5, 6
AVDD Analog Power Supply Input. The AVDD range for the AD7923-EP is from 2.7 V to 5.25 V. For the 0 V to 2 × REFIN range,
operates.
PIN CONFIGURATION AND FUNCTION DESCRIPTION
Figure 3. Pin Configuration
Table 4. Pin Function Descriptions
Pin
1 SCLK Serial Clock. Logic Input. SCLK provides the serial clock for accessing data for the part. This clock input is also used
as the clock source for the AD7923-EP conversion process.
2 DIN Data In. Logic Input. Data to be written to the control register is provided on this input and is clocked into the
register on the falling edge of SCLK.
3
CS
Chip Select. Active low logic input. This input provides the dual function of initiating conversions on the AD7923-EP
and framing the serial data transfer.
4, 8,
AGND Analog Ground. Ground reference point for all analog circuitry on the AD7923-EP. All analog input signals and any
AVDD should be from 4.75 V to 5.25 V.
7 REFIN Reference Input for the AD7923-EP. An external reference must be applied to this input. The voltage range for the
external reference is 2.5 V ± 1% for specified performance.
12 to 9 VIN0 to VIN3 Analog Input 0 through Analog Input 3. Four single-ended analog input channels that are multiplexed into the on-
chip track-and-hold. The analog input channel to be converted is selected by using the Address Bits ADD1 and
ADD0 of the control register. The address bits in conjunction with the SEQ1 and SEQ0 bits allow the sequencer to
be programmed. The input range for all input channels can extend from 0 V to REF
or from 0 V to 2 × REFIN as
IN
selected via the range bit in the control register. Any unused input channels must be connected to AGND to avoid
noise pickup.
14 DOUT Data Out. Logic Output. The conversion result from the AD7923-EP is provided on this output pin as a serial data
stream. The AD7923-EP serial data stream consists of two leading 0s, and two address bits indicating which channel
the conversion result corresponds to, followed by 12 bits of conversion data, MSB first. The output coding can be
selected as straight binary or twos complement via the coding bit in the control register. The data bits are clocked
out of the AD7923-EP on the SCLK falling edge.
15 V
Logic Power Supply Input. The voltage supplied at this pin determines at which voltage the serial interface
DRIVE
Rev. 0 | Page 7 of 12
AD7923-EP Enhanced Product
FREQUENCY ( kHz )
SNR (dB)
–10
–50
–30
–70
–90
–110
0 10 20 30 40 60 70 80 9050 100
4096 POINT FFT
AV
DD
= 4.75V
f
SAMPLE
= 200kSPS
f
IN
= 50 kHz
SINAD = 70.714dB
THD = –82.853dB
SFDR = –84.815dB
10190-004
INPUT FRE QUENCY (kHz)
THD (dB)
–55
–95
–90
–85
–80
–75
–70
–65
–60
10 100
f
SAMPLE
= 200kSPS
T
A
= 25°C
AV
DD
= 5.25V
RANGE = 0V TO RE F
IN
R
IN
= 100Ω
RIN = 1000Ω
RIN = 10Ω
R
IN
= 50Ω
10190-005
CODE
INL ERROR ( LSB)
1.0
0.6
0.8
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
–1.0
0 512 1024 1536 2048 2560 3072 3584 4096
AVDD = V
DRIVE
= 5V
TEMP = 25°C
10190-006
CODE
DNL ERROR (L S B)
1.0
0.6
0.8
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
–1.0
0 512 1024 1536 2048 2560 3072 3584 4096
AVDD = V
DRIVE
= 5V
TEMP = 25°C
10190-007
TYPICAL PERFORMANCE CHARACTERISTICS
Figure 4. Dynamic Performance at 200 kSPS
Figure 5. THD vs. Analog Input Frequency for Various Source Impedances
Figure 6. Typical INL
Figure 7. Typical DNL
Rev. 0 | Page 8 of 12
Enhanced Product AD7923-EP
OUTLINE DIMENSIONS
5.10
5.00
4.90
16
4.50
4.40
4.30
PIN 1
0.15
0.05
0.65
BSC
COPLANARITY
COMPLIANT TO JEDEC STANDARDS MO-153-AB
Figure 8. 16-Lead Thin Shrink Small Outline Package [TSSOP]
0.10
0.30
0.19
9
81
1.20
MAX
SEATING
PLANE
6.40
BSC
0.20
0.09
8°
0°
0.75
0.60
0.45
(RU-16)
Dimensions shown in millimeters
ORDERING GUIDE
Model
AD7923SRU-EP −55°C to +125°C ±1 16-Lead TSSOP RU-16
AD7923SRU-EP-RL7 −55°C to +125°C ±1 16-Lead TSSOP RU-16
1
Linearity error refers to integral linearity error.
Temperature Range Linearity Error (LSB)1 Package Description Package Option
Rev. 0 | Page 9 of 12
AD7923-EP Enhanced Product
NOTES
Rev. 0 | Page 10 of 12
Enhanced Product AD7923-EP
NOTES
Rev. 0 | Page 11 of 12
AD7923-EP Enhanced Product
©2011 Analog Devices, Inc. All rights reserved. Trademarks and
NOTES
registered trademarks are the property of their respective owners.
D10190-0-10/11(0)
Rev. 0 | Page 12 of 12
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