ANALOG DEVICES AD7923-EP Service Manual
with Sequencer in 16-Lead TSSOP
AD7923-EP
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
Trademarks and registered trademarks are the property of their respective owners.
Fax: 781.461.3113 ©2011 Analog Devices, Inc. All rights reserved.
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V
IN
3
T/H
INPUT
MUX
SEQUENCER
CONTROL LOGIC
12-BIT
SUCCESSIVE
APPROXIMATION
ADC
GND
SCLK
DOUT
DIN
CS
V
DRIVE
AV
DD
AD7923-EP
REF
IN
VIN0
10190-001
Enhanced Product
FEATURES
Fast throughput rate: 200 kSPS
Specified for AV
Low power
3.6 mW max at 200 kSPS with 3 V supply
7.5 mW max at 200 kSPS with 5 V supply
4 (single-ended) inputs with sequencer
Wide input bandwidth
70 dB min SNR at 50 kHz input frequency
Flexible power/serial clock speed management
No pipeline delays
High speed serial interface SPI
MICROWIRE™-/DSP-compatible
Shutdown mode: 0.5 µA max
16-lead TSSOP package
Support defense and aerospace applications (AQEC)
Military temperature range (−55°C to +125°C)
Controlled manufacturing baseline
One assembly/test site
One fabrication site
Enhanced product change notification
Qualification data available on request
of 2.7 V to 5.25 V
DD
®-/QSPI™-/
4-Channel, 200 kSPS 12-Bit ADC
clock to control the conversion. The conversion time can be as
short as 800 ns with a 20 MHz SCLK.
Additional application and technical information can be found
in the AD7923 data sheet.
FUNCTIONAL BLOCK DIAGRAM
GENERAL DESCRIPTION
The AD7923-EP is a 12-bit, high speed, low power, 4-channel,
successive approximation (SAR) ADC. It operates from a single
2.7 V to 5.25 V power supply and features throughput rates up to
200 kSPS. It contains a low noise, wide bandwidth track-and-hold
amplifier that can handle input frequencies in excess of 8 MHz.
The conversion process and data acquisition are controlled by
CS
and the serial clock, allowing the device to easily interface
with microprocessors or DSPs. The input signal is sampled on
the falling edge of
The AD7923-EP uses advanced design techniques to achieve
very low power dissipation at maximum throughput rates. At
maximum throughput rates, it consumes 1.2 mA maximum
with 3 V supplies and 1.5 mA maximum with 5 V supplies.
Through the configuration of the control register, the analog
input range can be selected as 0 V to REF
with either straight binary or twos complement output coding.
The AD7923-EP features four single-ended analog inputs with a
channel sequencer to allow a preprogrammed selection of
channels to be converted sequentially.
The conversion time for the AD7923-EP is determined by the
serial clock, SCLK, frequency, since this is used as the master
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
CS
; the conversion is also initiated at this point.
or 0 V to 2 × REFIN,
IN
PRODUCT HIGHLIGHTS
1. High Throughput with Low Power Consumption.
2. Four Single-Ended Inputs with a Channel Sequencer.
3. Single-Supply Operation with V
4. Flexible Power/Serial Clock Speed Management.
5. No Pipeline Delay.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Figure 1.
The AD7923-EP offers up to 200 kSPS throughput rates.
At the maximum throughput rate with 3 V supplies, the
AD7923-EP dissipates just 3.6 mW of power.
Function.
DRIVE
The V
function allows the serial interface to connect
DRIVE
directly to either 3 V or 5 V processor systems independent
of AV
DD
.
The conversion rate is determined by the serial clock,
allowing the conversion time to be reduced through the
serial clock speed increase. The part also features various
shutdown modes to maximize power efficiency at lower
throughput rates. Current consumption is 0.5 µA maximum
when in full shutdown.
The part features a SAR ADC with accurate control of the
sampling instant via a
CS
input and once off conversion
control.
www.analog.com
AD7923-EP Enhanced Product
TABLE OF CONTENTS
Features .............................................................................................. 1
General Description ......................................................................... 1
Functional Block Diagram .............................................................. 1
Product Highlights ........................................................................... 1
Specifications ..................................................................................... 3
Timing Specifications .................................................................. 5
REVISION HISTORY
10/11—Revision 0: Initial Version
Absolute Maximum Ratings ............................................................6
ESD Caution...................................................................................6
Pin Configuration and Function Description ...............................7
Typical Performance Characteristics ..............................................8
Outline Dimensions ..........................................................................9
Ordering Guide .............................................................................9
Rev. 0 | Page 2 of 12
Enhanced Product AD7923-EP
DYNAMIC PERFORMANCE
fIN = 50 kHz sine wave, f
= 20 MHz
Total Harmonic Distortion (THD)
−77
dB max
@ 5 V typ, −84 dB
Integral Nonlinearity
±1
LSB max
SPECIFICATIONS
AVDD = V
version): −55°C to +125°C.
Table 1.
Parameter EP Version1 Unit Test Conditions/Comments
Signal-to-(Noise + Distortion) (SINAD) 70 dB min @ 5 V, –40°C to +85°C
69 dB min @ 5 V, 85°C to 125°C, typ 70 dB
69 dB min @ 3 V typ 70 dB, –40°C to +125°C
Signal-to-Noise (SNR) 70 dB min
−73 dB max @ 3 V typ,−77 dB
Peak Harmonic or Spurious Noise −78 dB max @ 5 V typ, −86 dB
(SFDR) −76 dB max @ 3 V typ, −80 dB
Intermodulation Distortion (IMD) fA = 40.1 kHz, fB = 41.5 kHz
Second Order Terms −90 dB typ
Third Order Terms −90 dB typ
Aperture Delay 10 ns typ
Aperture Jitter 50 ps typ
Channel-to-Channel Isolation −85 dB typ fIN = 400 kHz
Full Power Bandwidth 8.2 MHz typ @ 3 dB
1.6 MHz typ @ 0.1 dB
DC ACCURACY
Resolution 12 Bits
= 2.7 V to 5.25 V, REFIN = 2.5 V, f
DRIVE
= 20 MHz, TA = T
SCLK
MIN
to T
, unless otherwise noted. Temperature range (EP
MAX
SCLK
Differential Nonlinearity −0.9/+1.5 LSB max Guaranteed no missed codes to 12 bits
0 V to REFIN Input Range Straight binary output coding
Offset Error ±8 LSB max Typ ±0.5 LSB
Offset Error Match ±0.5 LSB max
Gain Error ±1.5 LSB max
Gain Error Match ±0.5 LSB max
0 V to 2 × REFIN Input Range −REFIN to +REFIN biased about REFIN with twos
complement output coding
Positive Gain Error ±1.5 LSB max
Positive Gain Error Match ±0.5 LSB max
Zero-Code Error ±8 LSB max Typ ±0.8 LSB
Zero-Code Error Match ±0.5 LSB max
Negative Gain Error ±1 LSB max
Negative Gain Error Match ±0.5 LSB max
ANALOG INPUT
Input Voltage Range 0 to REFIN V Range bit set to 1
0 to 2 × REFIN V Range bit set to 0, AVDD = 4.75 V to 5.25 V
DC Leakage Current ±1 µA max
Input Capacitance 20 pF typ
REFERENCE INPUT
REFIN Input Voltage 2.5 V ±1% specified performance
DC Leakage Current ±1 µA max
REFIN Input Impedance 36 kΩ typ f
= 200 kSPS
SAMPLE
Rev. 0 | Page 3 of 12
AD7923-EP Enhanced Product
Input Capacitance, C
10
pF max
Auto Shutdown (Static)
2.5
µW max
AVDD = 5 V
Parameter EP Version1 Unit Test Conditions/Comments
LOGIC INPUTS
Input High Voltage, V
Input Low Voltage, V
Input Current, IIN ±1 µA max Typ 10 nA, VIN = 0 V or V
LOGIC OUTPUTS
Output High Voltage, VOH V
Output Low Voltage, VOL 0.4 V max I
Floating-State Leakage Current ±1 µA max
Floating-State Output Capacitance2 1 pF max
Output Coding Twos Complement Coding bit set to 0
Straight (Natural)
CONVERSION RATE
Conversion Time
Track-and-Hold Acquisition Time 800 ns max 16 SCLK cycles with SCLK at 20 MHz
300 ns max Sinewave input
300 ns max Full-scale step Input
Throughput Rate 200 kSPS max
POWER REQUIREMENTS
AVDD 2.7/5.25 V min/max
V
2.7/5.25 V min/max
DRIVE
IDD Digital I/Ps = 0 V or V
During Conversion 2.7 mA max AVDD = 4.75 V to 5.25 V, f
2.0 mA max AVDD = 2.7 V to 3.6 V, f
Normal Mode (Static) 600 µA typ AVDD = 2.7 V to 5.25 V, SCLK on or off
Normal Mode (Operational) f
1.2 mA max AVDD = 2.7 V to 3.6 V, f
Using Auto Shutdown Mode f
650 µA typ AVDD = 2.7 V to 3.6 V, f
Auto Shutdown (Static) 0.5 µA max SCLK on or off (20 nA typ)
Full Shutdown Mode 0.5 µA max SCLK on or off (20 nA typ)
Power Dissipation
Normal Mode (Operational) f
3.6 mW max AVDD = 3 V, f
0.7 × V
INH
0.3 × V
INL
2
IN
Binary
= 200 kSPS 1.5 mA max AVDD = 4.75 V to 5.25 V, f
SAMPLE
= 200 kSPS 900 µA typ AVDD = 4.75 V to 5.25 V, f
SAMPLE
= 200 kSPS 7.5 mW max AVDD = 5 V, f
SAMPLE
V min
DRIVE
V max
DRIVE
– 0.2 V min I
DRIVE
Coding bit set to 1
DRIVE
= 200 µA, AVDD = 2.7 V to 5.25 V
SOURCE
= 200 µA
SINK
DRIVE
SCLK
= 20 MHz
SCLK
SCLK
= 20 MHz
SCLK
SAMPLE
SAMPLE
= 20 MHz
SCLK
= 20 MHz
SCLK
= 20 MHz
= 20 MHz
= 200 kSPS
= 200 kSPS
1.5 µW max AVDD = 3 V
Full Shutdown Mode 2.5 µW max AVDD = 5 V
1.5 µW max AVDD = 3 V
1
Temperature range: EP Version: −55°C to +125°C.
2
Sample tested @ 25°C to ensure compliance.
Rev. 0 | Page 4 of 12
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