ANALOG DEVICES AD7921 Service Manual

2-Channel, 2.35 V to 5.25 V

V

V

www.BDTIC.com/ADI

FEATURES

Fast throughput rate: 250 kSPS
Specified for V
Low power:

4 mW typ at 250 kSPS with 3 V supplies

13.5 mW typ at 250 kSPS with 5 V supplies

Wide input bandwidth:

71 dB minimum SNR at 100 kHz input frequency
Flexible power/serial clock speed management
No pipeline delays
High speed serial interface:

SPI®/QSPI™/MICROWIRE™/DSP compatible
Standby mode: 1 µA maximum
8-lead TSOT package
8-lead MSOP package

APPLICATIONS

Battery-powered systems:

Personal digital assistants

Medical instruments

Mobile communications
Instrumentation and control systems
Data acquisition systems
High speed modems
Optical sensors

GENERAL DESCRIPTION

The AD7911/AD79211 are 10-bit and 12-bit, high speed, low
power, 2-channel successive approximation ADCs, respectively.
The parts operate from a single 2.35 V to 5.25 V power supply
and feature throughput rates of up to 250 kSPS. The parts
contain a low noise, wide bandwidth track-and-hold amplifier,
which can handle input frequencies in excess of 6 MHz. The
conversion process and data acquisition are controlled using
and the serial clock, allowing the devices to interface with
microprocessors or DSPs. The input signal is sampled on the
falling edge of
point. There are no pipeline delays associated with the part.

The channel to be converted is selected through the DIN pin,
and the mode of operation is controlled by
stream from the DOUT pin has a channel identifier bit, which
provides information about the converted channel.

1

Protected by U.S. Patent Number 6,681,332.

of 2.35 V to 5.25 V

DD

CS

, and the conversion is also initiated at this

CS

. The serial data

CS

250 kSPS, 10-/12-Bit ADCs

AD7911/AD7921

FUNCTIONAL BLOCK DIAGRAM

V

DD

IN0

IN1

AD7911/AD7921

MUX

T/H

The AD7911/AD7921 use advanced design techniques to
achieve very low power dissipation at high throughput rates.

The reference for the part is taken internally from V
allowing the widest dynamic input range to the ADC. The
analog input range for the part, therefore, is 0 to V
conversion rate is determined by the SCLK signal.

PRODUCT HIGHLIGHTS

1. 2-channel, 250 kSPS, 10-/12-bit ADCs in TSOT package.

2. Low power consumption.

3. Flexible power/serial clock speed management.

The conversion rate is determined by the serial clock;
conversion time is reduced when the serial clock speed is
increased. The parts also feature a power-down mode to
maximize power efficiency at lower throughput rates.
Average power consumption is reduced when the power­down mode is used while not converting. Current
consumption is 1 µA maximum and 50 nA typically when
in power-down mode.

4. Reference derived from the power supply.

5. No pipeline delay.

The parts feature a standard successive approximation
ADC with accurate control of the sampling instant via a
input and once-off conversion control.

10-/12-BIT

SUCCESSIVE

APPROXIMATION

ADC

CONTROL LOGIC

GND

Figure 1.

DD

DD

. The

SCLK
CS
DOUT
DIN

04350-0-001

, thereby

CS

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] © 2004 Analog Devices, Inc. All rights reserved.

AD7911/AD7921

www.BDTIC.com/ADI

TABLE OF CONTENTS

Specifications..................................................................................... 3

Analog Input............................................................................... 16

AD7911 Specifications................................................................. 3

AD7921 Specifications................................................................. 5

Timing Specifications ..................................................................7

Timing Diagrams.......................................................................... 7

Timing Examples.......................................................................... 8

Absolute Maximum Ratings............................................................ 9

ESD Caution.................................................................................. 9

Pin Configurations and Function Descriptions......................... 10

Terminology ....................................................................................11

Typical Performance Characteristics ...........................................13

Circuit Information........................................................................ 15

Converter Operation.................................................................. 15

ADC Transfer Function............................................................. 15

Typical Connection Diagram ................................................... 16

Digital Inputs.............................................................................. 17

DIN Input.................................................................................... 17

DOUT Output............................................................................ 17

Modes of Operation....................................................................... 18

Normal Mode.............................................................................. 18

Power-Down Mode.................................................................... 18

Power-Up Time .......................................................................... 19

Power vs. Throughput Rate....................................................... 20

Serial Interface ................................................................................21

Microprocessor Interfacing....................................................... 22

Application Hints ........................................................................... 24

Grounding and Layout .............................................................. 24

Outline Dimensions....................................................................... 25

Ordering Guide .......................................................................... 25

REVISION HISTORY

Revision 0: Initial Version

Rev. 0 | Page 2 of 28

AD7911/AD7921

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SPECIFICATIONS

AD7911 SPECIFICATIONS

Temperature range for A Grade from −40°C to +85°C.
V

= 2.35 V to 5.25 V, f

DD

Table 1.

Parameter A Grade1 Unit Test Conditions/Comments

DYNAMIC PERFORMANCE fIN = 100 kHz sine wave

Signal-to- Noise and Distortion (SINAD)2 61 dB min
Total Harmonic Distortion (THD)2 −71 dB max
Peak Harmonic or Spurious Noise (SFDR)2 −72 dB max
Intermodulation Distortion (IMD)2

Second-Order Terms −82 dB typ fa = 100.73 kHz, fb = 90.7 kHz

Third-Order Terms −83 dB typ fa = 100.73 kHz, fb = 90.7 kHz
Aperture Delay 10 ns typ
Aperture Jitter 30 ps typ
Channel-to-Channel Isolation2 −90 dB typ
Full Power Bandwidth 8.5 MHz typ @ 3 dB

1.5 MHz typ @ 0.1 dB
DC ACCURACY

Resolution 10 Bits
Integral Nonlinearity2 ±0.5 LSB max
Differential Nonlinearity2 ±0.5 LSB max Guaranteed no missed codes to 10 bits
Offset Error2 ±0.5 LSB max
Offset Error Match
Gain Error2 ±0.5 LSB max
Gain Error Match
Total Unadjusted Error (TUE)2 ±0.5 LSB max

ANALOG INPUT

Input Voltage Ranges 0 to VDD V
DC Leakage Current ±0.3 µA max
Input Capacitance 20 pF typ

LOGIC INPUTS

Input High Voltage, V
2 V min 2.7 V < VDD ≤ 5.25 V
Input Low Voltage, V

0.2 (VDD) V max 2.35 V < VDD ≤ 2.7 V

0.8 V max 2.7 V < VDD ≤ 5.25 V
Input Current, IIN, SCLK Pin ±0.3 µA max VIN = 0 V or V
Input Current, IIN, CS Pin

Input Current, IIN, DIN Pin ±0.3 µA max

Input Capacitance, CIN 5 pF max
LOGIC OUTPUTS

Output High Voltage, VOH V
Output Low Voltage, VOL 0.2 V max I
Floating-State Leakage Current ±0.3 µA max
Floating-State Output Capacitance3 5 pF max
Output Coding Straight (natural) binary

See notes at end of table.

2, 3

= 5 MHz, f

SCLK

2, 3

±0.3 LSB max

±0.3 LSB max

0.7 (VDD) V min 2.35 V ≤ VDD ≤ 2.7 V

INH

0.3 V max VDD = 2.35 V

INL

= 250 kSPS; TA = T

SAMPLE

±0.3 µA max

to T

MIN

− 0.2 V min I

DD

, unless otherwise noted.

MAX

= 200 µA, VDD = 2.35 V to 5.25 V

SOURCE

= 200 µA

SINK

DD

Rev. 0 | Page 3 of 28

AD7911/AD7921

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Parameter A Grade1 Unit Test Conditions/Comments

CONVERSION RATE

Conversion Time 2.8 µs max 14 SCLK cycles with SCLK at 5 MHz
Track-and-Hold Acquisition Time2 290 ns max
Throughput Rate 250 kSPS max

POWER REQUIREMENTS

VDD 2.35/5.25 V min/max
IDD Digital I/Ps = 0 V or VDD

Normal Mode (Static) 3 mA typ VDD = 4.75 V to 5.25 V, SCLK on or off

1.5 mA typ VDD = 2.35 V to 3.6 V, SCLK on or off
Normal Mode (Operational) 4 mA max VDD = 4.75 V to 5.25 V, f
2 mA max VDD = 2.35 V to 3.6 V, f
Full Power-Down Mode (Static) 1 µA max SCLK on or off, typically 50 nA
Full Power-Down Mode (Dynamic) 0.38 mA typ VDD = 5 V, f

0.2 mA typ VDD = 3 V, f

= 5 MHz, f

SCLK

= 5 MHz, f

SCLK

Power Dissipation4

Normal Mode (Operational) 20 mW max VDD = 5 V, f
6 mW max VDD = 3 V, f

= 250 kSPS

SAMPLE

= 250 kSPS

SAMPLE

Full Power-Down 5 µW max VDD = 5 V

1

Operational from VDD = 2 V, with VIH = 1.9 V minimum and VIL = 0.1 V maximum.

2

See the Terminology section.

3

Guaranteed by characterization.

4

See the Power vs. Throughput Rate section.

SAMPLE

SAMPLE

SAMPLE

SAMPLE

= 250 kSPS

= 250 kSPS

= 25 kSPS
= 25 kSPS

Rev. 0 | Page 4 of 28

AD7911/AD7921

www.BDTIC.com/ADI

AD7921 SPECIFICATIONS

Temperature range for A Grade from −40°C to +85°C.
V

= 2.35 V to 5.25 V, f

DD

Table 2.

Parameter A Grade1 Unit Test Conditions/Comments

DYNAMIC PERFORMANCE fIN = 100 kHz sine wave

Signal-to-Noise and Distortion (SINAD)2 70 dB min
72 dB typ
Signal-to-Noise Ratio (SNR)2 71 dB min

72.5 dB typ
Total Harmonic Distortion (THD)2 −81 dB typ
Peak Harmonic or Spurious Noise (SFDR)2 −84 dB typ
Intermodulation Distortion (IMD)2

Second-Order Terms −84 dB typ fa = 100.73 kHz, fb = 90.72 kHz

Third-Order Term −86 dB typ fa = 100.73 kHz, fb = 90.72 kHz
Aperture Delay 10 ns typ
Aperture Jitter 30 ps typ
Channel-to-Channel Isolation2 −90 dB typ
Full Power Bandwidth 8.5 MHz typ @ 3 dB

1.5 MHz typ @ 0.1 dB

DC ACCURACY

Resolution 12 Bits
Integral Nonlinearity2 ±1.5 LSB max
Differential Nonlinearity2 −0.9/+1.5 LSB max Guaranteed no missed codes to 12 bits
Offset Error2 ±1.5 LSB max
±0.5 LSB typ
Offset Error Match
Gain Error2 ± 2 LSB max
±0.3 LSB typ
Gain Error Match

2, 3

Total Unadjusted Error (TUE)2 ±1.5 LSB max

ANALOG INPUT

Input Voltage Ranges 0 to VDD V
DC Leakage Current ±0.3 µA max
Input Capacitance 20 pF typ

LOGIC INPUTS

Input High Voltage, V
2 V min 2.7 V < VDD ≤ 5.25 V
Input Low Voltage, V

0.2 (VDD) V max 2.35 V < VDD ≤ 2.7 V

0.8 V max 2.7 V < VDD ≤ 5.25 V
Input Current, IIN, SCLK Pin ±0.3 µA max VIN = 0 V or VDD

Input Current, IIN, CS Pin
Input Current, IIN, DIN Pin ±0.3 µA max
Input Capacitance, C

LOGIC OUTPUTS

Output High Voltage, VOH V
Output Low Voltage, V
Floating-State Leakage Current ±0.3 µA max
Floating-State Output Capacitance
Output Coding Straight (natural) binary

See notes at end of table.

= 5 MHz, f

SCLK

2, 3

±0.5 LSB max

= 250 kSPS; TA = T

SAMPLE

MIN

to T

, unless otherwise noted.

MAX

±1 LSB max

0.7 (VDD) V min 2.35 V ≤ VDD ≤ 2.7 V

INH

0.3 V max VDD = 2.35 V

INL

±0.3 µA max

3

5 pF max

IN

− 0.2 V min I

DD

0.2 V max I

OL

3

5 pF max

= 200 µA; VDD = 2.35 V to 5.25 V

SOURCE

= 200 µA

SINK

Rev. 0 | Page 5 of 28

AD7911/AD7921

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Parameter A Grade1 Unit Test Conditions/Comments

CONVERSION RATE

Conversion Time 3.2 µs max 16 SCLK cycles with SCLK at 5 MHz
Track-and-Hold Acquisition Time2 290 ns max
Throughput Rate 250 kSPS max See the Serial Interface section

POWER REQUIREMENTS

VDD 2.35/5.25 V min/max
IDD Digital I/Ps = 0 V or VDD

Normal Mode (Static) 3 mA typ VDD = 4.75 V to 5.25 V, SCLK on or off

1.5 mA typ VDD = 2.35 V to 3.6 V, SCLK on or off
Normal Mode (Operational) 4 mA max VDD = 4.75 V to 5.25 V, f
2 mA max VDD = 2.35 V to 3.6 V, f
Full Power-Down Mode (Static) 1 µA max SCLK on or off, typically 50 nA
Full Power-Down Mode (Dynamic) 0.4 mA typ VDD = 5 V, f

0.22 mA typ VDD = 3 V, f

= 5 MHz, f

SCLK

= 5 MHz, f

SCLK

Power Dissipation4

Normal Mode (Operational) 20 mW max VDD = 5 V, f
6 mW max VDD = 3 V, f

= 250 kSPS

SAMPLE

= 250 kSPS

SAMPLE

Full Power-Down 5 µW max VDD = 5 V

3 µW max VDD = 3 V

1

Operational from VDD = 2 V, with VIH = 1.9 V minimum and VIL = 0.1 V maximum.

2

See the Terminology section.

3

Guaranteed by characterization.

4

See the Power vs. Throughput Rate section.

SAMPLE

SAMPLE

SAMPLE

SAMPLE

= 250 kSPS

= 250 kSPS

= 25 kSPS
= 25 kSPS

Rev. 0 | Page 6 of 28

AD7911/AD7921

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TIMING SPECIFICATIONS

Guaranteed by characterization.
All input signals are specified with tr = tf = 5 ns (10% to 90% of V
V

= 2.35 V to 5.25 V; TA = T

DD

MIN

to T

, unless otherwise noted.

MAX

Table 3.

Parameter Limit at T

1

f

10 kHz min2

SCLK

MIN

, T

Unit Description

MAX

5 MHz max
t

16 × t

CONVERT

14 × t
t

30 ns min Minimum quiet time required between bus relinquish and start of next conversion

QUIET

t1 15 ns min
t2 10 ns min

3

t

30 ns max

3

3

t

45 ns max DOUT access time after SCLK falling edge

4

t5 0.4 t
t6 0.4 t

4

t

7

10 ns min SCLK to DOUT valid hold time

AD7921

SCLK

AD7911

SCLK

Minimum CS
CS

to SCLK setup time

Delay from CS

ns min SCLK low pulse width

SCLK

ns min SCLK high pulse width

SCLK

t8 5 ns min DIN setup time prior to SCLK falling edge
t9 6 ns min DIN hold time after SCLK falling edge

5

t

30 ns max SCLK falling edge to DOUT three-state

10

10 ns min SCLK falling edge to DOUT three-state

6

t

1 µs max Power-up time from full power-down

POWER-UP

1

Mark/space ratio for SCLK input is 40/60 to 60/40.

2

Minimum f

3

Measured with the load circuit in Figure 2 and defined as the time required for the output to cross VIH or VIL voltage.

4

Measured with a 50 pF load capacitor.

5

T10 is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit in Figure 2. The measured number is then extrapolated

back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t10, quoted in the timing characteristics is the true bus relinquish
time of the part and is independent of the bus loading.

6

See the Power-Up Time section.

at which specifications are guaranteed.

SCLK

) and timed from a voltage level of 1.6 V.

DD

pulse width

until DOUT three-state is disabled

TIMING DIAGRAMS

200µAI

TO OUTPUT

PIN

C

L

50pF

200µAI

Figure 2. Load Circuit for Digital Output Timing Specifications

t

4

SCLK

DOUT

Figure 3. Access Time after SCLK Falling Edge

OL

SCLK

1.6V

V

IH

DOUT

V

OH

04350-0-002

IL

Figure 4. Hold Time after SCLK Falling Edge

SCLK

V

IH

V

IL

04350-0-003

DOUT

Figure 5. SCLK Falling Edge to DOUT Three-State

Rev. 0 | Page 7 of 28

t

7

04350-0-004

t

10

1.6V

04350-0-005

AD7911/AD7921

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TIMING EXAMPLES

Figure 6 and Figure 7 show some of the timing parameters from
the Timing Specifications section.

Timing Example 1

As shown in Figure 7, when f
250 kSPS, the cycle time is

+ 12.5(1/f

t

2

SCLK

) + t

ACQ

= 5 MHz and the throughput is

SCLK

= 4 µs

Timing Example 2

The AD7921 can also operate with slower clock frequencies. As
shown in Figure 7, when f

= 2 MHz and the throughput rate

SCLK

is 100 KSPS, the cycle time is

t

+ 12.5(1/f

2

= 10 ns minimum, then t

With t

2

the requirement of 290 ns for t

SCLK

) + t

= 10 µs

ACQ

is 3.74 µs, which satisfies

ACQ

.

ACQ

= 10 ns minimum, then t

With t

2

the requirement of 290 ns for t

In Figure 7, t

t

= 30 ns maximum. This allows a value of 960 ns for t

10

is comprised of 2.5(1/f

ACQ

is 1.49 µs, which satisfies

ACQ

.

ACQ

) + t10 + t

SCLK

satisfying the minimum requirement of 30 ns.

CS

t

2

SCLK

DOUT

THREE-STATE

DIN

12345 13141516

t

3

ZERO

CHN X DB11 DB10 DB2 DB1 DB0Z

t

X

8

X CHN X X X X XX

Figure 6. AD7921 Serial Interface Timing Diagram

CS

t

SCLK

2

12345 13141516

12.5(1/f

In Figure 7, t
t

= 30 ns maximum. This allows a value of 2.46 µs for t

10

satisfying the minimum requirement of 30 ns.

, where

QUIET

QUIET

,

In this example, as with other slower clock values, the signal
might already be acquired before the conversion is complete,
but it is still necessary to leave 30 ns minimum t
conversions. In this example, the signal should be fully acquired
at approximately point C in Figure 7.

t

CONVERT

t

6

t

7

t

4

t

9

t

CONVERT

)

SCLK

1/THROUGHPUT

Figure 7. Serial Interface Timing Example

B

t

5

BC

is comprised of 2.5(1/f

ACQ

t

10

THREE-STATE

t

10

t

ACQUISITION

t

t

QUIET

QUIET

) + t10 + t

SCLK

t

1

QUIET

QUIET

04350-0-006

04350-0-007

, where

QUIET

between

,

Rev. 0 | Page 8 of 28

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ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted.

Table 4.

Parameter Rating

VDD to GND −0.3 V to +7 V
Analog Input Voltage to GND −0.3 V to VDD + 0.3 V
Digital Input Voltage to GND −0.3 V to +7 V
Digital Output Voltage to GND −0.3 V to VDD + 0.3 V
Input Current to Any Pin except Supplies1 ±10 mA
Operating Temperature Range

Commercial (A Grade) −40°C to +85°C

Storage Temperature Range −65°C to +150°C
Junction Temperature 150°C
TSOT Package

θJA Thermal Impedance 207°C/W

MSOP Package

θJA Thermal Impedance 205.9°C/W
θJC Thermal Impedance 43.74°C/W

Lead Temperature Soldering

Reflow (10 s to 30 s) 235 (0/+5)°C

ESD 2 kV

1

Transient currents of up to 100 mA do not cause SCR latch-up.

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or
any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.

Rev. 0 | Page 9 of 28