Analog Devices AD7895BR-2, AD7895BR-10, AD7895AR-3, AD7895AR-2, AD7895AN-3 Datasheet

5 V, 12-Bit, Serial 3.8 ms

SIGNAL

SCALING*

12-BIT

ADC

OUTPUT

REGISTER

TRACK/HOLD

AD7895

V

IN

CONVST

V

DD

GND

BUSY SCLK SDATA

REF IN

*AD7895-10, AD7895-3

a

FEATURES
Fast 12-Bit ADC with 3.8 ms Conversion Time
8-Pin Mini-DlP and SOIC
Single 5 V Supply Operation
High Speed, Easy-to-Use, Serial Interface
On-Chip Track/Hold Amplifier
Selection of Input Ranges

610 V for AD7895-10

62.5 V for AD7895-3

0 V to +2.5 V for AD7895-2
High Input Impedance
Low Power: 20 mW max
14-Bit Pin Compatible Upgrade (AD7894)

GENERAL DESCRIPTION

The AD7895 is a fast 12-bit ADC that operates from a single
+5 V supply and is housed in a small 8-pin mini-DIP and 8-pin
SOIC. The part contains a 3.8 µs successive approximation A/D
converter, an on-chip track/hold amplifier, an on-chip clock and
a high speed serial interface.

Output data from the AD7895 is provided via a high speed,
serial interface port. This two-wire serial interface has a serial
clock input and a serial data output with the external serial clock
accessing the serial data from the part.

In addition to the traditional dc accuracy specifications such as
linearity and full-scale and offset errors, the AD7895 is specified
for dynamic performance parameters, including harmonic
distortion and signal-to-noise ratio.

The part accepts an analog input range of ± 10 V (AD7895-10),
±2.5 V (AD7895-3), 0 V to 2.5 V (AD7895-2) and operates
from a single +5 V supply, consuming only 20 mW max.

The AD7895 features a high sampling rate mode and, for low
power applications, a proprietary automatic power-down mode
where the part automatically goes into power down once
conversion is complete and “wakes up” before the next conver­sion cycle.

The part is available in a small, 8-pin, 0.3" wide, plastic dual-in­line package (mini-DIP) and in an 8-pin, small outline IC (SOIC).

ADC in 8-Pin Package

AD7895

FUNCTIONAL BLOCK DIAGRAM

PRODUCT HIGHLIGHTS

1. Fast, 12-Bit ADC in 8-Pin Package

The AD7895 contains a 3.8 µs ADC, a track/hold amplifier,
control logic and a high speed serial interface, all in an 8-pin
package. This offers considerable space saving over alterna­tive solutions.

2. Low Power, Single Supply Operation
The AD7895 operates from a single +5 V supply and
consumes only 20 mW. The automatic power-down mode,
where the part goes into power-down once conversion is
complete and “wakes up” before the next conversion cycle,
makes the AD7895 ideal for battery-powered or portable
applications.

3. High Speed Serial Interface
The part provides high speed serial data and serial clock lines
allowing for an easy, two-wire serial interface arrangement.

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Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] World Wide Web Site: http://www.analog.com
Fax: [phone] © Analog Devices, Inc., 1996

(V

= +5 V, GND = 0 V, REF IN = +2.5 V.

DD

AD7895–SPECIFICATIONS

All specifications T

MIN

to T

unless otherwise noted)

MAX

Parameter A VersionslB Versions Units Test Conditions/Comments

DYNAMIC PERFORMANCE

Signal to (Noise + Distortion) Ratio

@ +25°C 70 70 dB min fIN = 50 kHz Sine Wave, f
T

to T

MIN

MAX

Total Harmonic Distortion (THD)3–78 –78 dB max fIN = 50 kHz Sine Wave, f

Peak Harmonic or Spurious Noise
Intermodulation Distortion (IMD)

2

3

= 200 kHz

SAMPLE

70 70 dB min

= 200 kHz,

3

–89 –89 dB typ fIN = 50 kHz Sine Wave, f

3

Typically –87 dB

fa = 9 kHz, fb = 9.5 kHz, f

SAMPLE

SAMPLE

SAMPLE

= 200 kHz

= 200 kHz
2nd Order Terms –87 –87 dB typ
3rd Order Terms –87 –87 dB typ

DC ACCURACY

Resolution 12 12 Bits
Minimum Resolution for which
No Missing Codes are Guaranteed 12 12 Bits
Relative Accuracy
Differential Nonlinearity
Positive Full-Scale Error

3

3

3

± 1 ±1 LSB max Typically 0.4 LSB
± 1 ±1 LSB max
± 3 ± 2 LSB max

AD7895-2

Unipolar Offset Error ±3 ±2 LSB max

AD7895-10, AD7895-3 Only

Negative Full-Scale Error

3

±3 ±2 LSB max

Bipolar Zero Error ±4 ±3 LSB max

ANALOG INPUT

AD7895-10

Input Voltage Range ±10 ±10 Volts
Input Resistance 24 24 kΩ min

AD7895-3

Input Voltage Range ±2.5 ±2.5 Volts
Input Resistance 9 9 kΩ min

AD7895-2

Input Voltage Range 0 to +2.5 0 to +2.5 Volts
Input Current 500 500 nA max

REFERENCE INPUT

REF IN Input Voltage Range 2.375/2.625 2.375/2.625 V min/V max 2.5 V ± 5%
Input Current 1 1 µA max
Input Capacitance

3

10 10 pF max

LOGIC INPUTS

Input High Voltage, V
Input Low Voltage, V
Input Current, I
Input Capacitance, C

IN

IN

INH

INL

4

2.4 2.4 V min VDD = 5 V ± 5%

0.8 0.8 V max V

= 5 V ± 5%

DD

±10 ±10 µA max VIN = 0 V to V
10 10 pF ax

DD

LOGIC OUTPUTS

Output High Voltage, V
Output Low Voltage, V

OL

OH

4.0 4.0 V min I

0.4 0.4 V max I

SOURCE

= 1.6 mA

SINK

= 200 µA

Output Coding
AD7895-10, AD7895-3 2s Complement
AD7895-2 Straight (Natural) Binary

CONVERSION RATE

Conversion Time
Mode 1 Operation 3.8 3.8 µs max
Mode 2 Operation
Track/Hold Acquisition Time

5

3

9.8 9.8 µs max

0.5 0.5 µs max

POWER REQUIREMENTS

V

DD

I

DD

+5 +5 V nom ±5% for Specified Performance
4 4 mA max Digital Inputs @ VDD, VDD = 5 V ± 5%

Power Dissipation 20 20 mW max Typically 16 mW

Power-Down Mode

IDD @ +25°C55µA max Digital Inputs @ GND, VDD = 5 V ± 5%
T

MIN

to T

MAX

10 10 µA max Digital Inputs @ GND, VDD = 5 V ± 5%

Power Dissipation @ +25°C2525 µW max

NOTES

1

Temperature ranges are as follows: A, B Versions: –40°C to +85°C.

2

Applies to Mode 1 operation. See section on “Operating Modes.”

3

See Terminology.

4

Sample tested @ +25°C to ensure compliance.

5

This 9.8 µs includes the “wake-up” time from standby. This “wake-up” time is timed from the rising edge of CONVST, whereas conversion is timed from the falling edge of CONVST, for

CONVST pulse width the conversion time is effectively the “wake-up” time plus conversion time hence 9.8 µs. This can be seen from Figure 3. Note that if the CONVST pulse width

narrow
is greater than 6 µs then the effective conversion time will increase beyond 9.8 µs.

Specifications subject to change without notice.

–2–

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AD7895

WARNING!

ESD SENSITIVE DEVICE

+1.6V

2.0mA

2.0mA

50pF

TO

OUTPUT

PIN

1, 2

TIMING CHARACTERISTICS

Parameter A, B Versions Units Test Conditions/Comments

t

1

t

2

t

3

t

4

t

5

t

6

NOTES

1

Sample tested at +25°C to ensure compliance. All input signals are measured with tr = tf = 1 ns (10% to 90% of +5 V) and timed from a voltage level of +1.4 V.

2

The SCLK maximum frequency is 15 MHz. Care must be taken when interfacing to account for the data access time, t

processor. These two times will determine the maximum SCLK frequency that the user’s system can operate with. See “Serial Interface” section for more information.

3

Measured with the load circuit of Figure 1 and defined as the time required for an output to cross 0.8 V or 2.0 V.

4

Derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapolated back
to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t6, quoted in the timing characteristics is the true bus relinquish time
of the part and, as such, is independent of external bus loading capacitances.

40 ns min CONVST Pulse Width

2

35

2

35

3

60
10 ns min Data Hold Time after Falling Edge of SCLK

4

50

(VDD = +5 V, GND = 0 V, REF IN = +2.5 V)

ns min SCLK High Pulse Width
ns min SCLK Low Pulse Width
ns max Data Access Time after Falling Edge of SCLK, VDD = 5 V ± 5%

ns max Bus Relinquish Time after Falling Edge of SCLK

, and the setup time required for the user's

4

ABSOLUTE MAXIMUM RATINGS*

(TA = +25°C unless otherwise noted)

VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V

Analog Input Voltage to GND

*Stresses above those listed under “Absolute Maximum Ratings” may cause

permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those listed in the
operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.

AD7895-10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±17 V

AD7895-2, AD7895-3 . . . . . . . . . . . . . . . . . . . –5 V, +10 V

Reference Input Voltage to GND . . . . –0.3 V to V

Digital Input Voltage to GND . . . . . . . –0.3 V to V

Digital Output Voltage to GND . . . . . –0.3 V to V

+ 0.3 V

DD

+ 0.3 V

DD

+ 0.3 V

DD

Operating Temperature Range

Commercial (A, B Versions) . . . . . . . . . . . –40°C to +85°C

Storage Temperature Range . . . . . . . . . . . –65°C to +150°C

Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . +150°C

Plastic DIP Package, Power Dissipation . . . . . . . . . . 450 mW

θ

Thermal Impedance . . . . . . . . . . . . . . . . . . . . 130°C/W

JA

Lead Temperature (Soldering, 10 sec) . . . . . . . . . . +260°C

SOIC Package, Power Dissipation . . . . . . . . . . . . . . . 450 mW

θ

Thermal Impedance . . . . . . . . . . . . . . . . . . . . 170°C/W

JA

Figure 1. Load Circuit for Access Time and Bus
Relinquish Time

Lead Temperature, Soldering

Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . +215°C

Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . .+220°C

ORDERING GUIDE

Model Temperature Range Linearity Error (LSB) SNR (dB) Package Option*

AD7895AN-2 –40°C to +85°C ±1 LSB 70 dB N-8
AD7895AR-2 –40°C to +85°C ±1 LSB 70 dB SO-8
AD7895BR-2 –40°C to +85°C ± 1 LSB 70 dB SO-8

AD7895AN-10 –40°C to +85°C ±1 LSB 70 dB N-8
AD7895AR-10 –40°C to +85°C ±1 LSB 70 dB SO-8
AD7895BR-10 –40°C to +85°C ±1 LSB 70 dB SO-8

AD7895AN-3 –40°C to +125°C ±1 LSB 70 dB N-8
AD7895AR-3 –40°C to +85°C ±1 LSB 70 dB SO-8

*N = Plastic DIP, SO = SOIC.

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD7895 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.

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–3–

AD7895

PIN FUNCTION DESCRIPTION

Pin Pin
No. Mnemonic Description

1 REF IN Voltage Reference Input. An external reference source should be connected to this pin to provide the refer-

ence voltage for the AD7895’s conversion process. The REF IN input is buffered on chip. The nominal ref­erence voltage for correct operation of the AD7895 is +2.5 V.

2V

IN

3 GND Analog Ground. Ground reference for track/hold, comparator, digital circuitry and DAC.
4 SCLK Serial Clock Input. An external serial clock is applied to this input to obtain serial data from the AD7895.

5 SDATA Serial Data Output. Serial data from the AD7895 is provided at this output. The serial data is clocked out

6 BUSY The BUSY pin is used to indicate when the part is doing a conversion. The BUSY pin will go high on the

7

8V

CONVST Convert Start. Edge-triggered logic input. On the falling edge of this input, the track/hold goes into its hold

DD

Analog Input Channel. The analog input range is ± 10 V (AD7895-10), ±2.5 V (AD7895-3) and 0 V to
+2.5 V (AD7895-2).

A new serial data bit is clocked out on the falling edge of this serial clock. Data is guaranteed valid for 10 ns
after this falling edge so that data can be accepted on the falling edge when a fast serial clock is used. The
serial clock input should be taken low at the end of the serial data transmission.

by the falling edge of SCLK, but the data can also be read on the falling edge of SCLK. This is possible
because data bit N is valid for a specified time after the falling edge of SCLK (data hold time) (see Figure 4).
Sixteen bits of serial data are provided with four leading zeros followed by the 12 bits of conversion data.
On the sixteenth falling edge of SCLK, the SDATA line is held for the data hold time and then is disabled
(three-stated). Output data coding is 2s complement for the AD7895-10, AD7895-3 and straight binary for
the AD7895-2.

falling edge of

mode, and conversion is initiated. If
down mode. In this case, the rising edge of

CONVST and will return low when the conversion is complete.

CONVST is low at the end of conversion, the part goes into power-

CONVST “wakes up” the part.

Positive supply voltage, +5 V ± 5%.

PIN CONFIGURATION

DIP and SOIC

REF IN

V

GND

SCLK

1
2

IN

3
4

AD7895

TOP VIEW

(Not to Scale)

8
7
6
5

V

DD

CONVST

BUSY
SDATA

–4–

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