Analog Devices AD7880CR, AD7880CQ, AD7880CN, AD7880BR, AD7880BQ Datasheet

LC2MOS Single +5 V Supply,

+
–

R

R

SAMPLING

COMPARATOR

CONTROL

LOGIC

SAR +

COUNTER

CLKIN

CS

CONVST

RD

BUSY

MODE

V

DD

LOW POWER

CONTROL

CIRCUIT

V

INA

V

INB

V

REF

AGND

DGND

DB0DB11

12-BIT DAC

AD7880

THREE
STATE

BUFFERS

a

Low Power, 12-Bit Sampling ADC

AD7880

FEATURES
12-Bit Monolithic A/D Converter
66 kHz Throughput Rate

12 ms Conversion Time
3 ms On-Chip Track/Hold Amplifier

Low Power

Power Save Mode: 2 mW typ

Normal Operation: 25 mW typ
70 dB SNR
Fast Data Access Time: 57 ns
Small 24-Lead SOIC and 0.3" DIP Packages

APPLICATIONS
Battery Powered Portable Systems
Digital Signal Processing
Speech Recognition and Synthesis
High Speed Modems
Control and Instrumentation

GENERAL DESCRIPTION

The AD7880 is a high speed, low power, 12-bit A/D converter
which operates from a single +5 V supply. It consists of a 3µs
track/hold amplifier, a 12 µs successive-approximation ADC,
versatile interface logic and a multiple-input-range circuit. The
part also includes a power save feature.

An internal resistor network allows the part to accept both uni­polar and bipolar input signals while operating from a single
+5 V supply. Fast bus access times and standard control inputs
ensure easy interfacing to modern microprocessors and digital
signal processors.

The AD7880 features a total throughput time of 15 µs and can
convert full power signals up to 33 kHz with a sampling fre­quency of 66 kHz.

PRODUCT HIGHLIGHTS

1. Fast Conversion Time.
12 µs conversion time and 3 µs acquisition time allow for
large input signal bandwidth. This performance is ideally
suited for applications in areas such as telecommunications,
audio, sonar and radar signal processing.

2. Low Power Consumption.
2 mW power consumption in the power-down mode makes
the part ideally suited for portable, hand held, battery pow­ered applications.

3. Multiple Input Ranges.
The part features three user-determined input ranges, 0 V to
+5 V, 0 V to 10 V and ± 5 V. These unipolar and bipolar
ranges are achieved with a 5 V only power supply.

In addition to the traditional dc accuracy specifications such as
linearity, full-scale and offset errors, the AD7880 is also fully
specified for dynamic performance parameters including har­monic distortion and signal-to-noise ratio.

The AD7880 is fabricated in Analog Devices’ Linear Compat­ible CMOS (LC

2

MOS) process, a mixed technology process
that combines precision bipolar circuits with low power CMOS
logic. The part is available in a 24-pin, 0.3 inch-wide, plastic or
hermetic dual-in-line package (DIP) as well as a small 24-lead
SOIC package.

REV. 0

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] Fax: [phone]

FUNCTIONAL BLOCK DIAGRAM

AD7880–SPECIFICA TIONS

(VDD = +5 V 6 5%, V
unless otherwise noted. All Specifications T

= VDD, AGND = DGND = O V, f

REF

MIN

= 2.5 MHz, MODE = V

CLKIN

to T

unless otherwise noted.)

MAX

Parameter B Versions1C Versions1Units Test Conditions/Comments

DYNAMIC PERFORMANCE

2

Signal-to-Noise Ratio3 (SNR) 70 70 dB min Typically SNR Is 72 dB

Total Harmonic Distortion (THD) –80 –80 dB typ VIN = 1 kHz Sine Wave, f

VIN = 1 kHz Sine Wave, f

Peak Harmonic or Spurious Noise –80 –80 dB typ VIN = 1 kHz, f

SAMPLE

= 66 kHz

SAMPLE
SAMPLE

= 66 kHz
= 66 kHz

Intermodulation Distortion (IMD)

Second Order Terms –80 –80 dB typ fa = 0.983 kHz, fb = 1.05 kHz, f
Third Order Terms –80 –80 dB typ fa = 0.983 kHz, fb = 1.05 kHz, f

SAMPLE
SAMPLE

= 66 kHz
= 66 kHz

DC ACCURACY

Resolution 12 12 Bits All DC ACCURACY Specifications Apply for

the Three Analog Input Ranges
Integral Nonlinearity ± 1 ±1 LSB max
Differential Nonlinearity ± 1 ±1 LSB max Guaranteed Monotonic
Full-Scale Error ± 15 ± 5 LSB max
Bipolar Zero Error ±10 ±5 LSB max
Unipolar Offset Error ±5 ±5 LSB max

ANALOG INPUT

Input Voltage Ranges 0 to V

REF

0 to 2 V
±V

REF

Input Resistance 10 10 MΩ min 0 to V

5/12 5/12 kΩ min/max 8 kΩ typical: 0 to 2 V
5/12 5/12 kΩ min/max 8 kΩ typical: ± V

REF

0 to V

REF

0 to 2 V
±V

REF

Volts See Figure 5
Volts See Figure 6

REF

Volts See Figure 7

REF

Range

REF

Range

REF

Range

REFERENCE INPUT

V

(For Specified Performance) 5 5 V ±5%: Normally V

REF

I

REF

Nominal Reference Range 2.5/V

1.5 1.5 mA max

DD

2.5/V

DD

V min/max See Figure 3 for Degradation in Performance Down to 2.5 V

= VDD (See Reference Input Section)

REF

LOGIC INPUTS

CONVST, RD, CS, CLKIN

Input High Voltage, V
Input Low Voltage, V
Input Current, I

IN

Input Capacitance, C

INL

IN

INH

4

2.4 2.4 V min

0.8 0.8 V max
±10 ±10 µA max VIN = 0 V or V
10 10 pF max

DD

MODE INPUT

Input High Voltage, V
Input Low Voltage, V
Input Current, I

IN

Input Capacitance, C

INL

IN

INH

4

4 4 V min
1 1 V max
±125 ±125 µA max VIN = 0 V or V
10 10 pF max

DD

LOGIC OUTPUTS

DB11–DB0, BUSY

Output High Voltage, V
Output Low Voltage, V

OH

OL

4.0 4.0 V min I

0.4 0.4 V max I

SOURCE

= 1.6 mA

SINK

= 400 µA

DB11–DB0

Floating-State Leakage Current ±10 ±10 µA max
Floating-State Output Capacitance410 10 pF max

CONVERSION

Conversion Time 12 12 µs max f

CLKIN

= 2.5 MHz

Track/Hold Acquisition Time 3 3 µs max

POWER REQUIREMENTS

V

DD

I

DD

Normal Power Mode @ +25°C 7.5 7.5 mA max Typically 4 mA; MODE = V

T

to T

MIN

MAX

+5 +5 V nom ± 5% for Specified Performance

10 10 mA max Typically 5 mA; MODE = V

DD
DD

Power Save Mode @ +25°C 750 750 µA max Logic Inputs @ 0 V or VDD; MODE = 0 V

T

MIN

to T

MAX

1 1 mA max Logic Inputs @ 0 V or VDD; MODE = 0 V

Power Dissipation

Normal Power Mode @ +25°C 37.5 37.5 mW max VDD = 5 V: Typically 20 mW; MODE = V

T

MIN

to T

MAX

50 50 mW max VDD = 5 V: Typically 25 mW; MODE = V

Power Save Mode @ +25°C 3.75 3.75 mW max VDD = 5 V: Typically 2 mW; MODE = 0 V

T

to T

MIN

MAX

NOTES

1

Temperature ranges are as follows: B/C Versions, –40°C to +85°C.

2

VIN = 0 to V

3

SNR calculation includes distortion and noise components.

4

Sample tested @ +25°C to ensure compliance.

REF

5 5 mW max VDD = 5 V: Typically 2.5 mW; MODE = 0 V

Specifications subject to change without notice.

–2–

DD

DD
DD

REV. 0

TIMING CHARACTERISTICS

1

(VDD = +5 V 6 5%, V

= VDD, AGND = DGND = 0 V)

REF

AD7880

Limit at +258C Limit at T

MIN

, T

MAX

Parameter (All Versions) (All Versions) Units Conditions/Comments

t

1

t

2

t

3

t

4

t

5

t

6

2

t

7

3

t

8

50 50 ns min CONVST Pulse Width
130 130 ns min CONVST to BUSY Falling Edge
0 0 ns min BUSY to CS Setup Time
0 0 ns min CS to RD Setup Time
0 0 ns min CS to RD Hold Time

60 75 ns min RD Pulse Width
57 70 ns max Data Access Time after RD
55 ns min Bus Relinquish Time after RD

50 50 ns max

NOTES

1

Timing specifications in bold print are 100% production tested. All other times are sample tested at +25°C to ensure compliance. All input signals are specified with

tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V.

2

t7 is measured with the load circuit of Figure 2 and defined as the time required for an output to cross 0.8 V or 2.4 V.

3

t8 is derived from the measured time taken by the data outputs to change by 0.5 V when loaded with the circuit of Figure 2. The measured number is then extrapo-

lated back to remove the effects of charging the 50 pF capacitor. This means that the time, t8, quoted in the timing characteristics is the true bus relinquish time of
the part and as such is independent of external bus loading capacitances.

t

CONVST

BUSY

CS

RD

DB0 – DB11

1

TRACK/HOLD
GOES INTO HOLD

t

2

t

CONVERT

THREE-STATE

Figure 1. Timing Diagram

1.6mA

CS CONVST RD Function

1 1 X Not Selected

t

3

1 j 1 Start Conversion g
0 1 0 Enable ADC Data
0 1 1 Data Bus Three Stated

t

t

4

5

t

6

ABSOLUTE MAXIMUM RATINGS*

VDD to AGND . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V

t

t

8

7

DATA

VALID

V

to DGND . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V

DD

AGND to DGND . . . . . . . . . . . . . . . . . –0.3 V to V

V

, V

INA

V

INA

V

INA

V

REF

to AGND (Figure 5) . . . . . . –0.3 V to VDD + 0.3 V

INB

to AGND (Figure 6) . . . . . . . . . –0.6 V to 2 VDD + 0.6 V

to AGND (Figure 7) . . . . . –VDD – 0.3 V to V

to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . 0.3 V to V

Digital Inputs to DGND . . . . . . . . . . . –0.3 V to VDD + 0.3 V

Digital Outputs to DGND . . . . . . . . . . –0.3 V to V

Table I. Truth Table

+ 0.3 V

DD

+ 0.3 V

DD

+ 0.3 V

DD

DD

Operating Temperature Range

TO OUTPUT

PIN

50pF

200µA

2.1V+

Figure 2. Load Circuit for Access and Relinquish Time

Industrial (B, C Versions) . . . . . . . . . . . . . –40°C to +85°C

Storage Temperature Range . . . . . . . . . . . –65°C to +150°C

Lead Temperature (Soldering, 10 secs) . . . . . . . . . . . . +300°C

Power Dissipation (Any Package) to +75°C . . . . . . . . 450 mW

Derates above +75°C by . . . . . . . . . . . . . . . . . . . . . 10 mW/°C

*Stresses above those listed under “Absolute Maximum Ratings” may cause

permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those listed in the
operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD7880 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.

REV. 0

–3–

WARNING!

ESD SENSITIVE DEVICE

AD7880

TOP VIEW

(Not to Scale)

1
2
3
4
5

6
7
8
9

10

11
12

13

14

24

23
22
21
20

19

18
17

16
15

AD7880

AGND

CLKIN
DGND

DB0
DB1 DB2

DB3

DB4

DB5

DB6

V

DD

DB8

V

INA

V

INB

DB7

DB9

DB10

DB11

MODE

CS

CONVST

RD

BUSY

V

REF

ORDERING GUIDE

PIN CONFIGURATION

Bipolar

Full-Scale Zero

Temperature Error Error Package

Model Range (LSBs) (LSBs) Option*

AD7880BN –40°C to +85°C ±15 ±10 N-24
AD7880BQ –40°C to +85°C ±15 ±10 Q-24
AD7880CN –40°C to +85°C ±5 ±5 N-24
AD7880CQ –40°C to +85°C ±5 ±5 Q-24
AD7880BR –40°C to +85 °C ±15 ±10 R-24
AD7880CR –40°C to +85°C ±5 ±5 R-24

*N = Plastic DIP; Q = Cerdip; R = SOIC (Small Outline Integrated Circuit).

PIN FUNCTION DESCRIPTION

Pin Pin
No. Mnemonic Function

1V
2V

INA
INB

Analog Input.

Analog Input.
3 AGND Analog Ground.
4V
5
6

7
8

REF

CS Chip Select. Active Low Logic input. The device is selected when this input is active.
CONVST Convert Start. A low to high transition on this input puts the track/hold into hold mode and starts con-

RD Read. Active Low Logic Input. This input is used in conjunction with CS low to enable data outputs.
BUSY Active Low Logic Output. This status line indicates converter status. BUSY is low during conversion.

Voltage Reference Input. This is normally tied to VDD.

version. This input is asynchronous to the CLKIN and is independent of

CS and RD.

9 CLKIN Clock Input. TTL-compatible logic input. Used as the clock source for the A/D converter. The mark/

space ratio of the clock can vary from 40/60 to 60/40.

10 DGND Digital Ground.
11 . . . 22 DB0–DB11 Three-State Data Outputs. These become active when

CS and RD are brought low.

23 MODE MODE Input. This input is used to put the device into the power save mode (MODE = 0 V). During

24 V

DD

normal operation, the MODE input will be a logic high (MODE = V

Power Supply. This is nominally +5 V.

DD

).

–4–

REV. 0

AD7880

+
–

R

R

SAMPLING
COMPARATOR

V

INA

V

INB

V

REF

AGND

12-BIT DAC

0 TO V

REF

V

REF

= 0 TO 2V

REF

V

IN

CIRCUIT INFORMATION

The AD7880 is a +5 V single supply 12-bit A/D converter. The
part requires no external components apart from a 2.5 MHz ex­ternal clock and power supply decoupling capacitors. It contains
a 12-bit successive approximation ADC based on a fast-settling
voltage-output DAC, a high speed comparator and SAR, as well
as the necessary control logic. The charge balancing comparator
used in the AD7880 provides the user with an inherent track­and-hold function. The ADC is specified to work with sampling
rates up to 66 kHz.

CONVERTER DETAILS

The AD7880 conversion cycle is initiated on the rising edge of
the CONVST pulse, as shown in the timing diagram of Figure

1. The rising edge of the

CONVST pulse places the track/hold
amplifier into “HOLD” mode. The conversion cycle then takes
between 26 and 28 clock periods. The maximum specified con­version time is 12 µs. This corresponds to a conversion cycle
time of 28 clock periods with a CLKIN frequency of 2.5 MHz
and also includes internal propagation delays. During conver­sion the

BUSY output will remain low, and the output databus
drivers will be three-stated. When a conversion is completed,
the

BUSY output will go to a high level, and the result of the

conversion can be read by bringing

CS and RD low.

The track/hold amplifier acquires a 12-bit input signal in 3µs.
The overall throughput time for the AD7880 is equal to the
conversion time plus the track/hold acquisition time. For a

2.5 MHz input clock the throughput time is 15 µs.

REFERENCE INPUT

For specified performance, it is recommended that the reference
input be tied to V

. The part, however, will operate with a ref-

DD

erence down to 2.5 V though with reduced performance specifi­cations. Figure 3 shows a graph of signal-to-noise ratio (SNR)
versus V

V

REF

.

REF

must not be allowed to go above VDD by more than

100 mV.

74

F = 51.2kHz

S

72

F = 2.525kHz

IN

T = 25 C

A

70

V

INA

+

R

V

INB

R

–

V

DAC

Figure 4. AD7880 Input Circuit

The AD7880 accommodates three separate input ranges, 0 to
V

, 0 to 2 V

REF

REF

and ±V

. The input configurations corre-

REF

sponding to these ranges are shown in Figures 5, 6 and 7.
With V

= VDD and using a nominal VDD of +5 V, the input

REF

ranges are 0 V to 5 V, 0 V to 10 V and +5 V, as shown in
Table II.

Table II. Analog Input Ranges

Analog Input
Range V

0 V to +5 V V
0 V to +10 V V
±5 V V

= 0 TO V

V

IN

REF

V

REF

Figure 5. 0 to V

Input Connections
V

REF

DD
DD
DD

INA

V

IN

V

IN

V

IN

R

V

INA

R

V

INB

V

REF

AGND

Unipolar Input Configuration

REF

V

INB

V

IN

AGND Figure 6
V

REF

0 TO V

12-BIT DAC

Connection
Diagram

Figure 5
Figure 7

SAMPLING
COMPARATOR

REF

+
–

68

– dBs

66

SNR

64

62

60

2345

Figure 3. SNR vs. V

ANALOG INPUT

The AD7880 has two analog input pins, V
4 shows the input circuitry to the ADC sampling comparator.
The on-board attenuator network, made up of equal resistors,
allows for various input ranges.

REV. 0

V

REF

– Volts

REF

INA

and V

INB

. Figure

–5–

Figure 6. 0 to 2 V

±

= V

V

REF

IN

V

REF

Figure 7.±V

V

INA

V

INB

V

REF

AGND

REF

Unipolar Input Configuration

REF

0 TO V

REF

12-BIT DAC

SAMPLING
COMPARATOR

+
–

R

R

Bipolar Input Configuration