Analog Devices AD7875, AD7876, AD7870 Datasheet

LC2MOS

a

FEATURES
Complete Monolithic 12-Bit ADC with:

2 ms Track/Hold Amplifier
8 ms A/D Converter
On-Chip Reference
Laser-Trimmed Clock
Parallel, Byte and Serial Digital Interface

72 dB SNR at 10 kHz Input Frequency

(AD7870, AD7875)
57 ns Data Access Time
Low Power: –60 mW typ
Variety of Input Ranges:

63 V for AD7870

0 V to +5 V for AD7875

610 V for AD7876

GENERAL DESCRIPTION

The AD7870/AD7875/AD7876 is a fast, complete, 12-bit A/D
converter. It consists of a track/hold amplifier, 8 µs successive-
approximation ADC, 3 V buried Zener reference and versatile
interface logic. The ADC features a self-contained internal
clock which is laser trimmed to guarantee accurate control of
conversion time. No external clock timing components are re­quired; the on-chip clock may he overridden by an external
clock if required.

The parts offer a choice of three data output formats: a single,
parallel, 12-bit word; two 8-bit bytes or serial data. Fast bus ac­cess times and standard control inputs ensure easy interfacing to
modern microprocessors and digital signal processors.

All parts operate from ±5 V power supplies. The AD7870 and
AD7876 accept input signal ranges of ± 3 V and ±10 V, respec­tively, while the AD7875 accepts a unipolar 0 V to +5 V input
range. The parts can convert full power signals up to 50 kHz.

The AD7870/AD7875/AD7876 feature dc accuracy specifica­tions such as linearity, full-scale and offset error. In addition,
the AD7870 and AD7875 are fully specified for dynamic perfor­mance parameters including distortion and signal-to-noise ratio.

The parts are available in a 24-pin, 0.3 inch-wide, plastic or her­metic dual-in-line package (DIP). The AD7870 and AD7875
are available in a 28-pin plastic leaded chip carrier (PLCC),
while the AD7876 is available and in a 24-pin small outline
(SOIC) package.

Complete, 12-Bit, 100 kHz, Sampling ADCs

AD7870/AD7875/AD7876

FUNCTIONAL BLOCK DIAGRAM

PRODUCT HIGHLIGHTS

1. Complete 12-Bit ADC on a Chip.
The AD7870/AD7875/AD7876 provides all the functions
necessary for analog-to-digital conversion and combines a
12-bit ADC with internal clock, track/hold amplifier and
reference on a single chip.

2. Dynamic Specifications for DSP Users.
The AD7870 and AD7875 are fully specified and tested for
ac parameters, including signal-to-noise ratio, harmonic dis­tortion and intermodulation distortion.

3. Fast Microprocessor Interface.
Data access times of 57 ns make the parts compatible with
modern 8- and 16-bit microprocessors and digital signal pro­cessors. Key digital timing parameters are tested and guaran­teed over the full operating temperature range.

REV. B

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] World Wide Web Site: http://www.analog.com
Fax: [phone] © Analog Devices, Inc., 1997

AD7870/AD7875/AD7876–SPECIFICATIONS

A6ND = DGND = 0 V, f

Parameter J, AlK, BlL, ClS

DYNAMIC PERFORMANCE

= 2.5 MHz external, unless otherwise stated. All Specifications T

CLK

AD7870

2

l

l

T

(VDD = +5 V 6 5%, VSS = –5 V 6 5%,

to T

min

Units Test Conditions/Comments

unless otherwise noted.)

max

Signal to Noise Ratio3 (SNR)

@ +25°C 70 70 72 69 69 dB min V
T

MIN

to T

MAX

70 70 71 69 69 dB min Typically 71.5 dB for 0 < V

Total Harmonic Distortion (THD) –80 –80 –80 –78 –78 dB max V

= 10 kHz Sine Wave, f

IN

= 10 kHz Sine Wave, f

IN

SAMPLE

< 50 kHz

IN

SAMPLE

= 100 kHz

= 100 kHz

Typically –86 dB for 0 < VIN < 50 kHz

Peak Harmonic or Spurious Noise –80 –80 –80 –78 –78 dB max VIN = 10 kHz, f

Typically –86 dB for 0 < V

SAMPLE

= 100 kHz

< 50 kHz

IN

Intermodulation Distortion (IMD)

Second Order Terms –80 –80 –80 –78 –78 dB max fa = 9 kHz, fb = 9.5 kHz, f
Third Order Terms –80 –80 –80 –78 –78 dB max fa = 9 kHz, fb = 9.5 kHz, f

SAMPLE
SAMPLE

= 50 kHz
= 50 kHz

Track/Hold Acquisition Time 2 2 2 2 2 µs max

DC ACCURACY

Resolution 12 12 12 12 12 Bits
Minimum Resolution for which

No Missing Codes are Guaranteed 12 12 12 12 12 Bits
Integral Nonlinearity ± 1/2 ± 1/2 ±1/4 ± 1/2 ± 1/2 LSB typ
Integral Nonlinearity ± 1 ±1/2 ±1 LSB max
Differential Nonlinearity ± 1 ±1 ±1 LSB max
Bipolar Zero Error ±5 ±5 ±5 ±5 ±5 LSB max
Positive Full-Scale Error
Negative Full-Scale Error

4

4

± 5 ±5 ±5 ±5 ±5 LSB max
±5 ±5 ±5 ±5 ±5 LSB max

ANALOG INPUT

Input Voltage Range ±3 ±3 ±3 ±3 ±3 Volts
Input Current ± 500 ± 500 ± 500 ± 500 ± 500 µA max

REFERENCE OUTPUT

REF OUT @ +25°C 2.99 2.99 2.99 2.99 2.99 V min

3.01 3.01 3.01 3.01 3.01 V max
REF OUT Tempco ±60 ±60 ±35 ±60 ±35 ppm/°C max
Reference Load Sensitivity (∆REF OUT/∆I) ±1 ±1 ±1 ±1 ±1 mV max Reference Load Current Change (0–500 µA)

Reference Load Should Not Be Changed
During Conversion.

LOGIC INPUTS

Input High Voltage, V
Input Low Voltage, V
Input Current, I
Input Current (12/8/CLK Input Only) ±10 ±10 ±10 ±10 ±10 µA max VIN = VSS to V
Input Capacitance, C

INH

INL

IN

5

IN

2.4 2.4 2.4 2.4 2.4 V min VDD = 5 V ± 5%

0.8 0.8 0.8 0.8 0.8 V max VDD = 5 V ± 5%

±10 ±10 ±10 ±10 ±10 µA max VIN = 0 V to V

10 10 10 10 10 pF max

DD
DD

LOGIC OUTPUTS

Output High Voltage, V
Output Low Voltage, V

OL

OH

4.0 4.0 4.0 4.0 4.0 V min I

0.4 0.4 0.4 0.4 0.4 V max I

SOURCE

= 1.6 mA

SINK

= 40 µA

DB11–DB0

Floating-State Leakage Current ± 10 ±10 ±10 ± 10 ±10 µA max
Floating-State Output Capacitance

5

15 15 15 15 15 pF max

CONVERSION TIME

External Clock (f

= 2.5 MHz) 8 8 8 8 8 µs max

CLK

Internal Clock 7/9 7/9 7/9 7/9 7/9 µs min/µs max

POWER REQUIREMENTS

V

DD

V

SS

I

DD

I

SS

+5 +5 +5 +5 +5 V nom ±5% for Specified Performance
–5 –5 –5 –5 –5 V nom ± 5% for Specified Performance
13 13 13 13 13 mA max Typically 8 mA
6 6 6 6 6 mA max Typically 4 mA

Power Dissipation 95 95 95 95 95 mW max Typically 60 mW

NOTES

1

Temperature ranges are as follows: J, K, L Versions; 0°C to +70°C: A, B, C Versions; –25 °C to +85°C: S, T Versions; –55 °C to +125°C.

2

VIN (pk-pk) = ±3 V.

3

SNR calculation includes distortion and noise components.

4

Measured with respect to internal reference and includes bipolar offset error.

5

Sample tested @ +25°C to ensure compliance.

Specifications subject to change without notice.

–2–

REV. B

AD7870/AD7875/AD7876

Parameter K, B1L, C1T

AD7875/AD7876

1

Units Test Conditions/Comments

DC ACCURACY

Resolution 12 12 12 Bits
Minimum Resolution for Which

No Missing Codes Are Guaranteed 12 12 12 Bits

Integral Nonlinearity @ +25°C ±1 ±1/2 ±1 LSB max

T

to T

MIN

T

MIN

(AD7875 Only) ±1 ±1 ±1 LSB max

MAX

to T

(AD7876 Only) ±1 ±1/2 ±1 LSB max

MAX

Differential Nonlinearity ± 1 ±1 ±1.5/–1.0 LSB max
Unipolar Offset Error (AD7875 Only) ±5 ±5 ±5 LSB max
Bipolar Zero Error (AD7876 Only) ±6 ±2 ±6 LSB max
Full-Scale Error at +25°C
Full-Scale TC

2

2

±8 ±8 ±8 LSB max Typical Full-Scale Error Is ±1 LSB
±60 ± 35 ±60 ppm/°C max Typical TC is ± 20 ppm/°C

Track/Hold Acquisition Time 2 2 2 µs max

DYNAMIC PERFORMANCE3 (AD7875 ONLY)

Signal-to-Noise Ratio4 (SNR)

@ +25°C 70 72 69 dB min VIN = 10 kHz Sine Wave, f
T

MIN

to T

MAX

70 71 69 dB min Typically 71.5 dB for 0 < V

Total Harmonic Distortion (THD) –80 –80 –78 dB max VIN = 10 kHz Sine Wave, f

Typically –86 dB for 0 < V

Peak Harmonic or Spurious Noise –80 –80 –78 dB max VIN = 10 kHz, f

SAMPLE

= 100 kHz

Typically –86 dB for 0 < V

SAMPLE

< 50 kHz

IN

SAMPLE

< 50 kHz

IN

< 50 kHz

IN

= 100 kHz

= 100 kHz

Intermodulation Distortion (IMD)
Second Order Terms –80 –80 –78 dB max fa = 9 kHz, fb = 9.5 kHz, f
Third Order Terms –80 –80 –78 dB max fa = 9 kHz, fb = 9.5 kHz, f

SAMPLE
SAMPLE

= 50 kHz
= 50 kHz

ANALOG INPUT

AD7875 Input Voltage Range 0 to +5 0 to +5 0 to +5 Volts
AD7875 Input Current 500 500 500 µA max
AD7876 Input Voltage Range ±10 ±10 ±10 Volts
AD7876 Input Current ±600 ±600 ±600 µA max

REFERENCE OUTPUT

REF OUT @ +25°C 2.99 2.99 2.99 V min

3.01 3.01 3.01 V max
REF OUT Tempco ±60 ±35 ±60 ppm/°C max Typical Tempco Is ±20 ppm/°C
Reference Load Sensitivity (∆REF OUT/∆I) –1 –1 –1 mV max Reference Load Current Change (0 µA–500 µA)

Reference Load Should Not Be Changed
During Conversion.

LOGIC INPUTS

Input High Voltage, V
Input Low Voltage, V
Input Current, I
Input Current (12/8/CLK Input Only) ±10 ±10 ±10 µA max VIN = VSS to V
Input Capacitance, C

INH

INL

IN

5

IN

2.4 2.4 2.4 V min VDD = 5 V ± 5%

0.8 0.8 0.8 V max VDD = 5 V ± 5%

±10 ±10 ±10 µA max VIN = 0 V to V

DD
DD

10 10 10 pF max

LOGIC OUTPUTS

Output High Voltage, V
Output Low Voltage, V

OH

OL

4.0 4.0 4.0 V min I

0.4 0.4 0.4 V max I

SOURCE

= 1.6 mA

SINK

= 40 µA

DB11–DB0

Floating-State Leakage Current 10 10 10 µA max
Floating-State Output Capacitance

5

15 15 15 pF max

CONVERSION TIME

External Clock (f

= 2.5 MHz) 8 8 8 µs max

CLK

Internal Clock 7/9 7/9 7/9 µs min/µs max

POWER REQUIREMENTS As per AD7870

NOTES

1

Temperature ranges are as follows: AD7875: K, L Versions, 0 °C to +70°C; B, C Versions, –40°C to +85°C; T Version, –55°C to +125°C. AD7876: B, C Versions,

–40°C to +85°C; T Version, –55°C to +125°C.

2

Includes internal reference error and is calculated after unipolar offset error (AD7875) or bipolar zero error (AD7876) has been adjusted out.

Full-scale error refers to both positive and negative full-scale error for the AD7876.

3

Dynamic performance parameters are not tested on the AD7876 but these are typically the same as for the AD7875.

4

SNR calculation includes distortion and noise components.

5

Sample tested @ +25°C to ensure compliance.

Specifications subject to change without notice.

REV. B

–3–

AD7870/AD7875/AD7876

WARNING!

ESD SENSITIVE DEVICE

TIMING CHARACTERISTICS

1, 2

(VDD = +5 V 6 5%, VSS = –5 V 6 5%, AGND = DGND = 0 V. See Figures 9, 10, 11 and 12.)

Limit at T

MIN

, T

MAX

Limit at T

MIN

, T

MAX

Parameter (J, K, L, A, B, C Versions) (S, T Versions) Units Conditions/Comments

t

1

t

2

t

3

t

4

t

5

3

t

6

4

t

7

50 50 ns min CONVST Pulse Width
0 0 ns min CS to RD Setup Time (Mode 1)
60 75 ns min RD Pulse Width
0 0 ns min CS to RD Hold Time (Mode 1)
70 70 ns max RD to INT Delay
57 70 ns max Data Access Time after RD
5 5 ns min Bus Relinquish Time after RD
50 50 ns max

t

8

t

9

t

10

5

t

11

6

t

12

t

13

0 0 ns min HBEN to RD Setup Time
0 0 ns min HBEN to RD Hold Time
100 100 ns min SSTRB to SCLK Falling Edge Setup Time
370 370 ns min SCLK Cycle Time
135 150 ns max SCLK to Valid Data Delay. CL = 35 pF
20 20 ns min SCLK Rising Edge to SSTRB
100 100 ns max

t

14

10 10 ns min Bus Relinquish Time after SCLK
100 100 ns max

t

15

t

16

t

17

t

18

t

19

t

20

NOTES

1

Timing specifications in bold print are 100% production tested. All other times are sample tested at +25°C to ensure compliance. All input signals are
specified with tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V.

2

Serial timing is measured with a 4.7 kΩ pull-up resistor on SDATA and SSTRB and a 2 kΩ pull-up on SCLK. The capacitance on all three outputs is 35 pF.

3

t6 is measured with the load circuits of Figure 1 and defined as the time required for an output to cross 0.8 V or 2.4 V.

4

t7 is defined as the time required for the data lines to change 0.5 V when loaded with the circuits of Figure 2.

5

SCLK mark/space ratio (measured from a voltage level of 1.6 V) is 40/60 to 60/40.

6

SDATA will drive higher capacitive loads but this will add to t12 since it increases the external RC time constant (4.7 kΩiCL) and hence the time to reach 2.4 V.

Specifications subject to chance without notice.

60 60 ns min CS to RD Setup Time (Mode 2)
120 120 ns max CS to BUSY Propagation Delay
200 200 ns min Data Setup Time Prior to BUSY
0 0 ns min CS to RD Hold Time (Mode 2)
0 0 ns min HBEN to CS Setup Time
0 0 ns min HBEN to CS Hold Time

ABSOLUTE MAXIMUM RATINGS*

VDD to AGND . . . . . . . . . . . . . . . . . . . . . . . . . .–0.3 V to +7 V

to AGND . . . . . . . . . . . . . . . . . . . . . . . . . .+0.3 V to –7 V

V

SS

AGND to DGND . . . . . . . . . . . . . . . . . –0.3 V to V

to AGND . . . . . . . . . . . . . . . . . . . . . . . . . –15 V to +15 V

V

IN

REF OUT to AGND . . . . . . . . . . . . . . . . . . . . . . . . 0 V to V

+0.3 V

DD

DD

Digital Inputs to DGND . . . . . . . . . . . . –0.3 V to VDD +0.3 V

Digital Outputs to DGND . . . . . . . . . . . –0.3 V to V

+0.3 V

DD

Operating Temperature Range

Commercial (J, K, L Versions – AD7870) . . . 0°C to +70°C

Commercial (K, L Versions – AD7875) . . . . . 0°C to +70°C

Industrial (A, B, C Versions – AD7870) . . . . –25°C to +85°C

a. High-Z to V

Figure 1. Load Circuits for Access Time

Industrial (B, C Versions – AD7875/AD7876)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .–40°C to +85°C

Extended (S, T Versions) . . . . . . . . . . . . . .–55°C to +125°C

Storage Temperature Range . . . . . . . . . . . . .–65°C to +150°C

Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . . +300°C

Power Dissipation (Any Package) to +75°C . . . . . . . . .450 mW

Derates above +75°C by . . . . . . . . . . . . . . . . . . . . . 10 mW/°C

*Stresses above those listed under “Absolute Maximum Ratings” may cause

permanent damage to the device. This is a stress rating only; functional
operation of the device at these or any other conditions above those listed in
the operational sections of this specification is not implied. Exposure
to absolute maximum rating conditions for extended periods may affect
device reliability.

a. VOH to High-Z b. VOL to High-Z

Figure 2. Load Circuits for Output Float Delay

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD7870/AD7875/AD7876 feature proprietary ESD protection circuitry, permanent damage
may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.

–4–

OH

b. High-Z to V

OL

REV. B

AD7870/AD7875/AD7876

AD7870 ORDERING GUIDE

Integral
Temperature V
Range Range (V) (dBs) (LSB) Option

Model

1, 2

AD7870JN 0°C to +70°C ±3 70 min ±1/2 typ N-24
AD7870KN 0°C to +70°C ±3 70 min ±1 max N-24
AD7870LN 0°C to +70°C ± 3 72 min ± 1/2 max N-24
AD7870JP 0°C to +70°C ±3 70 min ±1/2 typ P-28A
AD7870KP 0°C to +70°C ±3 70 min ±1 max P-28A
AD7870LP 0°C to +70°C ±3 72 min ± 1/2 max P-28A
AD7870AQ –25°C to +85°C ±3 70 min ±1/2 typ Q-24
AD7870BQ –25°C to +85°C ±3 70 min ±1 max Q-24
AD7870CQ –25°C to +85°C ±3 72 min ±1/2 max Q-24
AD7870SQ
AD7870TQ

NOTES

1

To order MIL-STD-883, Class B, processed parts, add /883B to part number. Contact local sales office for military data sheet.

2

Contact local sales office for LCCC (Leadless Ceramic Chip Carrier) availability.

3

N = Narrow Plastic DIP; P = Plastic Leaded Chip Carrier (PLCC); Q = Cerdip.

4

Available to /883B processing only.

4

4

–55°C to +125°C ±3 70 min ±1/2 typ Q-24
–55°C to +125°C ±3 70 min ±1 max Q-24

AD7875 ORDERING GUIDE

Temperature VIN Voltage SNR Nonlinearity Package
Range Range (V) (dBs) (LSB) Option

Model

1, 2

Voltage SNR Nonlinearity Package

IN

Integral

3

3

2

AD7875KN 0°C to +70°C 0 to +5 70 min ±1 max N-24
AD7875LN 0°C to +70°C 0 to +5 72 min ±1/2 max N-24
AD7875KP 0°C to +70°C 0 to +5 70 min ±1 max P-28A
AD7875LP 0°C to +70°C 0 to +5 72 min ±1/2 max P-28A
AD7875BQ –40°C to +85°C 0 to +5 70 min ±1 max Q-24
AD7875CQ –40°C to +85°C 0 to +5 72 min ±1/2 max Q-24
AD7875TQ

NOTES

1

To order MIL-STD-883, Class B. processed parts, add /883B to part number. Contact local sales office for military data sheet.

2

Contact local sales office for LCCC (Leadless Ceramic Chip Carrier) availability.

3

N = Narrow Plastic DlP; P = Plastic Leaded Chip Carrier (PLCC); Q = Cerdip.

4

Available to /883B processing only.

4

–55°C to +125°C 0 to +5 70 min ±1 max Q-24

AD7876 ORDERING GUIDE

Integral

Model

1

Temperature V
Range Range (V) (LSB) Option

Voltage Nonlinearity Package

IN

2

AD7876BN –40°C to +85°C ±10 ±1 max N-24
AD7876CN –40°C to +85°C ±10 ±1/2 max N-24
AD7876BR –40°C to +85°C ±10 ±1 max R-24
AD7876CR –40°C to +85°C ±10 ±1/2 max R-24
AD7876BQ –40°C to +85°C ±10 ±1 max Q-24
AD7876CQ –40°C to +85°C ±10 ±1/2 max Q-24
AD7876TQ

NOTES

1

To order MIL-STD-883, Class B, processed parts, add /883B to the part number. Contact local sales office for military data sheet.

2

N = Narrow Plastic DIP; Q = Cerdip; R = Small Outline IC (SOIC).

3

Available to /883B processing only.

3

–55°C to +125°C ±10 ±1 max Q-24

REV. B

–5–

AD7870/AD7875/AD7876

PIN FUNCTION DESCRIPTION

DIP Pin
Pin No. Mnemonic Function

1
2

RD Read. Active low logic input. This input is used in conjunction with CS low to enable the data outputs.
BUSY/INT Busy/Interrupt, Active low logic output indicating converter status. See timing diagrams.

3 CLK Clock input. An external TTL-compatible clock may be applied to this input pin. Alternatively, tying this pin to

V

enables the internal laser-trimmed clock oscillator.

4 DB11/HBEN Data Bit 11 (MSB)/High Byte Enable. The function of this pin is dependent on the state of the 12/

SS

8/CLK input (see
below). When 12-bit parallel data is selected, this pin provides the DB11 output. When byte data is selected, this pin
becomes the HBEN logic input HBEN is used for 8-bit bus interfacing. When HBEN is low, DB7/LOW to DB0/DB8
become DB7 to DB0. With HBEN high, DB7/LOW to DB0/DB8 are used for the upper byte of data (see Table I).

5 DB10/

SSTRB Data Bit 10/Serial Strobe. When 12-bit parallel data is selected, this pin provides the DB10 output. SSTRB is an

active low open-drain output that provides a strobe or framing pulse for serial data. An external 4.7 kΩ pull-up
resistor is required on

SSTRB.

6 DB9/SCLK Data Bit 9/Serial Clock. When 12-bit parallel data is selected, this pin provides the DB9 output. SCLK is the gated

serial clock output derived from the internal or external ADC clock. If the 12/
runs continuously. If 12/

8/CLK is at 0 V, then SCLK is gated off after serial transmission is complete. SCLK is an

8/CLK input is at –5 V, then SCLK

open-drain output and requires an external 2 kΩ pull-up resistor.

7 DB8/SDATA Data Bit 8/Serial Data. When 12-bit parallel data is selected, this pin provides the DB8 output. SDATA is an open-

drain serial data output which is used with SCLK and
ing edge of SCLK while

8–11 DB7/LOW– Three-state data outputs controlled by

DB4/LOW With 12/

8/CLK high, they are always DB7–DB4. With 12/8/CLK low or –5 V, their function is controlled by HBEN

SSTRB is low. An external 4.7 kΩ pull-up resistor is required on SDATA.

CS and RD. Their function depends on the 12/8/CLK and HBEN inputs.

SSTRB for serial data transfer. Serial data is valid on the fall-

(see Table I).

12 DGND Digital Ground. Ground reference for digital circuitry.
13–16 DB3/DB11– Three-state data outputs which are controlled by

DB0/DB8 inputs. With 12/

8/CLK high, they are always DB3–DB0. With 12/8/CLK low or –5 V, their function is controlled by

CS and RD. Their function depends on the 12/8/CLK and HBEN

HBEN (see Table I).

Table I. Output Data for Byte Interfacing

HBEN DB7/LOW DB6/LOW DB5/LOW DB4/LOW DB3/DB11 DB2/DB10 DB1/DB9 DB0/DB8
HIGH LOW LOW LOW LOW DB11(MSB) DB10 DB9 DB8
LOW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 (LSB)

17 V

DD

Positive Supply, +5 V ± 5%.

18 AGND Analog Ground. Ground reference for track/hold, reference and DAC.
19 REF OUT Voltage Reference Output. The internal 3 V reference is provided at this pin. The external load capability is 500 µA.
20 V
21 V
22 12/

IN
SS

8/CLK Three Function Input. Defines the data format and serial clock format. With this pin at +5 V, the output data for-

Analog Input. The analog input range is ±3 V for the AD7870, ±10 V for the AD7876 and 0 V to +5 V for the AD7875.
Negative Supply, –5 V ± 5%.

mat is 12-bit parallel only. With this pin at 0 V, either byte or serial data is available and SCLK is not continuous.
With this pin at –5 V, either byte or serial data is again available but SCLK is now continuous.

23

CONVST Convert Start. A low to high transition on this input puts the track/hold into its hold mode and starts conversion.

This input is asynchronous to the CLK input.

24

CS Chip Select. Active low logic input. The device is selected when this input is active. With CONVST tied low, a new

conversion is initiated when CS goes low.

1

PLCC

2

DIP and SOIC

2

PIN CONFIGURATIONS

1

PIN CONFIGURATIONS ARE THE SAME FOR

THE AD7875 AND AD7876.

2

THE AD7870 AND AD7875 ARE AVAILABLE IN

DIP AND PLCC; THE AD7870A IS AVAILABLE IN
PLASTIC DIP; THE AD7875 AND AD7876 ARE
AVAILABLE IN SOIC AND DIP.

–6–

REV. B