Analog Devices AD7874SQ, AD7874SE, AD7874BR, AD7874BQ, AD7874BN Datasheet
...
LC2MOS 4-Channel, 12-Bit Simultaneous
AGND
CLK
DGND
DB11
DB0
V
SS
CS
12-BIT
DAC
V
IN1
V
IN2
V
IN3
V
IN4
COMP
REFERENCE
BUFFER
INT
RD
AD7874
CONVST
VDDV
DD
REF IN
REF OUT
3V
REFERENCE
DATA
REGISTERS
SAR
MUX
CONTROL LOGIC
INTERNAL
CLOCK
TRACK/
HOLD 3
TRACK/
HOLD 4
TRACK/
HOLD 2
TRACK/
HOLD 1
a
Sampling Data Acquisition System
AD7874
FEATURES
Four On-Chip Track/Hold Amplifiers
Simultaneous Sampling of 4 Channels
Fast 12-Bit ADC with 8 ms Conversion Time/Channel
29 kHz Sample Rate for All Four Channels
On-Chip Reference
610 V Input Range
65 V Supplies
APPLICATIONS
Sonar
Motor Controllers
Adaptive Filters
Digital Signal Processing
GENERAL DESCRIPTION
The AD7874 is a four-channel simultaneous sampling, 12-bit
data acquisition system. The part contains a high speed 12-bit
ADC, on-chip reference, on-chip clock and four track/hold amplifiers. This latter feature allows the four input channels to be
sampled simultaneously, thus preserving the relative phase
information of the four input channels, which is not possible if
all four channels share a single track/hold amplifier. This makes
the AD7874 ideal for applications such as phased-array sonar
and ac motor controllers where the relative phase information is
important.
The aperture delay of the four track/hold amplifiers is small and
specified with minimum and maximum limits. This allows several AD7874s to sample multiple input channels simultaneously
without incurring phase errors between signals connected to
several devices. A reference output/reference input facility also
allows several AD7874s to be driven from the same reference
source.
In addition to the traditional dc accuracy specifications such as
linearity, full-scale and offset errors, the AD7874 is also fully
specified for dynamic performance parameters including distortion and signal-to-noise ratio.
The AD7874 is fabricated in Analog Devices’ Linear Compatible CMOS (LC
that combines precision bipolar circuits with low-power CMOS
logic. The part is available in a 28-pin, 0.6" wide, plastic or hermetic dual-in-line package (DIP), in a 28-terminal leadless ceramic chip carrier (LCCC) and in a 28-pin SOIC.
REV. C
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
2
MOS) process, a mixed technology process
PRODUCT HIGHLIGHTS
1. Simultaneous Sampling of Four Input Channels.
Four input channels, each with its own track/hold amplifier,
allow simultaneous sampling of input signals. Track/hold acquisition time is 2 µs, and the conversion time per channel is
8 µs, allowing 29 kHz sample rate for all four channels.
2. Tight Aperture Delay Matching.
The aperture delay for each channel is small and the aperture
delay matching between the four channels is less than 4 ns.
Additionally, the aperture delay specification has upper and
lower limits allowing multiple AD7874s to sample more than
four channels.
3. Fast Microprocessor Interface.
The high speed digital interface of the AD7874 allows direct
connection to all modern 16-bit microprocessors and digital
signal processors.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700 Fax: 617/326-8703
FUNCTIONAL BLOCK DIAGRAM
AD7874–SPECIFICA TIONS
(VDD = +5 V, VSS = –5 V, AGND = DGND = 0 V, REF IN = +3 V, f
external. All specifications T
MIN
to T
unless otherwise noted.)
MAX
= 2.5 MHz
CLK
Parameter A Version B Version S Version Units Test Conditions/Comments
SAMPLE-AND-HOLD
Acquisition Time2 to 0.01% 2 2 2 µs max
Droop Rate
–3 dB Small Signal Bandwidth
Aperture Delay
Aperture Jitter
Aperture Delay Matching
2, 3
2, 3
2
3
1 1 2 mV/ms max
500 500 500 kHz typ VIN = 500 mV p-p
0 0 0 ns min
40 40 40 ns max
2
200 200 200 ps typ
4 4 4 ns max
SAMPLE-AND-HOLD AND ADC
DYNAMIC PERFORMANCE
Signal-to-Noise Ratio 70 71 70 dB min fIN = 10 kHz Sine Wave, f
Total Harmonic Distortion –78 –80 –78 dB max fIN = 10 kHz Sine Wave, f
Peak Harmonic or Spurious Noise –78 –80 –78 dB max fIN = 10 kHz Sine Wave, f
Intermodulation Distortion fa = 9 kHz, fb = 9.5 kHz, f
SAMPLE
SAMPLE
SAMPLE
SAMPLE
= 29 kHz
= 29 kHz
= 29 kHz
= 29 kHz
2nd Order Terms –80 –80 –80 dB max
3rd Order Terms –80 –80 –80 dB max
Channel-to-Channel Isolation
2
–80 –80 –80 dB max
DC ACCURACY
Resolution 12 12 12 Bits
Relative Accuracy ± 1 ±1/2 ± 1 LSB max
Differential Nonlinearity ± 1 ±1 ±1 LSB max No Missing Codes Guaranteed
Positive Full-Scale Error
Negative Full-Scale Error
4
4
± 5 ± 5 ±5 LSB max Any Channel
±5 ±5 ±5 LSB max Any Channel
Full-Scale Error Match 5 5 5 LSB max Between Channels
Bipolar Zero Error ±5 ±5 ±5 LSB max Any Channel
Bipolar Zero Error Match 4 4 4 LSB max Between Channels
ANALOG INPUTS
Input Voltage Range ±10 ±10 ±10 Volts
Input Current ± 600 ±600 ± 600 µA max
REFERENCE OUTPUTS
REF OUT 333V nom
REF OUT Error @ +25°C ±0.33 ±0.33 ±0.33 % max
T
MIN
to T
MAX
±1 ±1 ±1 % max
REF OUT Temperature Coefficient ±35 ±35 ± 35 ppm/°C typ
Reference Load Change ±1 ±1 ±2 mV max Reference Load Current Change (0–500 µA)
Reference Load Should Not Be Changed During Conversion
REFERENCE INPUT
Input Voltage Range 2.85/3.15 2.85/3.15 2.85/3.15 V min/V max 3 V ± 5%
Input Current ± 1 ±1 ±1 µA max
Input Capacitance
3
10 10 10 pF max
LOGIC INPUTS
Input High Voltage, V
Input Low Voltage, V
Input Current, I
Input Capacitance, C
IN
IN
INH
INL
3
2.4 2.4 2.4 V min VDD = 5 V ± 5%
0.8 0.8 0.8 V max VDD = 5 V ± 5%
±10 ±10 ±10 µA max VIN = 0 V to V
10 10 10 pF max
DD
LOGIC OUTPUTS
Output High Voltage, V
Output Low Voltage, V
OL
OH
4.0 4.0 4.0 V min VDD = 5 V ± 5%; I
0.4 0.4 0.4 V max VDD = 5 V ± 5%; I
SOURCE
= 1–6 mA
SINK
= 40 µA
DB0–DB11
Floating-State Leakage Current ±10 ±10 ±10 µA max VIN = 0 V to V
DD
Floating-State Output Capacitance 10 10 10 pF max
Output Coding 2s COMPLEMENT
POWER REQUIREMENTS
V
DD
V
SS
I
DD
I
SS
+5 +5 +5 V nom ± 5% for Specified Performance
–5 –5 –5 V nom ±5% for Specified Performance
18 18 18 mA max CS = RD = CONVST = +5 V; Typically 12 mA
12 12 12 mA max CS = RD = CONVST = +5 V; Typically 8 mA
Power Dissipation 150 150 150 mW max CS = RD = CONVST = +5 V; Typically 100 mW
NOTES
1
Temperature ranges are as follows: A, B Versions: –40°C to +85°C; S Version: –55°C to +125°C.
2
See Terminology.
3
Sample tested @ +25°C to ensure compliance.
4
Measured with respect to the REF IN voltage and includes bipolar offset error.
5
For capacitive loads greater than 50 pF a series resistor is required.
Specifications subject to change without notice.
–2–
REV. C
AD7874
TIMING CHARACTERISTICS
(VDD = +5 V 6 5%, VSS = –5 V 6 5%, AGND = DGND = O V, t
1
otherwise noted.)
= 2.5 MHz external unless
CLK
Parameter A, B Versions S Version Units Conditions/Comments
t
1
t
2
t
3
t
4
t
5
2
t
6
3
t
7
50 50 ns min CONVST Pulse Width
0 0 ns min CS to RD Setup Time
60 70 ns min RD Pulse Width
0 0 ns min CS to RD Hold Time
60 60 ns max RD to INT Delay
57 70 ns max Data Access Time after RD
55ns min Bus Relinquish Time after RD
45 50 ns max
t
8
t
CONV
t
CLK
NOTES
1
Timing Specifications in bold print are 100% production tested. All other times are sample tested at +25°C to ensure compliance. All input signals are specified with
tr = tf = 5 ns (10% to 90% of +5 V) and timed from a voltage level of 1.6 V.
2
t6 is measured with the load circuit of Figure 1 and defined as the time required for an output to cross 0.8 V or 2.4 V.
3
t7 is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 2. The measured number is then extrapolated
back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t
time of the part and as such is independent of external bus loading capacitances.
Specifications subject to change without notice.
130 150 ns min Delay Time between Reads
31 31 µs min CONVST to INT, External Clock
32.5 32.5 µs max
31 31 µs min
35 35 µs max
CONVST to INT, External Clock
CONVST to INT, Internal Clock
CONVST to INT, Internal Clock
10 10 µs max Minimum Input Clock Period
, quoted in the timing characteristics is the true bus relinquish
7
1.6mA
ABSOLUTE MAXIMUM RATINGS*
(TA = +25°C unless otherwise noted)
VDD to AGND . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
V
to DGND . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
DD
V
to AGND . . . . . . . . . . . . . . . . . . . . . . . . . +0.3 V to –7 V
SS
AGND to DGND . . . . . . . . . . . . . . . . –0.3 V to V
V
to AGND . . . . . . . . . . . . . . . . . . . . . . . . .–15 V to +15 V
IN
REF OUT to AGND . . . . . . . . . . . . . . . . . . . . . . . 0 V to V
DD
+ 0.3 V
DD
TO OUTPUT
PIN
50pF
2.1V+
200µA
Digital Inputs to DGND . . . . . . . . . . . –0.3 V to VDD + 0.3 V
Digital Outputs to DGND . . . . . . . . . . –0.3 V to V
+ 0.3 V
DD
Figure 1. Load Circuit for Access Time
Operating Temperature Range
Commercial (A, B Versions) . . . . . . . . . . . –40°C to +85°C
1.6mA
Extended (S Version) . . . . . . . . . . . . . . . . –55°C to +125°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Lead Temperature (Soldering, 10 secs) . . . . . . . . . . . +300°C
Power Dissipation (Any Package) to +75°C . . . . . . 1,000 mW
Derates above +75°C by . . . . . . . . . . . . . . . . . . . . 10 mW/°C
*Stresses above those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those listed in the
operational sections of this specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
TO OUTPUT
PIN
50pF
200µA
2.1V+
Figure 2. Load Circuit for Bus Relinquish Time
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD7874 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
REV. C
–3–
WARNING!
ESD SENSITIVE DEVICE
AD7874
V
IN1
V
IN2
V
IN4
V
IN3
REF IN
AGND
DB0 (LSB)
V
DD
V
SS
REF OUT
CLK DB1
V
DD
DB2
DB11 (MSB) DB3
DB10 DB4
DB9 DB5
DB8 DB6
DGND DB7
13
18
1
2
28
27
5
6
7
24
23
22
3
4
26
25
821
920
10
19
1111
12
17
16
14
15
TOP VIEW
(Not to Scale)
AD7874
INT
CONVST
RD
CS
V
DD
CLK
V
DD
V
IN4
V
IN2
V
IN1
DB9
DB8
DB6
DGND
DB7
REF OUT
REF IN
DB1
AGND
DB0 (LSB)
DB10
DB11 (MSB)
DB4
DB5
V
SS
V
IN3
DB3
DB2
AD7874
2712822634
25
22
24
23
21
19
20
181712 13 1614 15
11
10
9
8
7
6
5
TOP VIEW
(Not to Scale)
CONVST
RD
CS
INT
TERMINOLOGY
ACQUISITION TIME
Acquisition Time is the time required for the output of the
track/hold amplifiers to reach their final values, within ±1/2
LSB, after the falling edge of
holds return to track mode). This includes switch delay time,
slewing time and settling time for a full-scale voltage change.
APERTURE DELAY
Aperture Delay is defined as the time required by the internal
switches to disconnect the hold capacitors from the inputs. This
produces an effective delay in sample timing. It is measured by
applying a step input and adjusting the
until the output code follows the step input change.
APERTURE DELAY MATCHING
Aperture Delay Matching is the maximum deviation in aperture
delays across the four on-chip track/hold amplifiers.
APERTURE JITTER
Aperture Jitter is the uncertainty in aperture delay caused by
internal noise and variation of switching thresholds with signal
level.
DROOP RATE
Droop Rate is the change in the held analog voltage resulting
from leakage currents.
INT (the point at which the track/
CONVST input position
PIN CONFIGURATIONS
DIP and SOIC
LCCC
CHANNEL-TO-CHANNEL ISOLATION
Channel-to-Channel Isolation is a measure of the level of
crosstalk between channels. It is measured by applying a fullscale 1 kHz signal to the other three inputs. The figure given is
the worst case across all four channels.
SNR, THD, IMD
See DYNAMIC SPECIFICATIONS section.
–4–
REV. C
PIN FUNCTION DESCRIPTION
Pin Mnemonic Description
AD7874
1V
IN1
Analog Input Channel 1. This is the first of the four input channels to be converted in a con-
version cycle. Analog input voltage range is ± 10 V.
2V
3V
4
5
IN2
DD
INT Interrupt. Active low logic output indicating converter status. See Figure 7.
CONVST Convert Start. Logic Input. A low to high transition on this input puts the track/hold into its
Analog Input Channel 2. Analog input voltage range is ±10 V.
Positive supply voltage, +5 V ± 5%. This pin should be decoupled to AGND.
hold mode and starts conversion. The four channels are converted sequentially, Channel 1 to
Channel 4. The
6
RD Read. Active low logic input. This input is used in conjunction with CS low to enable the
CONVST input is asynchronous to CLK and independent of CS and RD.
data outputs. Four successive reads after a conversion will read the data from the four chan-
nels in the sequence, Channel 1, 2, 3, 4.
7
CS Chip Select. Active low logic input. The device is selected when this input is active.
8 CLK Clock Input. An external TTL-compatible clock may be applied to this input pin. Alterna-
9V
DD
tively, tying this pin to V
Positive Supply Voltage, +5 V ± 5%. Same as Pin 3; both pins must be tied together at the
enables the internal laser trimmed clock oscillator.
SS
package. This pin should be decoupled to DGND.
10 DB11 Data Bit 11 (MSB). Three-state TTL output. Output coding is 2s complement.
11–13 DB10–DB8 Data Bit 10 to Data Bit 8. Three-state TTL outputs.
14 DGND Digital Ground. Ground reference for digital circuitry.
15–21 DB7–DB1 Data Bit 7 to Data Bit 1. Three-state TTL outputs.
22 DB0 Data Bit 0 (LSB). Three-state TTL output.
23 AGND Analog Ground. Ground reference for track/hold, reference and DAC.
24 REF IN Voltage Reference Input. The reference voltage for the part is applied to this pin. It is inter-
nally buffered, requiring an input current of only ±1 µA. The nominal reference voltage for
correct operation of the AD7874 is 3 V.
25 REF OUT Voltage Reference Output. The internal 3 V analog reference is provided at this pin. To oper-
ate the AD7874 with internal reference, REF OUT is connected to REF IN. The external
load capability of the reference is 500 µA.
26 V
27 V
28 V
SS
IN3
IN4
Negative Supply Voltage, –5 V ± 5%.
Analog Input Channel 3. Analog input voltage range is ±10 V.
Analog Input Channel 4. Analog input voltage range is ±10 V.
REV. C
ORDERING GUIDE
Relative
Temperature SNR Accuracy Package
Range (dBs) (LSB) Option
Model
1
AD7874AN –40°C to +85°C 70 min ±1 max N-28
AD7874BN –40°C to +85°C 72 min ±1/2 max N-28
AD7874AR –40°C to +85°C 70 min ±1 max R-28
AD7874BR –40°C to +85°C 72 min ±1/2 max R-28
AD7874AQ –40°C to +85°C 70 min ±1 max Q-28
AD7874BQ –40°C to +85°C 72 min ±1/2 max Q-28
AD7874SQ
AD7874SE
NOTES
1
To order MIL-STD-883, Class B processed parts, add /883B to part number. Contact
1
our local sales office for military data sheet and availability.
2
E = Leaded Ceramic Chip Carrier; N = Plastic DIP; Q = Cerdip; R = SOIC.
3
Available to /883B processing only.
3
–55°C to +125°C 70 min ±1 max Q-28
3
–55°C to +125°C 70 min ±1 max E-28A
–5–
2
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