Analog Devices AD7819 Datasheet

+2.7 V to +5.5 V, 200 kSPS

CLOCK

OSC

CHARGE

REDISTRIBUTION

DAC

THREE-

STATE

DRIVERS

CONTROL

LOGIC

BUSY

CS RD CONVST

V

IN

VDDAGND V

REF

DB7

DB0

COMP

AD7819

T/H

a

FEATURES
8-Bit ADC with 4.5 s Conversion Time
On-Chip Track and Hold
Operating Supply Range: +2.7 V to +5.5 V
Specifications at +2.7 V – 3.6 V and 5 V  10%
8-Bit Parallel Interface

8-Bit Read

Power Performance

Normal Operation

10.5 mW, V

Automatic Power-Down

57.75 W @ 1 kSPS, VDD = 3 V
Analog Input Range: 0 V to V
Reference Input Range: 1.2 V to V

GENERAL DESCRIPTION

The AD7819 is a high speed, microprocessor-compatible, 8-bit
analog-to-digital converter with a maximum throughput of
200 kSPS. The converter operates off a single +2.7 V to +5.5 V
supply and contains a 4.5 µs successive approximation A/D
converter, track/hold circuitry, on-chip clock oscillator and 8-bit
wide parallel interface. The parallel interface is designed to
allow easy interfacing to microprocessors and DSPs. Using only
address decoding logic the AD7819 is easily mapped into the
microprocessor address space.

When used in its power-down mode, the AD7819 automatically
powers down at the end of a conversion and powers up at the
start of a new conversion. This feature significantly reduces the
power consumption of the part at lower throughput rates. The
AD7819 can also operate in a high speed mode where the part is
not powered down between conversions. In this mode of opera­tion the part is capable of providing 200 kSPS throughput.

The part is available in a small, 16-pin 0.3" wide, plastic dual­in-line package (DIP); in a 16-pin, 0.15" wide, narrow body
small outline IC (SOIC) and in a 16-pin, narrow body, thin
shrink small outline package (TSSOP).

= 3 V

DD

REF

DD

8-Bit Sampling ADC

AD7819

FUNCTIONAL BLOCK DIAGRAM

PRODUCT HIGHLIGHTS

1. Low Power, Single Supply Operation
The AD7819 operates from a single +2.7 V to +5.5 V sup­ply and typically consumes only 10.5 mW of power. The
power dissipation can be significantly reduced at lower
throughput rates by using the automatic power-down mode.

2. Automatic Power-Down
The automatic power-down mode, whereby the AD7819
goes into power-down mode at the end of a conversion and
powers up before the next conversion, means the AD7819
is ideal for battery powered applications; e.g., 57.75 µW
@ 1 kSPS. (See Power vs. Throughput Rate section.)

3. Parallel Interface
An easy to use 8-bit wide parallel interface allows interfacing
to most popular microprocessors and DSPs with minimal
external circuitry.

4. Dynamic Specifications for DSP Users
In addition to the traditional ADC specifications, the AD7819
is specified for ac parameters, including signal-to-noise ratio
and distortion.

REV. A

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] World Wide Web Site: http://www.analog.com
Fax: [phone] © Analog Devices, Inc., 2000

AD7819–SPECIFICATIONS

(GND = 0 V, V

1

to +125C unless otherwise noted.)

REF

= +V

= 3 V  10% to 5 V  10%). All specifications –40C

DD

Parameter Y Version Units Test Conditions/Comments

DYNAMIC PERFORMANCE f

Signal to (Noise + Distortion) Ratio
Total Harmonic Distortion (THD)
Peak Harmonic or Spurious Noise
Intermodulation Distortion

2

1

1

1

48 dB min
–70 dB typ
–70 dB typ

= 30 kHz, f

IN

SAMPLE

= 136 kHz

fa = 29.1 kHz; fb = 29.8 kHz
2nd Order Terms –77 dB typ
3rd Order Terms –77 dB typ

DC ACCURACY

Resolution 8 Bits
Minimum Resolution for Which

No Missing Codes Are Guaranteed 8 Bits

Relative Accuracy
Differential Nonlinearity (DNL)
Total Unadjusted Error
Gain Error
Offset Error

1

1

1

1

1

± 0.5 LSB max
± 0.5 LSB max
± 1 LSB max
± 0.5 LSB max
± 0.5 LSB max

ANALOG INPUT

Input Voltage Range 0 V min

V
Input Leakage Current
Input Capacitance

REFERENCE INPUTS

V

Input Voltage Range 1.2 V min

REF

2

2

2

REF

± 1 µA max

15 pF mx

V

DD

V max

V max
Input Leakage Current ± 1 µA max
Input Capacitance 20 pF max

LOGIC INPUTS

V

Input High Voltage 2.0 V min

INH,

V

Input Low Voltage 0.4 V max (0.8 V max, VDD = 5 V)

INL,

Input Current, I
Input Capacitance, C

2

IN

IN

± 1 µA max Typically 10 nA, VIN = 0 V to V
8 pF max

LOGIC OUTPUTS

Output High Voltage, V
Output Low Voltage, V

OL

OH

2.4 V min I

0.4 V max I

SOURCE

= 200 µA

SINK

= 200 µA

High Impedance Leakage Current ± 1 µA max
High Impedance Capacitance 15 pF max

CONVERSION RATE

Conversion Time 4.5 µs max
Track/Hold Acquisition Time

1

100 ns max See DC Acquisition Section

POWER SUPPLY

V

DD

I

DD

2.7–5.5 Volts For Specified Performance
Digital Inputs = 0 V or V

DD

Normal Operation 3.5 mA max
Power-Down 1 µA max V

DD

= 5 V

Power Dissipation

Normal Operation 17.5 mW max V

DD

= 5 V
Power-Down 5 µW max
Auto Power-Down (Mode 2) V

DD

= 3 V

1 kSPS Throughput 57.75 µW max
10 kSPS Throughput 577.5 µW max
50 kSPS Throughput 2.89 mW max

NOTES

1

See Terminology section.

2

Sample tested during initial release and after any redesign or process change that may affect this parameter.

Specifications subject to change without notice.

DD

–2–

REV. A

AD7819

1, 2

TIMING CHARACTERISTICS

Parameter VDD = 3 V  10% VDD = 5 V  10% Units Conditions/Comments

t

POWER-UP

t

1

t

2

t

3

t

4

t

5

3

t

6

3, 4

t

7

3

t

8

NOTES

1

Sample tested to ensure compliance.

2

See Figures 12, 13 and 14.

3

These numbers are measured with the load circuit of Figure 1. They are defined as the time required for the o/p to cross 0.8 V or 2.4 V for VDD = 5 V ± 10% and

0.4 V or 2 V for VDD = 3 V ± 10%.

4

Derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapolated back
to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t
of the part and as such is independent of external bus loading capacitances.

Specifications subject to change without notice.

ABSOLUTE MAXIMUM RATINGS*

VDD to DGND . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V

Digital Input Voltage to DGND

(CONVST, RD, CS) . . . . . . . . . . . . . . –0.3 V, V

Digital Output Voltage to DGND

(BUSY, DB0–DB7) . . . . . . . . . . . . . . . –0.3 V, V

REF

to AGND . . . . . . . . . . . . . . . . . . . –0.3 V, V

IN

Analog Input . . . . . . . . . . . . . . . . . . . . . . –0.3 V, V

Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C

Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . .+150°C

Plastic DIP Package, Power Dissipation . . . . . . . . . . 450 mW

Thermal Impedance . . . . . . . . . . . . . . . . . . . +105°C/W

θ

JA

Lead Temperature, (Soldering 10 sec) . . . . . . . . . . .+260°C

SOIC Package, Power Dissipation . . . . . . . . . . . . . . . 450 mW

Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 75°C/W

θ

JA

Lead Temperature, Soldering

Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . .+215°C

Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . .+220°C

SSOP Package, Power Dissipation . . . . . . . . . . . . . . . 450 mW

Thermal Impedance . . . . . . . . . . . . . . . . . . . . 115°C/W

θ

JA

Lead Temperature, Soldering

Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . +215°C

Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . .+220°C

ESD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ≤4 kV

*Stresses above those listed under Absolute Maximum Ratings may cause perma-

nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.

11 µs (max) Power-Up Time of AD7819 after Rising Edge of CONVST.

4.5 4.5 µs (max) Conversion Time.
30 30 ns (min) CONVST Pulsewidth.
30 30 ns (max) CONVST Falling Edge to BUSY Rising Edge Delay.
0 0 ns (min) CS to RD Setup Time.
0 0 ns (min) CS Hold Time after RD High.
10 10 ns (max) Data Access Time after RD Low.
10 10 ns (max) Bus Relinquish Time after RD High.
100 100 ns (min) Data Bus Relinquish to Falling Edge of CONVST Delay.

(–40C to +125C, unless otherwise noted)

, quoted in the Timing Characteristics is the true bus relinquish time

7

+ 0.3 V

DD

+ 0.3 V

DD

+ 0.3 V

DD

+ 0.3 V

DD

OUTPUT

PIN

Figure 1. Load Circuit for Digital Output Timing

Specifications

Model (LSB) Description Option

AD7819YN ± 1 LSB Plastic DIP N-16
AD7819YR ±1 LSB Small Outline IC R-16A
AD7819YRU ± 1 LSB Thin Shrink Small Outline RU-16

I

OL

+1.6V

I

OH

TO

50pF

200A

C

L

200A

ORDERING GUIDE

Linearity
Error Package Package

(TSSOP)

REV. A

–3–

AD7819

PIN FUNCTION DESCRIPTIONS

Pin
No. Mnemonic Description

1V
2V

REF

IN

3 GND Analog and Digital Ground.
4 CONVST Convert Start. A low-to-high transition on this pin initiates a 1 µs pulse on an internally generated

5 CS Chip Select. This is a logic input. CS is used in conjunction with RD to enable outputs.
6 RD Read Pin. This is a logic input. When CS is low and RD goes low, the DB7–DB0 leave their high

7 BUSY ADC Busy Signal. This is a logic output. This signal goes logic high during the conversion process.
8–15 DB0–DB7 Data Bit 0 to 7. These outputs are three-state TTL-compatible.
16 V

DD

Reference Input, 1.2 V to VDD.
Analog Input, 0 V to V

REF

.

CONVST signal. A high-to-low transition on this line initiates the conversion process if the internal
CONVST signal is low. Depending on the signal on this pin at the end of a conversion, the AD7819

automatically powers down.

impedance state and data is driven onto the data bus.

Positive power supply voltage, +2.7 V to +5.5 V.

PIN CONFIGURATION

DIP/SOIC

1

V

REF

2

V

IN

3

GND

CONVST

BUSY

AD7819

4

TOP VIEW

5

CS

(Not to Scale)

6

RD

7

8

DB0 DB1

16

V

DD

15

DB7

14

DB6

13

DB5

12

DB4

11

DB3

10

DB2

9

–4–

REV. A