Analog Devices AD7809, AD7804, AD7808, AD7805 Datasheet

a

+3.3 V to +5 V Quad/Octal 10-Bit DACs

AD7804/AD7805/AD7808/AD7809*

FEATURES
Four 10-Bit DACs in One Package
Serial and Parallel Loading Facilities Available

AD7804 Quad 10-Bit Serial Loading
AD7805 Quad 10-Bit Parallel Loading
AD7808 Octal 10-Bit Serial Loading

AD7809 Octal 10-Bit Parallel Loading
+3.3 V to +5 V Operation
Power-Down Mode
Power-On Reset
Standby Mode (All DACs/Individual DACs)
Low Power All CMOS Construction
10-Bit Resolution
Double Buffered DAC Registers
Dual External Reference Capability

APPLICATIONS
Optical Disk Drives
Instrumentation and Communication Systems
Process Control and Voltage Setpoint Control
Trim Potentiometer Replacement
Automatic Calibration

GENERAL DESCRIPTION

The AD7804/AD7808 are quad/octal 10-bit digital-to-analog
converters, with serial load capabilities, while the AD7805/AD7809
are quad/octal 10-bit digital-to-analog converters with parallel
load capabilities. These parts operate from a +3.3 V to +5 V

(±10%) power supply and incorporates an on-chip reference.

These DACs provide output signals in the form of V

is derived internally from V

V

SWING

. On-chip control registers

BIAS

BIAS

± V

SWING

.

include a system control register and channel control registers.
The system control register has control over all DACs in the
package. The channel control registers allow individual control
of DACs. The complete transfer function of each individual
DAC can be shifted around the V

point using an on-chip

BIAS

Sub DAC. All DACs contain double buffered data inputs,
which allow all analog outputs to be simultaneously updated
using the asynchronous LDAC input.

Control Features Channels Controlled Main DAC Sub DAC

Hardware Clear All 兹兹

System Control

Power Down

1

All 兹兹

System Standby2All 兹兹
System Clear All 兹
Input Coding All 兹兹

Channel Control

Channel Standby2Selective 兹兹
Channel Clear Selective 兹
V

BIAS

NOTES

1

Power-down function powers down all internal circuitry including the reference.

2

Standby functions power down all circuitry except for the reference.

Selective 兹兹

REV. A

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.

FUNCTIONAL BLOCK DIAGRAMS

AV

REFOUT

REFIN

COMP

PD**

FSIN

CLKIN

SDIN

REFOUT

REFIN

COMP

PD**

CS

WR

1.23V REF

AV

DD

DIVIDER

CHANNEL D

CONTROL REG

CHANNEL C

CONTROL REG

CHANNEL B

CONTROL REG

CHANNEL A

CONTROL REG

SYSTEM

CONTROL REG

**ONLY AD7804 SHOWN FOR CLARITY
**SHOWS ADDITIONAL CHANNELS ON THE AD7808

**PIN ON THE AD7808 ONLY

SYSTEM

CONTROL REG

CONTROL

LOGIC

MODE A0 A1 DB9 DB2 DB1 DB0

**ONLY AD7805 SHOWN FOR CLARITY
**SHOWS ADDITIONAL CHANNELS ON THE AD7809

**PIN ON THE AD7809 ONLY

CONTROL LOGIC

1.23V REF

AV

DD

DIVIDER

CHANNEL D

CONTROL REG

CHANNEL C

CONTROL REG

CHANNEL B

CONTROL REG

CHANNEL A

CONTROL REG

A2**

INPUT SHIFT
REGISTER &

AV

REGISTER

*Patent pending.
Index on Page 26.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] World Wide Web Site: http://www.analog.com
Fax: [phone] © Analog Devices, Inc., 1998

DDDVDD

POWER ON

RESET

DDDVDD

POWER ON

RESET

INPUT

AGND DGND

MUX

DATA

REGISTER

MUX

DATA

REGISTER

MUX

DATA

REGISTER

MUX

DATA

REGISTER

AGND DGND

MUX

DATA

REGISTER

MUX

DATA

REGISTER

MUX

DATA

REGISTER

MUX

DATA

REGISTER

AD7804/
AD7808

V

BIAS

V

BIAS

V

BIAS

V

BIAS

AD7805/
AD7809

V

BIAS

V

BIAS

V

BIAS

V

BIAS

DAC D

DAC

REGISTER

DAC C

DAC

REGISTER

DAC B

DAC

REGISTER

DAC A

DAC

REGISTER

LDACCLR

DAC D

DAC

REGISTER

DAC C

DAC

REGISTER

DAC B

DAC

REGISTER

DAC A

DAC

REGISTER

LDACCLR

V

F*

OUT

V

E*

OUT

V

D

OUT

V

C

OUT

B

V

OUT

V

A

OUT

V

H*

OUT

V

G*

OUT

V

F*

OUT

V

E*

OUT

V

D

OUT

V

C

OUT

B

V

OUT

V

A

OUT

V

H*

OUT

V

G*

OUT

AD7804/AD7805/AD7808/AD7809

AD7804/AD7805–SPECIFICATIONS

Reference = Internal Reference; CL = 100 pF; RL = 2 k⍀ to GND. Sub DAC at Midscale. All specifications T

Parameter B Grade

1

C Grade

(AVDD and DVDD = 3.3 V ⴞ 10% to 5 V ⴞ 10%; AGND = DGND = 0 V;

to T

MIN

1

Units Comments

unless otherwise noted.)

MAX

STATIC PERFORMANCE

MAIN DAC

Resolution 10 10 Bits

Relative Accuracy ±3 ±3 LSB max
Gain Error ±3 ±3 % FSR max

Bias Offset Error
Zero-Scale Error

Monotonicity 9 10 Bits and 200H for Twos Complement Coding

2

3

–80/+40 –80/+40 mV max DAC Code = 0.5 Full Scale

–V

BIAS

/ +40

16

–V

BIAS

/ +40

16

mV max DAC Code = 000H for Offset Binary

Minimum Load Resistance 2 2 kΩ min

SUB DAC

Resolution 8 8 Bits

Differential Nonlinearity ±0.125 ±0.125 LSB typ Refers to an LSB of the Main DAC

±0.5 ±0.5 LSB max

OUTPUT CHARACTERISTICS

Output Voltage Range

3

V

± 15/16 × V

BIAS

V

/16 to 31/16 × V

BIAS

BIAS

BIASVBIAS

V

± 15/16 × V

BIAS

/16 to 31/16 × V

BIAS

V Twos Complement Coding
V Offset Binary Coding

BIAS

Voltage Output Settling Time to 10 Bits 4 4 µs max Typically 1.5 µs
Slew Rate 2.5 2.5 V/µs typ

Digital-to-Analog Glitch Impulse 1 1 nV-s typ 1 LSB Change Around the Major Carry
Digital Feedthrough 0.5 0.5 nV-s typ
Digital Crosstalk 0.5 0.5 nV-s typ

Analog Crosstalk ±0.2 ±0.2 LSB typ
DC Output Impedance 2 2 Ω typ
Power Supply Rejection Ratio 0.002 0.002 %/% typ ∆VDD ± 10%

DAC REFERENCE INPUTS

REF IN Range 1.0 to VDD/2 1.0 to VDD/2 V min to V max

REF IN Input Leakage ±1 ±1 µA max Typically ±1 nA

DIGITAL INPUTS

Input High Voltage, VIH @ VDD = 5 V 2.4 2.4 V min
Input High Voltage, VIH @ VDD = 3.3 V 2.1 2.1 V min
Input Low Voltage, VIL @ VDD = 5 V 0.8 0.8 V max
Input Low Voltage, VIL @ VDD = 3.3 V 0.6 0.6 V max

Input Leakage Current ±10 µA max

Input Capacitance 10 10 pF max
Input Coding Twos Comp/Binary Twos Comp/Binary

REFERENCE OUTPUT

REF OUT Output Voltage 1.23 1.23 V nom

REF OUT Error ±8 ±8 % max
REF OUT Temperature Coefficient –100 –100 ppm/°C typ
REF OUT Output Impedance 5 5 kΩ nom

POWER REQUIREMENTS

VDD (AV
I

DD

and DVDD) 3/5.5 3/5.5 V min to V max

DD

(AI

Plus DIDD) Excluding Load Currents

DD

Normal Mode 12 12 mA max VIH = VDD, VIL = DGND

System Standby (SSTBY) Mode 250 250 µAV

= VDD, VIL = DGND

IH

Power-Down (PD) Mode

@ +25°C 0.8 0.8 µA max V

T

MIN–TMAX

1.5 1.5 µA max

= VDD, VIL = DGND

IH

Power Dissipation Excluding Power Dissipated in Load

Normal Mode 66 66 mW max
System Standby (SSTBY) Mode 1.38 1.38 mW max
Power-Down (PD) Mode

@ +25°C 4.4 4.4 µW max

T

MIN–TMAX

NOTES

1

Temperature range is – 40°C to +85°C.

2

Can be minimized using the Sub DAC.

3

V

is the center of the output voltage swing and can be VDD/2, Internal Reference or REFIN as determined by MX1 and MX0 in the channel control register.

BIAS

Specifications subject to change without notice.

8.25 8.25 µW max

REV. A–2–

AD7804/AD7805/AD7808/AD7809

AD7808/AD7809–SPECIFICATIONS

Reference = Internal Reference; CL = 100 pF; RL = 2 k⍀ to GND. Sub DAC at Midscale. All specifications T

Parameter B Grade

1

(AVDD and DVDD = 3.3 V ⴞ 10% to 5 V ⴞ 10%; AGND = DGND = 0 V;

to T

MIN

Units Comments

unless otherwise noted.)

MAX

STATIC PERFORMANCE

MAIN DAC

Resolution 10 Bits

Relative Accuracy ±4 LSB max
Gain Error ±3 % FSR max

Bias Offset Error

2

±60 mV max DAC Code = 0.5 Full Scale

Zero-Scale Error ±35 mV max DAC Code = 000H for Offset Binary

Monotonicity 9 Bits and 200H for Twos Complement

Minimum Load Resistance 2 kΩ min Coding

SUB DAC

Resolution 8 Bits

Differential Nonlinearity ±0.125 LSB typ Refers to an LSB of the Main DAC

±0.5 LSB max

OUTPUT CHARACTERISTICS

Output Voltage Range

3

V

± 15/16 × V

BIAS

V

/16 to 31/16 × V

BIAS

BIAS

BIAS

V Twos Complement Coding
V Offset Binary Coding

Voltage Output Settling Time to 10 Bits 4 µs max Typically 1.5 µs
Slew Rate 2.5 V/µs typ

Digital-to-Analog Glitch Impulse 1 nV-s typ 1 LSB Change Around the Major Carry
Digital Feedthrough 0.5 nV-s typ
Digital Crosstalk 0.5 nV-s typ

Analog Crosstalk ±0.2 LSB typ
DC Output Impedance 2 Ω typ
Power Supply Rejection Ratio 0.002 %/% typ ∆V

DD

± 10%

DAC REFERENCE INPUTS

REF IN Range 1.0 to VDD/2 V min to V max

REF IN Input Leakage ±1 µA max Typically ±1 nA

DIGITAL INPUTS

Input High Voltage, VIH @ VDD = 5 V 2.4 V min
Input High Voltage, VIH @ VDD = 3.3 V 2.1 V min
Input Low Voltage, VIL @ VDD = 5 V 0.8 V max
Input Low Voltage, VIL @ VDD = 3.3 V 0.6 V max

Input Leakage Current ±10 µA max

Input Capacitance 8 pF max
Input Coding Twos Comp/Binary

REFERENCE OUTPUT

REF OUT Output Voltage 1.23 V nom

REF OUT Error ±8 % max
REF OUT Temperature Coefficient –100 ppm/°C typ
REF OUT Output Impedance 5 kΩ nom

POWER REQUIREMENTS

VDD (AV
I

DD

and DVDD) 3/5.5 V min to V max

DD

(AI

Plus DIDD) Excluding Load Currents

DD

Normal Mode 18 mA max VIH = VDD, VIL = DGND

System Standby (SSTBY) Mode 250 µA max V

= VDD, VIL = DGND

IH

Power-Down (PD) Mode

@ +25°C1µA max V

T

MIN–TMAX

3 µA max

= VDD, VIL = DGND

IH

Power Dissipation Excluding Power Dissipated in Load

Normal Mode 99 mW max
System Standby (SSTBY) Mode 1.38 mW max
Power-Down (PD) Mode

@ +25°C 5.5 µW max

T

MIN–TMAX

NOTES

1

Temperature range is – 40°C to +85°C.

2

Can be minimized using the Sub DAC.

3

V

is the center of the output voltage swing and can be VDD/2, Internal Reference or REFIN as determined by MX1 and MX0 in the channel control register.

BIAS

Specifications subject to change without notice.

16.5 µW max

REV. A

–3–

AD7804/AD7805/AD7808/AD7809

AD7804/AD7808 TIMING CHARACTERISTICS

Internal Reference. All specifications T

MIN

to T

unless otherwise noted.)

MAX

1

(V

= 3.3 V ⴞ 10% to 5 V ⴞ 10%; AGND = DGND = 0 V; Reference =

DD

Limit at T

MIN

, T

MAX

Parameter All Versions Units Description

t

1

t

2

t

3

t

4

t

5

t

6

t

6A

t

7

100 ns min CLKIN Cycle Time
40 ns min CLKIN High Time
40 ns min CLKIN Low Time
30 ns min FSIN Setup Time
30 ns min Data Setup Time
5 ns min Data Hold Time
6 ns min LDAC Hold Time
90 ns max FSIN Hold Time
20 ns min

t

8

t

9

NOTES

1

Sample tested during initial release and after any redesign or process change that may affect this parameter. All input signals are specified with tr = tf = 5 ns and
timed from a voltage of (VIL + VIH)/2.

Specifications subject to change without notice.

CLKIN(I)

FSIN(I)

SDIN(I) DB15

1

LDAC

2

LDAC

40 ns min LDAC, CLR Pulsewidth
100 ns min LDAC Setup Time

t

1

t

2

t

4

t

5

t

6

t

3

t

7

DB0

t

6A

t

5

t

9

t

8

t

CLR

1

TIMING REQUIREMENTS FOR SYNCHRONOUS LDAC UPDATE OR LDAC MAY BE TIED PERMANENTLY LOW IF REQUIRED.

2

TIMING REQUIREMENTS FOR ASYNCHRONOUS LDAC UPDATE.

8

Figure 1. Timing Diagram for AD7804 and AD7808

REV. A–4–

AD7805/AD7809 TIMING CHARACTERISTICS

= Internal Reference. All specifications T

MIN

to T

unless otherwise noted.)

MAX

AD7804/AD7805/AD7808/AD7809

1

(V

= 3.3 V ⴞ 10% to 5 V ⴞ 10%; AGND = DGND = 0 V; Reference

DD

Limit at T

MIN

, T

MAX

Parameter All Versions Unit Description

t

1

t

2

t

3

t

4

t

5

t

6

t

6A

t

7

t

8

t

9

t

10

t

11

t

12

NOTE

1

Sample tested during initial release and after any redesign or process change that may affect this parameter. All input signals are specified with tr = tf = 5 ns and
timed from a voltage of (VIL + VIH)/2.

Specifications subject to change without notice.

MODE

A0, A1, A2

25 ns min Mode Valid to Write Setup Time

4.5 ns min Mode Valid to Write Hold Time
25 ns min Address Valid to Write Setup Time

4.5 ns min Address Valid to Write Hold Time
25 ns min Data Setup Time

4.5 ns min Data Hold Time
6 ns min LDAC Valid to Write Hold Time
40 ns min Chip Select to Write Setup Time
0 ns min Chip Select to Write Hold Time
40 ns min Write Pulsewidth
100 ns min Time Between Successive Writes
40 ns min LDAC, CLR Pulsewidth
100 ns min Write to LDAC Setup Time

t

1

t

2

t

4

t

3

DATA

LDAC

LDAC

CLR

t

t

CS

WR

1

2

1

TIMING REQUIREMENTS FOR SYNCHRONOUS LDAC UPDATE OR LDAC MAY BE TIED PERMANENTLY LOW IF REQUIRED.

2

TIMING REQUIREMENTS FOR ASYNCHRONOUS LDAC UPDATE.

7

t

9

8

t

10

t

6

t

5

t

6A

t

12

t

11

t

11

Figure 2. Timing Diagram for AD7805/AD7809 Parallel Write

–5–REV. A

AD7804/AD7805/AD7808/AD7809

WARNING!

ESD SENSITIVE DEVICE

ABSOLUTE MAXIMUM RATINGS

(T

= +25°C unless otherwise noted)

A

1

DVDD to DGND . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V

to AGND . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V

AV

DD

AGND to DGND . . . . . . . . . . . . . . . . . . . . . . . –0.3 V + 0.3 V

Digital Input Voltage to DGND . . . . . –0.3 V to DV

Analog Input Voltage to AGND . . . . . –0.3 V to AV

COMP to AGND . . . . . . . . . . . . . . . –0.3 V to AV

REF OUT to AGND . . . . . . . . . . . . . . . . . . –0.3 V to + AV

+ 0.3 V

DD

+ 0.3 V

DD

+ 0.3 V

DD

DD

REF IN to AGND . . . . . . . . . . . . . . . –0.3 V to AVDD + 0.3 V

to AGND2 . . . . . . . . . . . . . . . . –0.3 V to AVDD + 0.3 V

V

OUT

Input Current to Any Pin Except Supplies

3

. . . . . . . . ±10 mA

Operating Temperature Range

AD7804/AD7805 Commercial Plastic

(B, C Versions) . . . . . . . . . . . . . . . . . . . . –40°C to +85°C

AD7808/AD7809 Commercial Plastic

(B, C Versions) . . . . . . . . . . . . . . . . . . . . –40°C to +85°C

Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C

Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . +150°C

SOIC (R-16) Package, Power Dissipation . . . . . . . . . 450 mW

Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . 75°C/W

θ

JA

Lead Temperature, Soldering

Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . +215°C

Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . +220°C

PDIP (N-16) Package, Power Dissipation . . . . . . . . . 670 mW

Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 116°C/W

θ

JA

Lead Temperature, Soldering (10 sec) . . . . . . . . . . . +260°C

SOIC (R-24) Package, Power Dissipation . . . . . . . . . 450 mW

Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . 75°C/W

θ

JA

Lead Temperature, Soldering

Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . +215°C

Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . +220°C

PDIP (N-24) Package, Power Dissipation . . . . . . . . . 670 mW

Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 105°C/W

θ

JA

Lead Temperature, Soldering (10 sec) . . . . . . . . . . . +260°C

SOIC (R-28) Package, Power Dissipation . . . . . . . . . 875 mW

Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . 70°C/W

θ

JA

Lead Temperature, Soldering

Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . +215°C

Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . +220°C

PDIP (N-28) Package, Power Dissipation . . . . . . . . . 875 mW

Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . 75°C/W

θ

JA

Lead Temperature, Soldering (10 sec) . . . . . . . . . . . +260°C

SSOP (RS-28) Package, Power Dissipation . . . . . . . . 875 mW

Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 110°C/W

θ

JA

Lead Temperature, Soldering

Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . +215°C

Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . +220°C

TQFP (ST-44B) Package, Power Dissipation . . . . . . 450 mW

Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 116°C/W

θ

JA

Lead Temperature, Soldering

Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . +215°C

Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . +220°C

NOTES

1

Stresses above those listed under Absolute Maximum Ratings may cause perma-

nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.

2

The outputs may be shorted to voltages in this range provided the power dissipation

of the package is not exceeded.

3

Transient currents of up to 100 mA will not cause SCR latch-up.

ORDERING GUIDE

Supply Temperature Relative Package

Model Voltage Range Accuracy Package Descriptions Options

AD7804BN 3.3 V to 5 V –40°C to +85°C ±3 LSB 16-Lead Plastic DIP N-16
AD7804BR 3.3 V to 5 V –40°C to +85°C ±3 LSB 16-Lead Small Outline IC R-16

AD7805BN 3.3 V to 5 V –40°C to +85°C ±3 LSB 28-Lead Plastic DIP N-28
AD7805BR 3.3 V to 5 V –40°C to +85°C ±3 LSB 28 Lead Small Outline IC R-28
AD7805BRS 3.3 V to 5 V –40°C to +85°C ±3 LSB 28-Lead Shrink Small Outline Package RS-28
AD7805CR 3.3 V to 5 V –40°C to +85°C ±3 LSB 28-Lead Small Outline IC R-28

AD7808BN 3.3 V to 5 V –40°C to +85°C ±4 LSB 24-Lead Plastic DIP N-24
AD7808BR 3.3 V to 5 V –40°C to +85°C ±4 LSB 24 Lead Small Outline IC R-24
AD7809BST 3.3 V to 5 V –40°C to +85°C ±4 LSB 44-Lead Thin Plastic Quad Flatpack (TQFP) ST-44B

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although these devices feature proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.

REV. A–6–

AD7804/AD7805/AD7808/AD7809

AD7804/AD7808 PIN FUNCTION DESCRIPTION

AD7804 AD7808

Pin No. Pin No. Mnemonic Description

1 1, 6 AGND Ground reference point for analog circuitry.

2, 3 2, 3 V

4 4 REFOUT Reference Output. This is a bandgap reference and is typically 1.23 V.

5 PD Active low input used to put the part into low power mode reducing current consumption

7, 8 V

59FSIN Level-triggered control input (active low). This is the frame synchronization signal for the

610LDAC LDAC Input. When this digital input is taken low, all DAC registers are simultaneously

7 11 SDIN Serial Data Input. These devices accept a 16-bit word. Data is clocked into the input shift

8 12 DGND Ground reference point for digital circuitry.

913DV

10 14 CLKIN Clock Input. Data is clocked into the input shift register on the falling edges of CLKIN.

11 15 CLR Asynchronous CLR Input. When this input is taken low, all Main DAC outputs are

16 NC No Connect. This pin should be left open circuit.
17, 18 V

12 20 REFIN This is an external reference input for the DACs. When this reference is selected for a

13 21 COMP Compensation Pin. This pin provides an output from the internal V

14, 15 22, 23 V

16 19, 24 AV

OUT

OUT

OUT

OUT

DD

DD

B, V

F, V

H, V

D, V

A Analog output voltage from the DACs.

OUT

to 1 µA.

E Analog output voltages from the DACs.

OUT

input data. When FSIN goes low, it enables the input shift register and data is transferred
on the falling edges of CLKIN.

updated with the contents of the data registers. If LDAC is tied permanently low, or is
low on the sixteenth falling clock edge with timing similar to that of SDIN, an automatic
update will take place.

register on the falling edge of CLKIN.

Digital Power Supply.

Duty Cycle should be between 40% and 60%.

cleared either to V

BIAS

or to V

BIAS

transfer function of the Main DAC will remain centered around the V

G Analog output voltages from the DACs.

OUT

DAC in the control register, the analog output from the selected DAC swings around this
point.

provided for ac bypass purposes only. This pin should be decoupled with 1 nF capacitors
to both AV

and AGND. This pin can be overdriven with an external reference, thus

DD

giving the facility for two external references on the part.

C Analog output voltage from the DACs.

OUT

Analog Power Supply. +3.3 V to +5 V.

/16 volts. All Sub DACs are also cleared and thus the

point.

BIAS

/2 divider and is

DD

AD7804 PIN CONFIGURATION

AGND

V

OUT

V

OUT

REFOUT

FSIN

LDAC

SDIN

DGND

1

B

2

3

A

4

5

6

7

8

AD7804

TOP VIEW

(Not to Scale)

16

15

14

13

12

11

10

9

AV

DD

V

OUT

V

OUT

COMP
REFIN

CLR

CLKIN
DV

DD

C
D

AD7808 PIN CONFIGURATION

AGND

V

OUT

V

OUT

REFOUT

AGND

V

OUT

V

OUT

FSIN

LDAC

SDIN

DGND

1
2

B

3

A

4
5

PD

AD7808

6

TOP VIEW

(Not to Scale)

7

F

8

E

9
10
11
12

NC = NO CONNECT

24

AV

DD

23

V

C

OUT

22

D

V

OUT

21

COMP

20

REFIN

19

AV

DD

18

V

G

OUT

17

V

H

OUT

16

NC

15

CLR

14

CLKIN

13

DV

DD

–7–REV. A

AD7804/AD7805/AD7808/AD7809

44 43 42 41 40 39 38 37 36 35 34

1
2
3
4
5
6
7
8

9
10
11

12 13 14 15 16 17 18 19 20 21 22

33
32
31
30
29
28
27
26
25
24
23

PIN 1
IDENTIFIER

TOP VIEW

(Not to Scale)

NC = NO CONNECT

NC
REFIN
MODE
A0
A1
AV

DD

A2
DB0
V

OUT

G
DB1
DB2

NC

AGND

DB9
DB8

AGND

DB7
DB6

V

OUT

F
DB5
DB4

NC

PD

REFOUT

V

OUT

A

V

OUT

B

AGND

AGND

AV

DD

V

OUT

E

NC

LDAC

DB3

DV

DD

WR

CLR

NC

CS

V

OUT

H

DGND

AV

DD

V

OUT

C

V

OUT

D

COMP

AD7809

AD7805/AD7809 PIN FUNCTION DESCRIPTIONS

AD7805 AD7809
Pin No. Pin No. Mnemonic Description

1, 11, 13, NC No Connect. These pins should be left open circuit.

20, 33
1 2, 5, 39, 40 AGND Ground reference point for analog circuitry.
2, 3 41, 42 V

4 43 REFOUT Reference Output. This is a bandgap reference and is typically 1.23 V.
5–10, 3, 4, 6, 7, 9, DB9–DB2 Data Inputs. DB9 to DB2 are the 8 MSBs of the data word.

12, 13 10, 15, 23
19, 20 24, 26 DB1, DB0 DB1 and DB0 function as the 2 LSBs of the 10-bit word in 10-bit parallel mode but

8, 12 V
11 14 LDAC LDAC Input. When this digital input is taken low, all DAC registers are simultaneously

14 16 DGND Ground reference point for digital circuitry.
15 17 DV
16 18 WR Write Input WR is an active low logic input which is used in conjunction with CS and

17 21 CS Chip Select. Active low logic input.
18 19 CLR Asynchronous CLR Input. When this input is taken low, all Main DAC outputs are

22, 25 V
21, 22 27, 29, 30 A2, A1, A0 DAC Address Inputs. These digital inputs are used in conjunction with CS and WR to

23 31 MODE Logic Input. Logic high enables writing to the DAC data registers, a logic low enables

24 32 REFIN This is an external reference input for the DAC. When this reference is selected for the DAC

25 34 COMP Compensation Pin. This pin provides an output from the internal V

26, 27 35, 36 V
28 28, 37, 38 AV

44 PD Active low input used to put the part into low power mode reducing current consump-

OUT

OUT

OUT

OUT

DD

DD

B, V

F, V

H, V

D, V

A Analog output voltages from the DACs.

OUT

have other functions when BYTE loading structure is used.

E Analog output voltages from the DACs.

OUT

updated with the contents of the DAC data registers. If LDAC is permanently tied low, or is
low during the rising edge of WR similar to data inputs, an automatic update will take place.

Digital Power Supply.

the address pins to write data to the relevant registers.

cleared either to V

BIAS

or to V

BIAS

transfer function of the MAIN DAC will remain centered around the V

G Analog output voltages from the DACs.

OUT

determine which DAC channel control register or DAC data register is loaded from the
input register. These address bits are don’t cares when writing to the system control register.

writing to the control registers.

in the control register, the analog output from the selected DAC swings around this point.

provided for ac bypass purposes only. This pin should be decoupled with 1 nF capacitors
to both AV

and AGND. This pin can be overdriven with an external reference, thus

DD

giving the facility for two external references on the part.

C Analog output voltages from the DACs.

OUT

Analog Power Supply.

tion to 1 µA.

/16 volts. All Sub DACs are also cleared and thus the

point.

BIAS

/2 divider and is

DD

AD7805 PIN CONFIGURATION

1

AGND

2

B

V

OUT

3

V

A

OUT

DB9

DB8
DB7
DB6
DB5
DB4

LDAC

DB3
DB2

DGND

4
5
6

AD7805

7

TOP VIEW

(Not to Scale)

8

9
10
11
12
13
14

REFOUT

AD7809 PIN CONFIGURATION

28

AV

DD

27

V

C

OUT

V

D

26

OUT

25

COMP

24

REFIN
MODE

23

A0

22

A1

21

DB0

20

DB1

19
18

CLR

17

CS

16

WR

15

DV

DD

REV. A–8–

AD7804/AD7805/AD7808/AD7809

TERMINOLOGY
Relative Accuracy

For the DACs, relative accuracy or endpoint nonlinearity is a
measure of the maximum deviation, in LSBs, from a straight
line passing through the endpoints of the DAC transfer func­tion. Figures 32 and 33 show the linearity at 3 V and 5 V
respectively.

Differential Nonlinearity

Differential nonlinearity is the difference between the measured
change and the ideal 1 LSB change between any two adjacent

codes. A specified differential nonlinearity of ±1 LSB maxi-

mum ensures monotonicity.

Bias Offset Error

If the DACs are ideal, the output voltage of any DAC with
midscale code loaded will be equal to V

BIAS

where V

BIAS

is se­lected by MX1 and MX0 in the control register. The DAC bias
offset error is the difference between the actual output voltage
and V

, expressed in mV.

BIAS

Gain Error

The difference between the actual and ideal analog output
range, expressed as a percent of full-scale range. It is the devia­tion in slope of the DAC transfer characteristic from ideal.

Zero-Scale Error

The zero-scale error is the actual output minus the ideal output
from any DAC when zero code is loaded to the DAC. If offset
binary coding is used, the code loaded is 000Hex, and if twos
complement coding is used, a code of 200HEX is loaded to the
DAC to calculate the zero-scale error. Zero-scale error is ex­pressed in mV.

Digital-to-Analog Glitch Impulse

Digital-to-analog glitch impulse is the impulse injected into the
analog output when the digital inputs change state with the
DAC selected and the LDAC used to update the DAC. It is
normally specified as the area of the glitch in nV-s and is mea­sured when the digital input code is changed by 1 LSB at the
major carry transition. Regardless of whether offset binary or twos
complement coding is used, the major carry transition occurs at
the analog output voltage change of V

BIAS

to V

– 1 LSB

BIAS

or vice versa.

Digital Feedthrough

Digital feedthrough is a measure of the impulse injected into
the analog output of a DAC from the digital inputs of the same
DAC but is measured when the DAC is not updated. It is speci­fied in nV secs and is measured with a full-scale code change on
the data bus, i.e., from all 0s to all 1s and vice versa.

Digital Crosstalk

Digital crosstalk is the glitch impulse transferred to the output
of one converter due to a digital code change to another DAC.
It is specified in nV-s.

Analog Crosstalk

Analog crosstalk is a change in output of any DAC in response
to a change in the output of one or more of the other DACs. It
is measured in LSBs.

Power Supply Rejection Ratio (PSRR)

This specification indicates how the output of the DAC is af­fected by changes in the power supply voltage. Power-supply
rejection ratio is quoted in terms of % change in output per %
change in V

for full-scale output of the DAC. VDD is varied

DD

±10%.

AD7804/AD7808 INTERFACE SECTION

The AD7804 and AD7808 are serial input devices. Three lines
control the serial interface, FSIN, CLKIN and SDIN. The timing
diagram is shown in Figure 1.

Two mode bits (MD1 and MD0) which are DB13 and DB14 of
the serial word written to the AD7804/AD7808 are used to deter­mine whether writing is to the DAC data registers or the control
registers of the device. These parts contain a system control
register for controlling the operation of all DACs in the package
as well as a channel control register for controlling the operation of
each individual DAC. Table I shows how to access these registers.

Table I. Register Selection Table for the AD7804/AD7808

MD1 MD0 Function

0 0 Write enable to system control register.
0 1 Write enable to channel control register.
1 X Write enable to DAC data registers.

When the FSIN input goes low, data appearing on the SDIN
line is clocked into the input register on each falling edge of
CLKIN. Data to be transferred to the AD7804/AD7808 is
loaded MSB first. Figure 4 shows the loading sequence for the
AD7804/AD7808 system control register, Figure 5 shows the

sequence for the channel control register write, and Figures 6
and 7 show the sequence for loading data to the Main and Sub
DAC data registers. Figure 3 shows the internal registers associ­ated with the AD7804/AD7808 serial interface DACs. Only one
DAC structure is shown for clarity.

FSIN

CLKIN
SDIN

DATA REGISTER

8

DAC REGISTER

8

8-BIT DAC
(SUB DAC)

SYSTEM
CONTROL
REGISTER

TO ALL

CHANNELS

SINGLE

CHANNEL

INTERNAL V

REFIN

V

OUT

REF

VDD/2

16-BIT

INPUT SHIFT REGISTER

DECODER

CHANNEL
CONTROL
REGISTER

MUX

V

BIAS

DATA REGISTER

DAC REGISTER

10

10

10-BIT DAC
(MAIN DAC)

Figure 3. AD7804/AD7808 Internal Registers

–9–REV. A