Analog Devices AD7801BRU, AD7801BR Datasheet

+2.7 V to +5.5 V, Parallel Input,

a

FEATURES
Single 8-Bit DAC
20-Pin SOIC/TSSOP Package
+2.7 V to +5.5 V Operation
Internal and External Reference Capability
DAC Power-Down Function
Parallel Interface
On-Chip Output Buffer Rail-to-Rail Operation
Low Power Operation 1.75 mA max @ 3.3 V
Power-Down to 1 mA max @ 258C

APPLICATIONS
Portable Battery Powered Instruments
Digital Gain and Offset Adjustment
Programmable Voltage and Current Sources
Programmable Attenuators

GENERAL DESCRIPTION

The AD7801 is a single, 8-bit, voltage out DAC that operates
from a single +2.7 V to +5.5 V supply. Its on-chip precision output
buffer allows the DAC output to swing rail to rail. The AD7801
has a parallel microprocessor and DSP compatible interface with
high speed registers and double buffered interface logic. Data is
loaded to the input register on the rising edge of CS or WR.

Reference selection for the AD7801 can be either an internal
reference derived from the V
at the REFIN pin. The output of the DAC can be cleared by
using the asynchronous CLR input.

The low power consumption of this part makes it ideally suited
to portable battery operated equipment. The power consump­tion is less than 5 mW at 3.3 V, reducing to less than 3 µW in
power-down mode.

The AD7801 is available in a 20-lead SOIC and a 20-lead
TSSOP package.

or an external reference applied

DD

Voltage Output 8-Bit DAC

AD7801

FUNCTIONAL BLOCK DIAGRAM

D7
D0

WR

CS

PRODUCT HIGHLIGHTS

1. Low Power, Single Supply operation. This part operates
from a single +2.7 V to +5.5 V supply and consumes typically
5 mW at 3 V, making it ideal for battery powered applications.

2. The on-chip output buffer amplifier allows the output of the
DAC to swing rail to rail with a settling time of typically 1.2 µs.

3. Internal or external reference capability.

4. High speed parallel interface.

5. Power-down capability. When powered down the DAC
consumes less than 1 µA at 25°C.

6. Packaged in 20-lead SOIC and TSSOP packages.

INPUT

REGISTER

CONTROL

LOGIC

PD CLR LDAC

REGISTER

AD7801

DAC

I DAC

MUX

REFIN V

POWER-ON

RESET

÷

2

DD

I/V

DGND

V

OUT

AGND

REV. 0

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] World Wide Web Site: http://www.analog.com
Fax: [phone] © Analog Devices, Inc., 1997

(V

= +2.7 V to +5.5 V, Internal Reference; CL = 100 pF, RL = 10 kV to VDD and GND.

DD

AD7801–SPECIFICA TIONS

All specifications T

Parameter B Versions

1

to T

MIN

unless otherwise noted.)

MAX

Units Conditions/Comments

STATIC PERFORMANCE

Resolution 8 Bits
Relative Accuracy

2

±1 LSB max
Differential Nonlinearity ±1 LSB max Guaranteed Monotonic
Zero-Code Error @ +25°C 3 LSB typ All Zeros Loaded to DAC Register
Full-Scale Error –0.75 LSB typ All Ones Loaded to DAC Register
Zero-Code Error Drift 100 µV/°C typ
Gain Error

3

±1 % FSR typ

DAC REFERENCE INPUT

REFIN Input Range 1 to V

/2 V min/V max

DD

REFIN Input Impedance 10 MΩ typ

OUTPUT CHARACTERISTICS

Output Voltage Range 0 to V

DD

V min/V max
Output Voltage Settling Time 2 µs max Typically 1.2 µs
Slew Rate 7.5 V/µs typ
Digital-to-Analog Glitch Impulse 1 nV-s typ 1 LSB Change Around Major Carry
Digital Feedthrough 0.2 nV-s typ
DC Output Impedance 40 Ω typ
Short Circuit Current 14 mA typ
Power Supply Rejection Ratio

4

0.0003 %/% max ∆VDD = ±10%

LOGIC INPUTS

Input Current ±10 µA max

, Input Low Voltage 0.8 V max VDD = +5 V

V

INL

, Input Low Voltage 0.6 V max VDD = +3 V

V

INL

, Input High Voltage 2.4 V min VDD = +5 V

V

INH

, Input High Voltage 2.1 V min VDD = +3 V

V

INH

Pin Capacitance 7 pF max

POWER REQUIREMENTS

V

DD

(Normal Mode) DAC Active and Excluding Load Current

I

DD

= 3.3 V VIH = VDD and VIL = GND

V

DD

2.7/5.5 V min/V max

@ 25°C 1.55 mA max See Figure 6
T

V

DD

to T

MIN

= 5.5 V

MAX

1.75 mA max

@ 25°C 2.35 mA max

to T

T

MIN

(Power-Down)

I

DD

MAX

@ 25°C1µA max V

T

to T

MIN

NOTES

1

Temperature ranges are as follows: B Version: –40°C to +105 °C

2

Relative Accuracy is calculated using a reduced code range of 15 to 245.

3

Gain Error is specified between Codes 15 and 245. The actual error at Code 15 is typically 3 LSB.

4

Guaranteed by characterization at product release, not production tested.

Specifications subject to change without notice.

MAX

2.5 mA max
= VDD and VIL = GND

IH

2 µA max See Figure 18

CS

WR

D7-D0

LDAC

CLR

t

1

t

t

2

3

t

t

4

5

t

6

t

7

t

8

Figure 1. Timing Diagram for Parallel Data Write

–2–

REV. 0

AD7801

WARNING!

ESD SENSITIVE DEVICE

(VDD = +2.7 V to +5.5 V; GND = 0 V; Internal VDD/2 Reference. All specifications T

TIMING CHARACTERISTICS

Limit at T

1, 2

unless otherwise noted.)

, T

MIN

MAX

Parameter (B Version) Units Conditions/Comments

t

1

t

2

t

3

t

4

t

5

t

6

t

7

t

8

NOTES

1

Sample tested at +25°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of VDD) and timed from a voltage level of
(VIL + VIH)/2. tr and tf should not exceed 1 µs on any digital input.

2

See Figure 1.

ABSOLUTE MAXIMUM RATINGS*

(TA = +25°C unless otherwise noted)

VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V

Reference Input Voltage to AGND . . . .–0.3 V to V

Digital Input Voltage to DGND . . . . . .–0.3 V to V

AGND to DGND . . . . . . . . . . . . . . . . . . . . .–0.3 V to +0.3 V

V

to AGND . . . . . . . . . . . . . . . . . . –0.3 V to VDD + 0.3 V

OUT

Operating Temperature Range

0 ns min Chip Select to Write Setup Time
0 ns min Chip Select to Write Hold Time
20 ns min Write Pulse Width
15 ns min Data Setup Time

4.5 ns min Data Hold Time
20 ns min Write to LDAC Setup Time
20 ns min LDAC Pulse Width
20 ns min CLR Pulse Width

ORDERING GUIDE

Temperature Package

+ 0.3 V

DD

+ 0.3 V

DD

Model Range Option*

AD7801BR –40°C to +105°C R-20
AD7801BRU –40°C to +105°C RU-20

*R = Small Outline; RU = Thin Shrink Small Outline.

Commercial (B Version) . . . . . . . . . . . . . –40°C to +105°C

Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C

Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . .+150°C

SSOP Package, Power Dissipation . . . . . . . . . . . . . . . 700 mW

θ

Thermal Impedance . . . . . . . . . . . . . . . . . . . . 143°C/W

JA

Lead Temperature, Soldering

Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . .+215°C

Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . .+220°C

SOIC Package, Power Dissipation . . . . . . . . . . . . . . . 870 mW

θ

Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 74°C/W

JA

Lead Temperature, Soldering

Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . .+215°C

Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . .+220°C

MIN

to T

MAX

*Stresses above those listed under Absolute Maximum Ratings may cause perma-

nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD7801 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.

REV. 0

–3–

AD7801

PIN CONFIGURATION

(MSB) DB7

(LSB) DB0

1
2

DB6

3

DB5

4

DB4

5

AD7801

TOP VIEW

DB2

6

(Not to Scale)

DB1

7
8
9

CS

10

WR DGND

NC = NO CONNECT

20

DGND

19

V

OUT

18

NC

17

AGND

16

REFINDB3

15

V

DD

14

CLR

13

LDAC

12

PD

11

PIN FUNCTION DESCRIPTIONS

Pin
No. Mnemonic Function

1–8 D7–D0 Parallel Data Inputs. 8-bit data is loaded to the input register of the AD7801 under the control of CS and WR.
9 CS Chip Select. Active low logic input.
10 WR Write Input. WR is an active low logic input used in conjunction with CS to write data to the input register.
11 DGND Digital Ground
12 PD Active low input used to put the part into low power mode reducing current consumption to less than 1 µA.
13 LDAC Load DAC Logic Input. When this logic input is taken low the DAC output is updated with the contents of

its DAC register. If LDAC is permanently tied low the DAC is updated on the rising edge of WR.

14 CLR Asynchronous Clear Input (Active Low). When this input is taken low the DAC register is loaded with all

zeroes and the DAC output is cleared to zero volts.

15 V

DD

Power Supply Input. This part can be operated from +2.7 V to +5.5 V and should be decoupled to GND.

16 REFIN External Reference Input. This can be used as the reference for the DAC. The range on this reference input is

1 V to V

/2. If REFIN is tied directly to VDD the internal VDD/2 reference is selected.

DD

17 AGND Analog Ground reference point and return point for all analog current on the part.
18 NC No Connect Pin.
19 V

OUT

Analog Output Voltage from the DAC. The output amplifier can swing rail to rail on its output.

20 DGND Digital Ground reference point and return point for all digital current on the part.

–4–

REV. 0

Typical Performance Characteristics–

5

800

VDD = 5V AND 3V

720

INTERNAL REFERENCE

640

T

= +25 C

A

DAC LOADED WITH 00HEX

560
480
400

– mV

OUT

320

V

240
160

80

0

08

24 6

SINK CURRENT – mA

4.92

4.84

4.76

4.68

4.6

Volts
–

4.52

OUT

V

= 5V

DD

V

4.44

INTERNAL REFERENCE
DAC REGISTER LOADED

4.36

WITH FFHEX
T

= +25°C

A

4.28

4.2
02 846

SOURCE CURRENT – mA

AD7801

3.5

3.25

3.0

2.75

2.5

2.25

– Volts

2.0

OUT

V

VDD = 3V

1.75
INTERNAL REFERENCE
DAC REGISTER LOADED

1.5
WITH FFHex

1.25

T

= +25°C

A

1.0

01 8234567

SOURCE CURRENT – mA

Figure 2. Output Sink Current Capa­bility with V

0.5

0.45

0.4

0.35

0.3

0.25

0.2

ERROR – LSBs

0.15

0.1

0.05
0

1.0 1.2 2.8

= 3 V and VDD = 5 V

DD

VDD = 5V

= +25 C

T

A

INL ERROR

DNL ERROR

1.4 1.6 1.8 2.2 2.4 2.62.0

REFERENCE VOLTAGE – Volts

Figure 5. Relative Accuracy vs.
External Reference

10

5
0

–5
–10
–15
–20
–25

ATTENUATION – dB

VDD = 5V

–30

EXTERNAL SINEWAVE REFERENCE
DAC REGISTER LOADED WITH FFHEX

–35

T

= +25°C

A

–40

1 10 10k100 1k

FREQUENCY – Hz

Figure 8. Large Scale Signal
Frequency Response

Figure 3. Output Source Current
Capability with V

4.0

3.5

3.0

2.5

2.0

– mA

DD

I

1.5

1.0

0.5

0
–50 –25

INTERNAL REFERENCE
LOGIC INPUTS = V
DAC ACTIVE

TEMPERATURE – C

= 5 V

DD

OR GND

DD

VDD = 5.5V

VDD = 3.3V

0 255075 125

100

Figure 6. Typical Supply Current
vs. Temperature

WR

T

1

←

←

2

V

OUT

3

←

CH1 5V, CH2 1V, CH3 20mV

TIME BASE = 200 ns/Div

V

OUT

VDD = 3V
INTERNAL VOLTAGE

REFERENCE
FULL SCALE CODE
CHANGE 00H-FFH
T

= +25°C

A

←

Figure 9. Full-Scale Settling Time

Figure 4. Output Source Current
Capability with V

4.0
DAC ACTIVE
INTERNAL REFERENCE
T

= +25°C

A

3.0

LOGIC INPUTS = VIH OR V

2.0

– mA

DD

I

1.0

0

2.5 3.0 5.53.5 4.0 4.5 5.0

LOGIC INPUTS = V

= 3 V

DD

VDD – Volts

IL

OR GND

DD

Figure 7. Typical Supply Current
vs. Supply Voltage

PD

2

←

V

OUT

←

1

AD7801 POWER-UP TIME

= 5V

V

DD

INTERNAL REFERENCE
DAC IN POWER-DOWN INITIALLY

CH1 = 2V/div, CH2 = 5V/Div,

TIME BASE = 2 µs/Div

Figure 10. Exiting Power-Down (Full
Power-Down)

REV. 0

–5–