Analog Devices AD7798 9 Datasheet

3-Channel, Low Noise, Low Power, 16-/24-Bit

FEATURES

RMS noise:

27 nV at 4.17 Hz (AD7799)
65 nV at 16.7 Hz (AD7799)
40 nV at 4.17 Hz (AD7798)

85 nV at 16.7 Hz (AD7798)
Current: 380 µA typ
Power-down: 1 µA max
Low noise programmable gain instrumentation-amp
Update rate: 4.17 Hz to 500 Hz
3 differential inputs
Internal clock oscillator
Simultaneous 50 Hz/60 Hz rejection
Reference Detect
Low-side power switch
Programmable digital outputs
Burnout currents
Power supply: 2.7 V to 5.25 V
–40°C to +105°C temperature range
Independent interface power supply
16-lead TSSOP package

INTERFACE

3-wire serial
SPI®-, QSPI™-, MICROWIRE™-, and DSP-compatible
Schmitt trigger on SCLK

APPLICATIONS

Weigh scales
Pressure measurement
Strain gauge transducers
Gas analysis
Industrial process control
Instrumentation
Portable instrumentation
Blood analysis
Smart transmitters
Liquid/gas chromotography
6-digit DVM

Sigma-Delta ADC with On-Chip In-Amp

AD7798/AD7799

FUNCTIONAL BLOCK DIAGRAM

GND AV

DD

AD7798/AD7799

AIN1(+)
AIN1(–)
AIN2(+)

AIN2(–)
AIN3(+)/P1
AIN3(–)/P2

PSW

GND

MUX

AV

GND

DD

IN-AMP

INTERNAL

CLOCK

Figure 1.

GENERAL DESCRIPTION

The AD7798/AD7799 are low power, low noise, complete
analog front ends for high precision measurement applications.
The AD7798/AD7799 contains a low noise, 16-/24-bit ∑-∆
ADC with three differential analog inputs. The on-chip, low
noise instrumentation amplifier means that signals of small
amplitude can be interfaced directly to the ADC. With a gain
setting of 64, the rms noise is 27 nV for the AD7799 and 40 nV
for the AD7798 when the update rate equals 4.17 Hz.

On-chip features include a low-side power switch, reference
detect, programmable digital output pins, burnout currents,
and an internal clock oscillator. The output data rate from the
part is software-programmable and can be varied from 4.17 Hz
to 500 Hz.

The part operates with a power supply from 2.7 V to 5.25 V.
The AD7798 consumes a current of 300 µA typical, whereas the
AD7799 consumes 380 µA typical. Both devices are housed in a
16-lead TSSOP package.

REFIN(+)

Σ-∆

ADC

REFIN(–)

AD7798: 16-BIT
AD7799: 24-BIT

REFERENCE

DETECT

SERIAL

INTERFACE

AND

CONTROL

LOGIC

DOUT/RDY
DIN
SCLK
CS

DV

DD

04856-001

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] © 2005 Analog Devices, Inc. All rights reserved.

AD7798/AD7799

TABLE OF CONTENTS

Specifications..................................................................................... 3

Timing Characteristics..................................................................... 6

Absolute Maximum Ratings............................................................ 8

ESD Caution.................................................................................. 8

Pin Configuration and Function Descriptions............................. 9

Output Noise and Resolution Specifications .............................. 10

AD7798........................................................................................ 10

AD7799........................................................................................ 11

Typical Performance Characteristics ...........................................12

On-Chip Registers.......................................................................... 13

Communication Register ..........................................................13

Status Register............................................................................. 14

Mode Register ............................................................................. 14

Configuration Register ..............................................................16

Data Register............................................................................... 17

ADC Circuit Information.............................................................. 19

Overview ..................................................................................... 19

Digital Interface.......................................................................... 20

Circuit Description......................................................................... 23

Analog Input Channel............................................................... 23

Instrumentation Amplifier........................................................ 23

Bipolar/Unipolar Configuration .............................................. 23

Data Output Coding .................................................................. 24

Burnout Currents....................................................................... 24

Reference ..................................................................................... 24

Reference Detect......................................................................... 24

Reset ............................................................................................. 25

AV

Monitor ............................................................................. 25

DD

Calibration................................................................................... 25

Grounding and Layout.............................................................. 26

ID Register................................................................................... 17

IO Register................................................................................... 17

Offset Register............................................................................. 18

Full-Scale Register ...................................................................... 18

REVISION HISTORY

1/05—Revision 0: Initial Version

Applications..................................................................................... 27

Weigh Scales................................................................................ 27

Outline Dimensions....................................................................... 28

Ordering Guide .......................................................................... 28

Rev. 0 | Page 2 of 28

AD7798/AD7799

SPECIFICATIONS

AVDD = 2.7 V to 5.25 V; DVDD = 2.7 V to 5.25 V; GND = 0 V; REFIN(+) = AVDD; REFIN(−) = 0 V. All specifications T
otherwise noted.

Table 1.

Parameter AD7798B/AD7799B1 Unit Test Conditions/Comments

ADC CHANNEL

Output Update Rate 4.17 − 500 Hz nom
No Missing Codes2 24 Bits min AD7799: f

< 250 Hz

ADC

16 Bits min AD7798
Resolution See Table 5 to Table 8
Output Noise and Update Rates See Table 5 to Table 8
Integral Nonlinearity ±15 ppm of FSR max
Offset Error3 ±1 µV typ
Offset Error Drift vs. Temperature4 ±10 nV/°C typ
Full-Scale Error

3, 5

±10 µV typ
Gain Drift vs. Temperature4 ±1 ppm/°C typ
Power Supply Rejection 100 dB min AIN = 1 V/gain, gain ≥ 4

ANALOG INPUTS

Differential Input Voltage Ranges ±V

/gain V nom V

REF

= REFIN(+) – REFIN(–), gain = 1 to 128

REF

Absolute AIN Voltage Limits2

MIN

to T

MAX

, unless

Unbuffered Mode GND − 30 mV V min Gain = 1 or 2
AVDD + 30 mV V max
Buffered Mode GND + 100 mV V min Gain = 1 or 2
AVDD – 100 mV V max
In-Amp Active GND + 300 mV V min Gain = 4 to 128
AVDD − 1.1 V max
Common-Mode Voltage, VCM 0.5 V min VCM = (AIN(+) + AIN(−))/2, gain = 4 to 128

Analog Input Current

Buffered Mode or In-Amp Active

Average Input Current2 ±1 nA max Gain = 1 or 2, update rate < 100 Hz
±250 pA max Gain = 4 to 128, update rate < 100 Hz
±1 nA max AIN3(+)/AIN3(−), update rate < 100 Hz
Average Input Current Drift ±2 pA/°C typ

Unbuffered Mode Gain = 1 or 2

Average Input Current ±400 nA/V typ Input current varies with input voltage
Average Input Current Drift ±50 pA/V/°C typ

Normal-Mode Rejection2

@ 50 Hz, 60 Hz 65 dB min 80 dB typ, 50 ± 1 Hz, 60 ± 1 Hz (FS[3:0] = 1010)6
@ 50 Hz 80 dB min 90 dB typ, 50 ± 1 Hz (FS[3:0] = 1001)6
@ 60 Hz 90 dB min 100 dB typ, 60 ± 1 Hz (FS[3:0] = 1000)6

Common-Mode Rejection

@ DC 100 dB min AIN = 1 V/gain, gain ≥4
@ 50 Hz, 60 Hz2 100 dB min 50 ± 1 Hz, 60 ± 1 Hz (FS[3:0] = 1010)6
@ 50 Hz, 60 Hz2 100 dB min

50 ± 1 Hz (FS[3:0] = 1001
(FS[3:0] = 1000

6

)

6

), 60 ± 1 Hz

Rev. 0 | Page 3 of 28

AD7798/AD7799

Parameter AD7798B/AD7799B1 Unit Test Conditions/Comments

REFERENCE

External REFIN Voltage 2.5 V nom REFIN = REFIN(+) − REFIN(−)
Reference Voltage Range2 0.1 V min
AVDD V max

When V

limited to (0.9 x V
Absolute REFIN Voltage Limits2 GND − 30 mV V min
AV

+ 30 mV V max

DD

Average Reference Input Current 400 nA/V typ
Average Reference Input Current Drift ±0.03 nA/V/°C typ
Normal-Mode Rejection

Same as for analog

inputs
Common-Mode Rejection 100 dB typ
Reference Detect Levels 0.3 V min

0.65 V max NOXREF bit active if V

LOW-SIDE POWER SWITCH

RON 7 Ω max AVDD = 5 V
9 Ω max AVDD = 3 V
Allowable Current2 30 mA max Continuous current

DIGITAL OUTPUTS (P1 and P2)

Output High Voltage, V

Output Low Voltage, V

Output High Voltage, V
Output Low Voltage, V

2

AVDD − 0.6 V min AVDD = 3 V, I

OH

2

0.4 V max AVDD = 3 V, I

OL

2

4 V min AVDD = 5 V, I

OH

2

0.4 V max AVDD = 5 V, I

OL

INTERNAL CLOCK

Frequency2 64 ± 3% kHz min/max

LOGIC INPUTS

CS2

Input Low Voltage, V

Input High Voltage, V

SCLK and DIN

(Schmitt-Triggered Input)

0.8 V max DVDD = 5 V

INL

INH

2

0.4

2.0

V max
V min

DV
DV

VT(+) 1.4/2 V min/max DVDD = 5 V
VT(–) 0.8/1.7 V min/max DVDD = 5 V
VT(+) – VT(–) 0.1/0.17 V min/max DVDD = 5 V
VT(+) 0.9/2 V min/max DVDD = 3 V
VT(–) 0.4/1.35 V min/max DVDD = 3 V

VT(+) − VT(–) 0.06/0.13 V min/max DVDD = 3 V
Input Currents ±10 µA max VIN = DVDD or GND
Input Capacitance 10 pF typ All digital inputs

LOGIC OUTPUTS

Output High Voltage, V
Output Low Voltage, V
Output High Voltage, V
Output Low Voltage, V

2

DVDD − 0.6 V min DVDD = 3 V, I

OH

2

0.4 V max DVDD = 3 V, I

OL

2

4 V min DVDD = 5 V, I

OH

2

0.4 V max DVDD = 5 V, I

OL

Floating-State Leakage Current ±10 µA max
Floating-State Output Capacitance 10 pF typ
Data Output Coding Offset binary

= AVDD, the differential input must be

REF

= 3 V

DD

= 3 V or 5 V

DD

/gain) if the in-amp is active.

REF

< 0.3 V

REF

= 100 µA

SOURCE

= 100 µA

SINK

= 200 µA

SOURCE

= 800 µA

SINK

= 100 µA

SOURCE

= 100 µA

SINK

= 200 µA

SOURCE

= 1.6 mA

SINK

Rev. 0 | Page 4 of 28

AD7798/AD7799

Parameter AD7798B/AD7799B1 Unit Test Conditions/Comments

SYSTEM CALIBRATION2

Full-Scale Calibration Limit 1.05 × FS V max

FS = Full scale analog input. When V
differential input must be limited to (0.9 x V

if the in-amp is active.
Zero-Scale Calibration Limit −1.05 × FS V min
Input Span 0.8 × FS V min

2.1 × FS V max
POWER REQUIREMENTS7

Power Supply Voltage

AVDD – GND 2.7/5.25 V min/max
DVDD – GND 2.7/5.25 V min/max

Power Supply Currents

IDD Current 140 µA max

180 µA max

400 µA max

500 µA max

Unbuffered mode, 110 µA typ @ AV

125 µA typ @ AV

= 5 V

DD

Buffered mode, Gain = 1 or 2, 130 µA typ @ AV

165 µA typ @ AV

= 5 V

DD

AD7798: Gain = 4 to 128, 300 µA typ @ AV

350 µA typ @ AV

= 5 V

DD

AD7799: Gain = 4 to 128, 380 µA typ @ AV

440 µA typ @ AV

= 5 V

DD

IDD (Power-Down Mode) 1 µA max

1

Temperature range is –40°C to +105°C.

2

Specification is not production tested, but is supported by characterization data at initial product release.

3

Following a calibration, this error is in the order of the noise for the programmed gain and update rate selected.

4

Recalibration at any temperature removes these errors.

5

Full-scale error applies to both positive and negative full scale and applies at the factory calibration conditions (AVDD = 4 V, gain = 1, TA = 25°C).

6

FS[3:0] are the four bits used in the mode register to select the output word rate.

7

Digital inputs equal to DVDD or GND.

= AVDD, the

REF

= 3 V,

DD

DD

DD

/gain)

REF

= 3 V,

DD

= 3 V,

= 3 V,

Rev. 0 | Page 5 of 28

AD7798/AD7799

TIMING CHARACTERISTICS

AVDD = 2.7 V to 5.25 V, DVDD = 2.7 V to 5.25 V, GND = 0 V, Input Logic 0 = 0 V, Input Logic 1 = DVDD, unless otherwise noted.

Table 2.

Parameter

t3 100 ns min SCLK high pulse width
t4 100 ns min SCLK low pulse width
Read Operation

t1 0 ns min
60 ns max DVDD = 4.75 V to 5.25 V
80 ns max DVDD = 2.7 V to 3.6 V
t
60 ns max DVDD = 4.75 V to 5.25 V
80 ns max DVDD = 2.7 V to 3.6 V
t
80 ns max
t6 0 ns min
t7 10 ns min

Write Operation

t8 0 ns min
t9 30 ns min Data valid to SCLK edge setup time

t10 25 ns min Data valid to SCLK edge hold time
t11 0 ns min

1, 2

Limit at T

3

0 ns min SCLK active edge to data valid delay4

2

5, 6

10 ns min

5

MIN

, T

(B Version) Unit Conditions/Comments

MAX

falling edge to DOUT/RDY active time

CS

Bus relinquish time after CS

SCLK inactive edge to CS

inactive edge

inactive edge

SCLK inactive edge to DOUT/RDY

falling edge to SCLK active edge setup time4

CS

rising edge to SCLK edge hold time

CS

high

1

Sample tested during initial release to ensure compliance. All input signals are specified with tR = tF = 5 ns (10% to 90% of DVDD) and timed from a voltage level of 1.6 V.

2

See Figure 3 and Figure 4.

3

These times are measured with the load circuit of Figure 2 and defined as the time required for the output to cross the VOL or VOH limits.

4

SCLK active edge is the falling edge of SCLK.

5

These times are derived from the measured time taken by the data output to change 0.5 V when loaded with the circuit of Figure 2. The measured time is then

extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the times quoted in the timing characteristics are the true bus
relinquish times of the part and, as such, are independent of external bus loading capacitances.

6

RDY

returns high after a read of the ADC. In single-conversion mode and continuous-conversion mode, data can be reread, if required, while

should be taken to ensure that subsequent reads do not occur close to the next output update. In continuous read mode, the digital word can be read only once.

RDY

is high, but care

I

(1.6mA WITH DVDD = 5V,

SINK

TO

OUTPUT

PIN

50pF

100µA WITH DV

I

SOURCE

100µA WITH DV

= 3V)

DD

1.6V

(200µA WITH DVDD = 5V,

= 3V)

DD

04856-002

Figure 2. Load Circuit for Timing Characterization

Rev. 0 | Page 6 of 28

AD7798/AD7799

S

CS (I)

t

t

1

DOUT/RDY (O)

SCLK (I)

t

2

I = INPUT, O = OUTPUT

MSB LSB

t

3

t

4

Figure 3. Read Cycle Timing Diagram

CS (I)

6

t

5

t

7

04856-003

t

11

04856-004

CLK (I)

DIN (I)

I = INPUT, O = OUTPUT

t

8

t

9

t

10

MSB LSB

Figure 4. Write Cycle Timing Diagram

Rev. 0 | Page 7 of 28

AD7798/AD7799

ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted.

Table 3.

Parameter Rating

AVDD to GND −0.3 V to +7 V
DVDD to GND −0.3 V to +7 V
Analog Input Voltage to GND −0.3 V to AVDD + 0.3 V
Reference Input Voltage to GND −0.3 V to AVDD + 0.3 V
Digital Input Voltage to GND −0.3 V to DVDD + 0.3 V
Digital Output Voltage to GND −0.3 V to DVDD + 0.3 V
AIN/Digital Input Current 10 mA
Operating Temperature Range −40°C to +85°C
Storage Temperature Range −65°C to +150°C
Maximum Junction

Temperature
TSSOP

θJA Thermal Impedance 128°C/W
θJC Thermal Impedance 14°C/W

Lead Temperature, Soldering

Vapor Phase (60 sec) 215°C
Infrared (15 sec) 220°C

150°C

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.

Rev. 0 | Page 8 of 28

AD7798/AD7799

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

1

SCLK

2

CS
AIN3(+)/P1
AIN3(–)/P2

3

AD7798/

4

AD7799

TOP VIEW

5

AIN1(+)
AIN1(–)
AIN2(+)
AIN2(–) REFIN(+)

(Not to Scale)

6

7

8

16

DIN

15

DOUT/RDY

14

DV

13

AV

12

GND

11

PSW

10

REFIN(–)

9

DD

DD

04856-005

Figure 5. Pin Configuration

Table 4. Pin Function Descriptions

Pin
No. Mnemonic Description

1 SCLK

Serial Clock Input for Data Transfers to and from the ADC. The SCLK has a Schmitt-triggered input, making the
interface suitable for opto-isolated applications. The serial clock can be continuous, with all data transmitted in a
continuous train of pulses. Alternatively, it can be noncontinuous, with the information transmitted to or from the
ADC in smaller batches of data.

2

Chip Select Input. This is an active low logic input used to select the ADC. CS can be used to select the ADC in systems

CS

with more than one device on the serial bus, or it can be used as a frame synchronization signal when communicating
with the device. CS

can be hardwired low, allowing the ADC to operate in 3-wire mode, with SCLK, DIN, and DOUT/RDY

used to interface with the device.

3 AIN3(+)/P1

4 AIN3(−)/P2

Analog Input/Digital Output Pin. AIN3(+) is the positive terminal of the differential analog input pair AIN3(+)/AIN3(−).
Alternatively, this pin can function as a general-purpose output bit referenced between AV

and GND

DD

Analog Input/Digital Output Pin. AIN3(−) is the negative terminal of the differential analog input pair AIN3(+)/AIN3(−).
Alternatively, this pin can function as a general-purpose output bit referenced between AV

and GND

DD

5 AIN1(+) Analog Input. AIN1(+) is the positive terminal of the differential analog input pair AIN1(+)/AIN1(−).
6 AIN1(−) Analog Input. AIN1(−) is the negative terminal of the differential analog input pair AIN1(+)/AIN1(−).
7 AIN2(+) Analog Input. AIN2(+) is the positive terminal of the differential analog input pair AIN2(+)/AIN2(−).
8 AIN2(−) Analog Input. AIN2(−) is the negative terminal of the differential analog input pair AIN2(+)/AIN2(−).
9 REFIN(+)

10 REFIN(−)

Positive Reference Input. An external reference can be applied between REFIN(+) and REFIN(−). REFIN(+) can lie
anywhere between AV
can function with a reference from 0.1 V to AV

and GND + 0.1 V. The nominal reference voltage (REFIN(+) – REFIN(−)) is 2.5 V, but the part

DD

.

DD

Negative Reference Input. REFIN(−) is the negative reference input for REFIN. This reference input can lie anywhere
between GND and AV

− 0.1 V.

DD

11 PSW Low-Side Power Switch to GND.
12 GND Ground Reference Point.
13 AVDD Supply Voltage. 2.7 V to 5.25 V.
14 DVDD

15

DOUT/RDY

Digital Interface Supply Voltage. The logic levels for the serial interface pins are related to this supply, which is
between 2.7 V and 5.25 V. The DV
DV

at 3 V, or vice versa.

DD

voltage is independent of the voltage on AVDD; therefore, AVDD can equal 5 V with

DD

Serial Data Output/Data Ready Output. DOUT/RDY serves a dual purpose. It functions as a serial data output pin to

access the output shift register of the ADC. The output shift register can contain data from any of the on-chip data or
control registers. In addition, DOUT/RDY

operates as a data ready pin, going low to indicate the completion of a

conversion. If the data is not read after the conversion, the pin goes high before the next update occurs.

16 DIN

The DOUT/RDY
external serial clock, the data can be read using the DOUT/RDY
placed on the DOUT/RDY

Serial Data Input to the Input Shift Register on the ADC. Data in this shift register is transferred to the control registers

falling edge can be used as an interrupt to a processor, indicating that valid data is available. With an

pin. With CS low, the data/control word information is

pin on the SCLK falling edge and is valid upon the SCLK rising edge.

within the ADC, with the register selection bits of the communication register identifying the appropriate register.

Rev. 0 | Page 9 of 28