ANALOG DEVICES AD7796 Service Manual

Low Power, 16-/24-Bit Sigma-Delta ADC

A

A

V

FEATURES

RMS noise: 65 nV
Instrumentation amp
Temperature sensor
Internal clock oscillator
Simultaneous 50 Hz/60 Hz rejection
Update rate: 4.17 Hz to 123 Hz
Current: 250 μA typ
Power-down: 1 μA
Power supply: 2.7 V to 5.25 V
–40°C to +85°C temperature range
Independent interface power supply
16-lead TSSOP

INTERFACE

3-wire serial
SPI®, QSPI™, MICROWIRE™, and DSP compatible
Schmitt trigger on SCLK

APPLICATIONS

Weigh scales
Strain gages
Industrial process control
Instrumentation
Portable instrumentation

GND

GENERAL DESCRIPTION

The AD7796/AD7797 are complete, analog front ends for high
precision, bridge sensor applications such as weigh scales. The
AD7796/AD7797 contain a Σ-Δ ADC capable of 16-/24-bit
resolution, respectively. The on-chip instrumentation amplifier
has a fixed gain of 128, allowing small amplitude signals such as
those from bridge sensors to be directly interfaced to the ADC.

Each part has one differential input and contains a temperature
sensor that is internally connected to the ADC. This sensor can
be used to perform temperature compensation of the bridge.

The devices can be operated with the internal clock or an
external clock. The output data rate from the parts is software­programmable and can be varied from 4.17 Hz to 123 Hz.

The AD7796/AD7797 operate with a power supply from 2.7 V
to 5.25 V. Each part consumes a current of 250 μA typical and is
housed in a 16-lead TSSOP.

FUNCTIONAL BLOCK DIAGRAM

A

DD

AV

DD

REFIN(–)REFIN(+)

AD7796: 16-BIT ADC
AD7797: 24-BIT ADC

for Bridge Sensors

AD7796/AD7797

IN(+)
IN(–)

MUX

GND

AD7796/
AD7797

×128

REFERENCE

TEMP

SENSOR

Σ-Δ

ADC

Figure 1.

SERIAL

INTERFACE

AND

CONTROL

LOGIC

INTERNAL

CLOCK

CLK

DOUT/RDY
DIN
SCLK
CS

DV

DD

06083-001

Rev. A

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her
rights of third parties that may result from its use. Specifications subject to change without notice. No
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One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] ©2006 Analog Devices, Inc. All rights reserved.

AD7796/AD7797

TABLE OF CONTENTS

Features.............................................................................................. 1

ID Register................................................................................... 14

Interface ............................................................................................. 1

Applications....................................................................................... 1

General Description ......................................................................... 1

Functional Block Diagram .............................................................. 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

Timing Characteristics..................................................................... 5

Timing Diagrams.......................................................................... 6

Absolute Maximum Ratings............................................................ 7

Thermal Resistance ...................................................................... 7

ESD Caution.................................................................................. 7

Pin Configuration and Function Descriptions............................. 8

RMS Noise and Resolution Specifications .................................... 9

Typical Performance Characteristics ........................................... 10

On-Chip Registers.......................................................................... 11

Offset Register ............................................................................ 15

Full-Scale Register...................................................................... 15

ADC Circuit Information.............................................................. 16

Overview ..................................................................................... 16

Digital Interface.......................................................................... 17

Circuit Description......................................................................... 20

Analog Input Channel............................................................... 20

Bipolar/Unipolar Configuration .............................................. 20

Data Output Coding .................................................................. 20

Reference ..................................................................................... 20

Reset ............................................................................................. 21

Burnout Currents....................................................................... 21

AV

Monitor ............................................................................. 21

DD

Temperature Monitor ................................................................ 21

Calibration................................................................................... 21

Communication Register ..........................................................11

Status Register............................................................................. 12

Mode Register ............................................................................. 12

Configuration Register ..............................................................14

Data Register............................................................................... 14

REVISION HISTORY

8/06—Rev. 0 to Rev. A.

Changes to Table 1............................................................................ 3

Changes to Figure 5.......................................................................... 8

Changes to Table 14........................................................................ 13

Grounding and Layout.............................................................. 22

Applications..................................................................................... 23

Weigh Scales................................................................................ 23

Outline Dimensions....................................................................... 24

Ordering Guide .......................................................................... 24

7/06—Revision 0: Initial Version

Rev. A | Page 2 of 24

AD7796/AD7797

SPECIFICATIONS

AVDD = 2.7 V to 5.25 V, DVDD = 2.7 V to 5.25 V, GND = 0 V, all specifications T

Table 1.

Parameter AD7796B/AD7797B1 Unit Test Conditions/Comments

ADC CHANNEL

Output Update Rate 4.17 to 123 Hz nom
No Missing Codes

2

24 Bits min AD7797 only
16 Bits min AD7796 only
Resolution See Tab le 7 and Tabl e 8
RMS Noise and Update Rates See Tab le 6
Integral Nonlinearity ±10 ppm of FSR typ
Offset Error
Offset Error Drift vs. Temperature
Full-Scale Error
Gain Drift vs. Temperature

3, 4

3, 4, 5

4

±10 nV/°C typ

±10 μV typ

±1 μV typ

4

±3 ppm/°C typ
Power Supply Rejection 90 dB min AIN = 1 V/128

ANALOG INPUTS

Differential Input Voltage Ranges ±V
Absolute AIN Voltage Limits

2

/128 V nom V

REF

GND + 300 mV V min

AVDD − 1.1 V max
Common-Mode Voltage, VCM 0.5 V min VCM = (AIN(+) + AIN(–))/2

Analog Input Current

Average Input Current

2

±250 pA max Update rate < 100 Hz

Average Input Current Drift ±2 pA/°C typ

Normal Mode Rejection

2

Internal Clock

@ 50 Hz, 60 Hz 65 dB min 80 dB typ, 50 ± 1 Hz, 60 ± 1 Hz, FS[3:0] = 1010
@ 50 Hz 80 dB min 90 dB typ, 50 ± 1 Hz, FS[3:0] = 1001
@ 60 Hz 90 dB min 100 dB typ, 60 ± 1 Hz, FS[3:0] = 1000

External Clock

@ 50 Hz, 60 Hz 80 dB min 90 dB typ, 50 ± 1 Hz, 60 ± 1 Hz, FS[3:0] = 1010
@ 50 Hz 94 dB min 100 dB typ, 50 ± 1 Hz, FS[3:0] = 1001
@ 60 Hz 90 dB min 100 dB typ, 60 ± 1 Hz, FS[3:0] = 1000

Common-Mode Rejection

@ DC 90 dB min AIN = 7.81 mV
@ 50 Hz, 60 Hz
@ 50 Hz, 60 Hz

2

2

90 dB min 50 ± 1 Hz, 60 ± 1 Hz, FS[3:0] = 1010

90 dB min

REFERENCE

External REFIN Voltage 2.5 V nom REFIN = REFIN(+) – REFIN(–)
Reference Voltage Range

2

0.1 V min

AVDD V max

Absolute REFIN Voltage Limits

AV

2

GND − 30 mV V min

+ 30 mV V max

DD

Average Reference Input Current 400 nA/V typ
Average Reference Input Current Drift ±0.03 nA/V/°C typ
Normal Mode Rejection Same as for analog inputs
Common-Mode Rejection 100 dB typ

TEMPERATURE SENSOR

Accuracy ±2 °C typ Applies if user calibrates the temperature sensor
Sensitivity 0.81 mV/°C typ

MIN

to T

, unless otherwise noted.

MAX

= REFIN(+) – REFIN(–)

REF

50 ± 1 Hz (FS[3:0] = 1001
FS[3:0] = 1000

6

6

), 60 ± 1 Hz,

6

6

6

6

6

6

6

Rev. A | Page 3 of 24

AD7796/AD7797

Parameter AD7796B/AD7797B1 Unit Test Conditions/Comments

INTERNAL/EXTERNAL CLOCK

Internal Clock

Frequenc y
Duty Cycle 50:50 % typ

External Clock

Frequency 64 kHz nom

Duty Cycle 45:55 to 55:45 % typ

LOGIC INPUTS

2

CS

Input Low Voltage, V

0.4 V max DVDD = 3 V
Input High Voltage, V

SCLK, CLK, and

DIN (Schmitt-Triggered Input)
VT(+) 1.4/2 V min/V max DVDD = 5 V
VT(–) 0.8/1.7 V min/V max DVDD = 5 V
VT(+) − VT(–) 0.1/0.17 V min/V max DVDD = 5 V
VT(+) 0.9/2 V min/V max DVDD = 3 V
VT(–) 0.4/1.35 V min/V max DVDD = 3 V
VT(+) − VT(–)
Input Currents ±10 μA max VIN = DVDD or GND
Input Capacitance 10 pF typ All digital inputs

LOGIC OUTPUTS (INCLUDING CLK)

Output High Voltage, V
4 V min DVDD = 5 V, I
Output Low Voltage, V

0.4 V max
Floating-State Leakage Current ±10 μA max
Floating-State Output Capacitance 10 pF typ
Data Output Coding Offset Binary

SYSTEM CALIBRATION

Full-Scale Calibration Limit +1.05 × FS V max
Zero-Scale Calibration Limit −1.05 × FS V min
Input Span 0.8 × FS V min

2.1 × FS V max

POWER REQUIREMENTS

Power Supply Voltage

AVDD – GND 2.7/5.25 V min/max
DVDD – GND 2.7/5.25 V min/max

Power Supply Currents

IDD Current 325 μA max 250 μA typ @ AVDD = 3 V, 280 μA typ @ AVDD = 5 V
IDD (Power-Down Mode) 1 μA max

1

Temperature range is –40°C to +85°C.

2

Specification is not production tested, but is supported by characterization data at initial product release.

3

Following a calibration, this error is in the order of the noise for the update rate selected.

4

Recalibration at any temperature removes these errors.

5

Full-scale error applies to both positive and negative full-scale and applies at the factory calibration conditions (AVDD = 4 V, TA = 25°C).

6

FS[3:0] are the four bits used in the mode register to select the output word rate.

7

Digital inputs equal to DVDD or GND.

2

64 ± 3% kHz min/max

A 128 kHz clock can be used if the divide by 2
function is used (Bit CLK1 = CLK0 = 1)

Applies for external 64 kHz clock (a 128 kHz
clock can have a less stringent duty cycle)

0.8 V max DVDD = 5 V

INL

2.0 V min DVDD = 3 V or 5 V

INH

2

0.06/0.13 V min/V max DVDD = 3 V

2

OH

2

OL

2

7

DVDD − 0.6 V min DVDD = 3 V, I

0.4 V max DVDD = 3 V, I
= 5 V, I

DV

DD

= 100 μA

SOURCE

= 200 μA

SOURCE

= 100 μA

SINK

= 1.6 mA (DOUT/RDY)/800 μA (CLK)

SINK

Rev. A | Page 4 of 24

AD7796/AD7797

TIMING CHARACTERISTICS

AVDD = 2.7 V to 5.25 V, DVDD = 2.7 V to 5.25 V, GND = 0 V, Input Logic 0 = 0 V, Input Logic 1 = DVDD, unless otherwise noted.

Table 2.

Parameter

t3 100 ns min SCLK high pulse width
t4 100 ns min SCLK low pulse width
Read Operation

t1 0 ns min
60 ns max DVDD = 4.75 V to 5.25 V
80 ns max DVDD = 2.7 V to 3.6 V
t

2

60 ns max DVDD = 4.75 V to 5.25 V
80 ns max DVDD = 2.7 V to 3.6 V
t

5

80 ns max
t6 0 ns min
t7 10 ns min

Write Operation

t8 0 ns min
t9 30 ns min Data valid to SCLK edge setup time

t10 25 ns min Data valid to SCLK edge hold time
t11 0 ns min

1

Sample tested during initial release to ensure compliance. All input signals are specified with tR = tF = 5 ns (10% to 90% of DVDD) and timed from a voltage level of 1.6 V.

2

See Figure 3 and Figure 4.

3

These numbers are measured with the load circuit of Figure 2 and defined as the time required for the output to cross the VOL or VOH limits.

4

SCLK active edge is falling edge of SCLK.

5

These numbers are derived from the measured time taken by the data output to change 0.5 V when loaded with the circuit of Figure 2. The measured number is then

extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the times quoted in the timing characteristics are the true bus
relinquish times of the parts and, as such, are independent of external bus loading capacitances.

6

RDY
Care should be taken to ensure that subsequent reads do not occur close to the next output update. In continuous read mode, the digital word can be read only once.

1, 2

Limit at T

MIN

, T

(B Version) Unit Conditions/Comments

MAX

CS falling edge to DOUT/RDY active time

3

5, 6

0 ns min SCLK active edge to data valid delay

10 ns min

Bus relinquish time after

SCLK inactive edge to

CS inactive edge

CS inactive edge

SCLK inactive edge to DOUT/

CS falling edge to SCLK active edge setup time

4

RDY high

4

CS rising edge to SCLK edge hold time

returns high after a read of the ADC. In single conversion mode and continuous conversion mode, the same data can be read again, if required, while

RDY

is high.

I

(1.6mA WITH DVDD=5V,

TO

OUTPUT

PIN

50pF

SINK

100µAWITHDV

I

SOURCE

100µAWITHDV

=3V)

DD

1.6V

(200µA WITH DVDD=5V,

=3V)

DD

06083-002

Figure 2. Load Circuit for Timing Characterization

Rev. A | Page 5 of 24

AD7796/AD7797

TIMING DIAGRAMS

CS (I)

DOUT/RDY (O)

SCLK (I)

CS (I)

t

1

MSB LSB

t

2

t

3

t

I = INPUT, O = OUTPUT

4

Figure 3. Read Cycle Timing Diagram

t

6

t

5

t

7

06083-003

t

11

06083-004

SCLK (I)

DIN (I)

I = INPUT

t

8

t

9

t

10

MSB LSB

Figure 4. Write Cycle Timing Diagram

Rev. A | Page 6 of 24

AD7796/AD7797

ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted.

Table 3.

Parameter Rating

AVDD to GND −0.3 V to +7 V
DVDD to GND −0.3 V to +7 V
Analog Input Voltage to GND −0.3 V to AVDD + 0.3 V
Reference Input Voltage to GND −0.3 V to AVDD + 0.3 V
Digital Input Voltage to GND −0.3 V to DVDD + 0.3 V
Digital Output Voltage to GND −0.3 V to DVDD + 0.3 V
AIN/Digital Input Current 10 mA
Operating Temperature Range −40°C to +85°C
Storage Temperature Range −65°C to +150°C
Maximum Junction Temperature 150°C
Lead Temperature, Soldering

Vapor Phase (60 sec) 215°C
Infrared (15 sec) 220°C

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

THERMAL RESISTANCE

θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.

Table 4.

Package Type θJA θ

TSSOP 128 14 °C/W

Unit

JC

ESD CAUTION

Rev. A | Page 7 of 24

AD7796/AD7797

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

SCLK

CLK

CS

NC

AIN(+)

AIN(–)

NC

NC

1

2

AD7796/

3

AD7797

4

TOP VIEW

(Not to Scale)

5

6

7

8

NC = NO CONNECT

16

DIN

15

DOUT/RDY

14

DV

13

AV

12

GND

11

NC

10

REFIN(–)

9

REFIN(+)

DD

DD

06083-005

Figure 5. Pin Configuration

Table 5. Pin Function Descriptions

Pin
No.

Mnemonic Description

1 SCLK

Serial Clock Input. This serial clock input is for data transfers to and from the ADC. The SCLK has a Schmitt­triggered input, making the interface suitable for opto-isolated applications. The serial clock can be continuous
with all data transmitted in a constant train of pulses. Alternatively, it can be a noncontinuous clock with the
information being transmitted to or from the ADC in smaller batches of data.

2 CLK

Clock In/Clock Out. The internal clock can be made available at this pin. Alternatively, the internal clock can be
disabled, and the ADC can be driven by an external clock. This allows several ADCs to be driven from a common
clock, allowing simultaneous conversions to be performed.

3

CS Chip Select Input. This is an active low logic input used to select the ADC. CS can be used to select the ADC in

systems with more than one device on the serial bus or as a frame synchronization signal in communicating
with the device. CS can be hardwired low, allowing the ADC to operate in 3-wire mode with SCLK, DIN, and

DOUT used to interface with the device.
4 NC No Connect.
5 AIN(+) Analog Input. AIN(+) is the positive terminal of the differential analog input pair AIN(+)/AIN(−).
6 AIN(−) Analog Input. AIN(−) is the negative terminal of the differential analog input pair AIN(+)/AIN(−).
7 NC No Connect.
8 NC No Connect.
9 REFIN(+)

10 REFIN(−)

Positive Reference Input/Analog Input. An external reference can be applied between REFIN(+) and REFIN(–).

REFIN(+) can lie anywhere between AV

2.5 V, but the parts function with a reference of 0.1 V to AV

and GND + 0.1 V. The nominal reference voltage (REFIN(+) – REFIN(−)) is

DD

.

DD

Negative Reference Input/Analog Input. REFIN(−) is the negative reference input for REFIN. This reference input

can lie anywhere between GND and AV

− 0.1 V.

DD

11 NC No Connect.
12 GND Ground Reference Point.

13 AVDD Supply Voltage, 2.7 V to 5.25 V.
14 DVDD

15

DOUT/

RDY Serial Data Output/Data Ready Output. DOUT/RDY serves a dual purpose. It functions as a serial data output pin

Digital Interface Supply Voltage. The logic levels for the serial interface pins are related to this supply, which is

between 2.7 V and 5.25 V. The DV

with DV

at 3 V or vice versa.

DD

voltage is independent of the voltage on AVDD; therefore, AVDD can equal 5 V

DD

to access the output shift register of the ADC. The output shift register can contain data from any of the on-chip

data or control registers. In addition, DOUT/

RDY operates as a data ready pin, going low to indicate the completion

of a conversion. If the data is not read after the conversion, the pin goes high before the next update occurs.

16 DIN

The DOUT/

With an external serial clock, the data can be read using the DOUT/

information is placed on the DOUT/

Serial Data Input. This serial data input accesses the input shift register on the ADC. Data in this shift register is

RDY falling edge can be used as an interrupt to a processor, indicating that valid data is available.

RDY pin. With CS low, the data/control word

RDY pin on the SCLK falling edge and is valid on the SCLK rising edge.

transferred to the control registers within the ADC; the register selection bits of the communication register

identify the appropriate register.

Rev. A | Page 8 of 24