ANALOG DEVICES AD7793 Service Manual

3-Channel, Low Noise, Low Power, 16-/24-Bit

Y

A

V

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∑-Δ ADC with On-Chip In-Amp and Reference

FEATURES

Up to 23 bits effective resolution
RMS noise
40 nV @ 4.17 Hz
85 nV @ 16.7 Hz
Current: 400 μA typical
Power-down: 1 μA maximum
Low noise programmable gain instrumentation amp
Band gap reference with 4 ppm/°C drift typical
Update rate: 4.17 Hz to 470 Hz
3 differential inputs
Internal clock oscillator
Simultaneous 50 Hz/60 Hz rejection
Programmable current sources
On-chip bias voltage generator
Burnout currents
Power supply: 2.7 V to 5.25 V
–40°C to +105°C temperature range
Independent interface power supply
16-lead TSSOP package
Interface

3-wire serial
SPI®, QSPI™, MICROWIRE™, and DSP compatible
Schmitt trigger on SCLK

APPLICATIONS

Thermocouple measurements
RTD measurements
Thermistor measurements
Gas analysis
Industrial process control
Instrumentation
Portable instrumentation
Blood analysis
Smart transmitters
Liquid/gas chromatography
6-digit DVM

AD7792/AD7793

FUNCTIONAL BLOCK DIAGRAM

AIN1(+)
AIN1(–)
AIN2(+)
AIN2(–)

IOUT1

IOUT2

V

GND

BIAS

MUX

DD

AV

DD

AV

DD

GND

BAND GAP

REFERENCE

IN-AMPBUF

INTERNAL

CLOCK

Figure 1.

REFIN(+)/AI N3(+)

CLK

GENERAL DESCRIPTION

The AD7792/AD7793 are low power, low noise, complete
analog front ends for high precision measurement applications.
The AD7792/AD7793 contain a low noise 16-/24-bit ∑-Δ ADC
with three differential analog inputs. The on-chip, low noise
instrumentation amplifier means that signals of small ampli­tude can be interfaced directly to the ADC. With a gain
setting of 64, the rms noise is 40 nV when the update rate
equals 4.17 Hz.

The devices contain a precision low noise, low drift internal

and gap reference and can accept an external differential

b
reference. Other on-chip features include programmable
excitation current sources, burnout currents, and a bias voltage
generator. The bias voltage generator sets the common-mode
voltage of a channel to AV

The devices can be operated with either the internal clock or an

ernal clock. The output data rate from the parts is software-

ext
programmable and can be varied from 4.17 Hz to 470 Hz.

The parts operate with a power supply from 2.7 V to 5.25 V.

nsume a current of 400 μA typical and are housed in a

They co
16-lead TSSOP package.

DD

/2.

REFIN(–)/AIN3(–)

GND

SERIAL

INTERFACE

Σ-Δ

ADC

CONTROL

LOGIC

AD7792: 16-BIT
AD7793: 24-BIT

AND

DOUT/RD

DIN

SCLK

CS

DV

DD

04855-001

Rev. B

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] ©2004–2007 Analog Devices, Inc. All rights reserved.

AD7792/AD7793

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TABLE OF CONTENTS

Features.............................................................................................. 1

Applications....................................................................................... 1

Functional Block Diagram .............................................................. 1

General Description ......................................................................... 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

Timing Characteristics..................................................................... 6

Timing Diagrams.......................................................................... 7

Absolute Maximum Ratings............................................................ 8

ESD Caution.................................................................................. 8

Pin Configuration and Function Descriptions............................. 9

Output Noise and Resolution Specifications ..............................11

External Reference...................................................................... 11

Internal Reference ...................................................................... 12

Typical Performance Characteristics ........................................... 13

On-Chip Registers.......................................................................... 14

Communications Register......................................................... 14

Status Register............................................................................. 15

Mode Register ............................................................................. 15

Configuration Register ..............................................................17

Data Register............................................................................... 18

ID Register................................................................................... 18

IO Register................................................................................... 18

Offset Register ............................................................................ 19

Full-Scale Register...................................................................... 19

ADC Circuit Information.............................................................. 20

Overview ..................................................................................... 20

Digital Interface.......................................................................... 21

Circuit Description......................................................................... 24

Analog Input Channel............................................................... 24

Instrumentation Amplifier........................................................ 24

Bipolar/Unipolar Configuration .............................................. 24

Data Output Coding .................................................................. 24

Burnout Currents....................................................................... 25

Excitation Currents.................................................................... 25

Bias Voltage Generator .............................................................. 25

Reference ..................................................................................... 25

Reset ............................................................................................. 25

AV

Monitor ............................................................................. 26

DD

Calibration................................................................................... 26

Grounding and Layout.............................................................. 26

Applications Information.............................................................. 28

Temperature Measurement using a Thermocouple............... 28

Temperature Measurement using an RTD.............................. 29

Outline Dimensions....................................................................... 30

Ordering Guide .......................................................................... 30

REVISION HISTORY

3/07—Rev. A to Rev. B

Updated Format..................................................................Universal

Change to Functional Block Diagram ........................................... 1

C

hanges to Specifications Section.................................................. 3

Changes to Specifications Endnote 1............................................. 5

C

hanges to Table 5, Table 6, and Table 7 ..................................... 11

Changes to Table 8, Table 9, and Table 10 ...................................12

Changes to Table 16........................................................................ 16

Changes to Overview Section ....................................................... 20

Renamed Applications Section to Applications Information... 29

Changes to Ordering Guide.......................................................... 30

Rev. B | Page 2 of 32

4/05—Rev. 0 to Rev. A

C

hanges to Absolute Maximum Ratings........................................8

Changes to Figure 17.......................................................................22

Changes to Data Output Coding Section.....................................24

Changes to Calibration Section.....................................................26

Changes to Ordering Guide........................................................... 30

10/04—Revision 0: Initial Version

AD7792/AD7793

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SPECIFICATIONS

AVDD = 2.7 V to 5.25 V; DVDD = 2.7 V to 5.25 V; GND = 0 V; all specifications T

Table 1.

Parameter AD7792B/AD7793B1 Unit Test Conditions/Comments

ADC CHANNEL

Output Update Rate 4.17 to 470 Hz nom
No Missing Codes

2

24 Bits min f
16 Bits min AD7792
Resolution See Output Noise and Resolution Specifications
Output Noise and Update Rates See Output Noise and Resolution Specifications
Integral Nonlinearity ±15 ppm of FSR max
Offset Error
Offset Error Drift vs. Temperature
Full-Scale Error
Gain Drift vs. Temperature

3

4

3, 5

4

±1 μV typ

±10 nV/°C typ

±10 μV typ

±1 ppm/°C typ Gain = 1 to 16, external reference
±3 ppm/°C typ Gain = 32 to 128, external reference
Power Supply Rejection 100 dB min AIN = 1 V/gain, gain ≥ 4, external reference

ANALOG INPUTS

Differential Input Voltage Ranges ±V

Absolute AIN Voltage Limits

2

/Gain V nom

REF

Unbuffered Mode GND – 30 mV V min Gain = 1 or 2

AVDD + 30 mV V max

Buffered Mode GND + 100 mV V min Gain = 1 or 2

AVDD – 100 mV V max

In-Amp Active GND + 300 mV V min Gain = 4 to 128

AVDD – 1.1 V max

Common-Mode Voltage, VCM 0.5 V min

Analog Input Current

Buffered Mode or In-Amp Active

Average Input Current

2

±1 nA max Gain = 1 or 2, update rate < 100 Hz
±250 pA max Gain = 4 to 128, update rate < 100 Hz

Average Input Current Drift ±2 pA/°C typ

Unbuffered Mode Gain = 1 or 2.

Average Input Current ±400 nA/V typ Input current varies with input voltage
Average Input Current Drift ±50 pA/V/°C typ

Normal Mode Rejection

2

Internal Clock

@ 50 Hz, 60 Hz 65 dB min 80 dB typ, 50 ± 1 Hz, 60 ± 1 Hz, FS[3:0] = 1010
@ 50 Hz 80 dB min 90 dB typ, 50 ± 1 Hz, FS[3:0] = 1001
@ 60 Hz 90 dB min 100 dB typ, 60 ± 1 Hz, FS[3:0] = 1000

External Clock

@ 50 Hz, 60 Hz 80 dB min 90 dB typ, 50 ± 1 Hz, 60 ± 1 Hz, FS[3:0] = 1010
@ 50 Hz 94 dB min 100 dB typ, 50 ± 1 Hz, FS[3:0] = 1001
@ 60 Hz 90 dB min 100 dB typ, 60 ± 1 Hz, FS[3:0] = 1000

Common-Mode Rejection

@ DC 100 dB min AIN = 1 V/gain, gain ≥ 4
@ 50 Hz, 60 Hz
@ 50 Hz, 60 Hz

2

2

100 dB min 50 ± 1 Hz, 60 ± 1 Hz, FS[3:0] = 1010

100 dB min

MIN

to T

, unless otherwise noted.

MAX

< 242 Hz, AD7793

ADC

= REFIN(+) − REFIN(−) or internal reference,

V

REF

gain = 1 to 128

VCM = (AIN(+) + AIN(−))/2, gain = 4 to 128

6

50 ± 1 Hz (FS[3:0] = 1001)
(FS[3:0] = 1000)

6

, 60 ± 1 Hz

6

6

6

6

6

6

6

Rev. B | Page 3 of 32

AD7792/AD7793

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Parameter AD7792B/AD7793B1 Unit Test Conditions/Comments

REFERENCE

Internal Reference

Internal Reference Initial Accuracy 1.17 ± 0.01% V min/max AVDD = 4 V, TA = 25°C

Internal Reference Drift

15 ppm/°C max

Power Supply Rejection 85 dB typ

External Reference

External REFIN Voltage 2.5 V nom

Reference Voltage Range

AVDD V max

Absolute REFIN Voltage Limits

AV

Average Reference Input Current 400 nA/V typ

Average Reference Input Current

Drift

Normal Mode Rejection Same as for analog inputs
Common-Mode Rejection 100 dB typ

EXCITATION CURRENT SOURCES

(IEXC1 and IEXC2)
Output Current 10/210/1000 μA nom
Initial Tolerance at 25°C ±5 % typ
Drift 200 ppm/°C typ
Current Matching ±0.5 % typ Matching between IEXC1 and IEXC2; V
Drift Matching 50 ppm/°C typ
Line Regulation (VDD) 2 %/V typ AVDD = 5 V ± 5%
Load Regulation 0.2 %/V typ
Output Compliance

TEMPERATURE SENSOR

Accuracy
Sensitivity

BIAS VOLTAGE GENERATOR

V

AVDD/2 V nom

BIAS

V

Generator Start-Up Time See Figure 10 ms/nF typ Dependent on the capacitance on the AIN pin

BIAS

INTERNAL/EXTERNAL CLOCK

Internal Clock

Frequenc y

2

Duty Cycle 50:50 % typ

External Clock

Frequency 64 kHz nom

Duty Cycle 45:55 to 55:45 % typ

LOGIC INPUTS

2

CS

V

, Input Low Voltage 0.8 V max DVDD = 5 V

INL

, Input High Voltage

V

INH

2

4 ppm/°C typ

REFIN = REFIN(+) − REFIN(−)

2

2

0.1 V min

GND − 30 mV

+ 30 mV V max

DD

±0.03 nA/V/°C t

AVDD − 0.65

AVDD − 1.1

GND − 30 mV

±2

0.81

V min

yp

V max 10 μA or 210 μA currents selected

V max 1 mA currents selected

V min

°C typ
mV/°C typ

When V
limited to 0.9 × V

= AVDD, the differential input must be

REF

/gain if the in-amp is active

REF

Applies if user calibrates the temperature
sensor

64 ± 3% kHz min/max

A 128 kHz external clock can be used if the

-by-2 function is used

divide
(Bit CLK1 = CLK0 = 1)

Applies for external 64 kHz clock; a 128 kHz

an have a less stringent duty cycle

clock c

0.4

2.0

V max
V min

DV

= 3 V

DD

= 3 V or 5 V

DV

DD

OUT

= 0 V

Rev. B | Page 4 of 32

AD7792/AD7793

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Parameter AD7792B/AD7793B1 Unit Test Conditions/Comments

SCLK, CLK, and DIN (Schmitt-

Triggered Input)

2

VT(+) 1.4/2 V min/V max DVDD = 5 V
VT(–) 0.8/1.7 V min/V max DVDD = 5 V
VT(+) − VT(−)
VT(+) 0.9/2 V min/V max DVDD = 3 V
VT(–) 0.4/1.35 V min/V max DVDD = 3 V
VT(+) − VT(−)

Input Currents
Input Capacitance

LOGIC OUTPUTS (INCLUDING CLK)

VOH, Output High Voltage

VOL, Output Low Voltage
VOH, Output High Voltage
VOL, Output Low Voltage

2

2

2

2

Floating-State Leakage Current ±10 μA max
Floating-State Output Capacitance 10 pF typ
Data Output Coding Offset binary

SYSTEM CALIBRATION

2

Full-Scale Calibration Limit +1.05 × FS V max
Zero-Scale Calibration Limit

Input Span 0.8 × FS V min

2.1 × FS V max

POWER REQUIREMENTS

7

Power Supply Voltage

AVDD to GND

DVDD to GND

Power Supply Currents

IDD Current 140 μA max

185 μA max

400 μA max

500 μA max

IDD (Power-Down Mode) 1 μA max

1

Temperature range is –40°C to +105°C. At the 19.6 Hz and 39.2 Hz update rates, the INL, power supply rejection (PSR), common-mode rejection (CMR), and normal

mode rejection (NMR) do not meet the data sheet specification if the voltage on the AIN(+) or AIN(−) pins exceed AV
the INL, for example, is reduced to 18 ppm of FS typically while the PSR is reduced to 69 dB typically. Therefore, for guaranteed performance at these update rates, the
absolute voltage on the analog input pins needs to be below AV

2

Specification is not production tested, but is supported by characterization data at initial product release.

3

Following a calibration, this error is in the order of the noise for the programmed gain and update rate selected.

4

Recalibration at any temperature removes these errors.

5

Full-scale error applies to both positive and negative full-scale and applies at the factory calibration conditions (AVDD = 4 V, gain = 1, TA = 25°C).

6

FS[3:0] are the four bits used in the mode register to select the output word rate.

7

Digital inputs equal to DVDD or GND with excitation currents and bias voltage generator disabled.

0.1/0.17 V min/V max DVDD = 5 V

0.06/0.13 V min/V max DVDD = 3 V

±10

10

DVDD − 0.6

0.4 V max DVDD = 3 V, I

4 V min DVDD = 5 V, I

0.4 V max

μA max
pF typ

VIN = DVDD or GND
All digital inputs

V min DVDD = 3 V, I

= 5 V, I

DV

DD

= 100 μA

SOURCE

= 100 μA

SINK

= 200 μA

SOURCE

= 1.6 mA (DOUT/RDY)/800 μA

SINK

(CLK)

−1.05 × FS

V min

2.7/5.25 V min/max

2.7/5.25 V min/max

110 μA typ @ AV

= 3 V, 125 μA typ @ AVDD = 5 V,

DD

unbuffered mode, external reference
130 μA typ @ AV

= 3 V, 165 μA typ @ AVDD = 5 V,

DD

buffered mode, gain = 1 or 2, external reference
300 μA typ @ AV

= 3 V, 350 μA typ @ AVDD = 5 V,

DD

gain = 4 to 128, external reference
400 μA typ @ AV

= 3 V, 450 μA typ @ AVDD = 5 V,

DD

gain = 4 to 128, internal reference

− 16 V typically. When this voltage is exceeded,

DD

− 1.6 V.

DD

Rev. B | Page 5 of 32

AD7792/AD7793

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TIMING CHARACTERISTICS

AVDD = 2.7 V to 5.25 V, DVDD = 2.7 V to 5.25 V, GND = 0 V, Input Logic 0 = 0 V, Input Logic 1 = DVDD, unless otherwise noted.

Table 2.

Parameter

1, 2

Limit at T

MIN

, T

(B Version) Unit Conditions/Comments

MAX

t3 100 ns min SCLK high pulse width
t4 100 ns min SCLK low pulse width
Read Operation

t1 0 ns min

falling edge to DOUT/RDY active time

CS
60 ns max DVDD = 4.75 V to 5.25 V
80 ns max DVDD = 2.7 V to 3.6 V

3

t

2

0 ns min SCLK active edge to data valid delay

4

60 ns max DVDD = 4.75 V to 5.25 V
80 ns max DVDD = 2.7 V to 3.6 V

5, 6

t

5

10 ns min

Bus relinquish time after CS

inactive edge
80 ns max
t6 0 ns min
t7 10 ns min

SCLK inactive edge to CS
SCLK inactive edge to DOUT/RDY

inactive edge

high

Write Operation

t8 0 ns min

falling edge to SCLK active edge setup time

CS

4

t9 30 ns min Data valid to SCLK edge setup time
t10 25 ns min Data valid to SCLK edge hold time
t11 0 ns min

1

Sample tested during initial release to ensure compliance. All input signals are specified with tR = tF = 5 ns (10% to 90% of DVDD) and timed from a voltage level of 1.6 V.

2

See Figure 3 and Figure 4.

3

These numbers are measured with the load circuit shown in Figure 2 and defined as the time required for the output to cross the VOL or VOH limits.

4

SCLK active edge is falling edge of SCLK.

5

These numbers are derived from the measured time taken by the data output to change 0.5 V when loaded with the circuit shown in Figure 2. The measured number

is then extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the times quoted in the timing characteristics are the
true bus relinquish times of the part and, as such, are independent of external bus loading capacitances.

6

RDY

returns high after a read of the ADC. In single conversion mode and continuous conversion mode, the same data can be read again, if required, while
although care should be taken to ensure that subsequent reads do not occur close to the next output update. In continuous read mode, the digital word can be read
only once.

rising edge to SCLK edge hold time

CS

RDY

is high,

I

(1.6mA WITH DVDD = 5V,

SINK

100µA WIT H DV

DD

= 3V)

TO

OUTPUT

PIN

50pF

I

SOURCE

100µA WIT H DV

Figure 2. Load Circuit for Timing Characterization

1.6V

(200µA WIT H DVDD = 5V,

= 3V)

DD

4855-002

Rev. B | Page 6 of 32

AD7792/AD7793

S

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TIMING DIAGRAMS

CS (I)

t

t

1

DOUT/RDY (O)

SCLK (I)

t

2

NOTES

1. I = INPUT, O = OUTPUT

MSB LSB

t

3

t

4

Figure 3. Read Cycle Timing Diagram

CS (I)

6

t

5

t

7

04855-003

t

11

04855-004

CLK (I)

DIN (I)

NOTES

1. I = INPUT, O = OUTPUT

t

8

t

9

t

10

MSB LSB

Figure 4. Write Cycle Timing Diagram

Rev. B | Page 7 of 32

AD7792/AD7793

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ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted.

Table 3.

Parameter Ratings

AVDD to GND

DVDD to GND

Analog Input Voltage to GND

Reference Input Voltage to GND

Digital Input Voltage to GND

Digital Output Voltage to GND

AIN/Digital Input Current 10 mA
Operating Temperature Range

Storage Temperature Range

Maximum Junction Temperature 150°C
TSSOP

θJA Thermal Impedance 128°C/W
θJC Thermal Impedance 14°C/W

Lead Temperature, Soldering

Vapor Phase (60 sec) 215°C
Infrared (15 sec) 220°C

−0.3 V to +7 V

−0.3 V to +7 V

−0.3 V to AVDD + 0.3 V

−0.3 V to AVDD + 0.3 V

−0.3 V to DVDD + 0.3 V

−0.3 V to DVDD + 0.3 V

−40°C to +105°C

−65°C to +150°C

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

ESD CAUTION

Rev. B | Page 8 of 32

AD7792/AD7793

A

A

A

A

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PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

1

SCLK

2

CLK

3

CS

AD7792/

4

IOUT1

5

IN1(+)

IN1(–)

IN2(+)

IN2(–) REFIN(+)/AIN3(+)

(Not to Scale)

6

7

8

Figure 5. Pin Configuration

Table 4. Pin Function Descriptions

Pin No. Mnemonic Description

1 SCLK

Serial Clock Input. This serial clock input is f
triggered input, making the interface suitable for opto-isolated applications. The serial clock can be
continuous with all data transmitted in a continuous train of pulses. Alternatively, it can be a noncontinuous
clock with the information being transmitted to or from the ADC in smaller batches of data.

2 CLK

Clock In/Clock Out. The internal clock can be made available at this pin. Alternatively, the internal clock can
be disabled

, and the ADC can be driven by an external clock. This allows several ADCs to be driven from a

common clock, allowing simultaneous conversions to be performed.

3

CS

Chip Select Input. This is an active low logic input used to select the ADC. CS can be used to select the ADC
in systems with more than one device on the serial bus or as a frame synchronization signal in communicating
with the device. CS

can be hardwired low, allowing the ADC to operate in 3-wire mode with SCLK, DIN, and

DOUT used to interface with the device.

4 IOUT1

Output of Internal Excitation Current Source. The internal ex
this pin. The excitation current source is programmable so that the current can be 10 μA, 210 μA, or 1 mA.
Either IEXC1 or IEXC2 can be switched to this output.

5 AIN1(+)

6

AIN1(−) Analog Input. AIN1(−) is the negative terminal of the differential analog input pair AIN1(+)/AIN1(−).
7 AIN2(+)

8

AIN2(−) Analog Input. AIN2(−) is the negative terminal of the differential analog input pair AIN2(+)/AIN2(−).
9 REFIN(+)/AIN3(+)

Analog Input. AIN1(+) is the positive terminal of the differential analog input pair AIN1(+)/AIN1(−).

Analog Input. AIN2(+) is the positive terminal of the differential analog input pair AIN2(+)/AIN2(−).

Positive Reference Input/Analog Input. An external r
REFIN(−). REFIN(+) can lie anywhere between AV

REFIN(+) − REFIN(−) is 2.5 V, but the part functions with a reference from 0.1 V to AVDD. Alternatively, this pin
can function as AIN3(+) where AIN3(+) is the positive terminal of the differential analog input pair
AIN3(+)/AIN3(−).

10

REFIN(−)/AIN3(−)

Negative Reference Input/Analog Input. REFIN(−)
input can lie anywhere between GND and AV
negative terminal of the differential analog input pair AIN3(+)/AIN3(−).

11 IOUT2

Output of Internal Excitation Current Source. The internal ex
this pin. The excitation current source is programmable so that the current can be 10 μA, 210 μA, or 1 mA.

Either IEXC1 or IEXC2 can be switched to this output.
12 GND Ground Reference Point.
13 AVDD Supply Voltage, 2.7 V to 5.25 V.
14 DVDD

Digital Interface Supply Voltage. The logic levels for the serial interface pins are related to this supply, which

ween 2.7 V and 5.25 V. The DV

is bet

equal 5 V with DV

at 3 V or vice versa.

DD

AD7793

TOP VIEW

16

DIN

15

DOUT/RDY

14

DV

DD

13

AV

DD

12

GND

11

IOUT2

10

REFIN(–)/ AIN3(–)

9

04855-005

or data transfers to and from the ADC. The SCLK has a Schmitt-

citation current source can be made available at

eference can be applied between REFIN(+) and

and GND + 0.1 V. The nominal reference voltage

DD

is the negative reference input for REFIN. This reference

− 0.1 V. This pin also functions as AIN3(−), which is the

DD

citation current source can be made available at

voltage is independent of the voltage on AVDD; therefore, AVDD can

DD

Rev. B | Page 9 of 32

AD7792/AD7793

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Pin No. Mnemonic Description

15

16 DIN

DOUT/RDY

Serial Data Output/Data Ready Output. DOUT/RDY serves a dual purpose. It functions as a serial data output
pin to access the output shift register of the ADC. The output shift register can contain data from any of the
on-chip data or control registers. In addition, DOUT/RDY
the completion of a conversion. If the data is not read after the conversion, the pin goes high before the

next update occurs.
The DOUT/RDY
With an external serial clock, the data can be read using the DOUT/RDY pin. With CS low, the data/control
word information is placed on the DOUT/RDY
rising edge.

Serial Data Input. This serial da
transferred to the control registers within the ADC; the register selection bits of the communications
register identify the appropriate register.

operates as a data ready pin, going low to indicate

falling edge can be used as an interrupt to a processor, indicating that valid data is available.

pin on the SCLK falling edge and is valid on the SCLK

ta input is to the input shift register on the ADC. Data in this shift register is

Rev. B | Page 10 of 32