Analog Devices AD7792 3 Datasheet

3-Channel, Low Noise, Low Power, 16/24-Bit

∑-Δ

FEATURES

Up to 22.5 bits effective resoluion
RMS noise: 40 nV @ 4.17 Hz
85 nV @ 16.7 Hz
Current: 400 µA typ
Power-down: 1 µA max
Low noise programmable gain instrumentation-amp
Band gap reference with 4 ppm/°C drift typ
Update rate: 4.17 Hz to 500 Hz
3 differential inputs
Internal clock oscillator
Simultaneous 50 Hz/60 Hz rejection
Programmable current sources
On-chip bias voltage generator
Burnout currents
Power supply: 2.7 V to 5.25 V
–40°C to +105°C temperature range
Independent interface power supply
16-lead TSSOP package

INTERFACE

3-wire serial
SPI®-, QSPI™-, MICROWIRE™-, and DSP-compatible
Schmitt trigger on SCLK

APPLICATIONS

Thermocouple measurements
RTD measurements
Thermistor measurements
Gas analysis
Industrial process control
Instrumentation
Portable instrumentation
Blood analysis
Smart transmitters
Liquid/gas chromotography
6-digit DVM

ADC with On-Chip In-Amp and Reference

AD7792/AD7793

FUNCTIONAL BLOCK DIAGRAM

AIN1(+)
AIN1(–)
AIN2(+)
AIN2(–)

IOUT1

IOUT2

GND AV

V

BIAS

MUX

DD

V

DD

V

DD

GND

BAND GAP

REFERENCE

IN-AMPBUF

INTERNAL

CLOCK

Figure 1.

REFIN(+)/AIN3(+)

CLK

GENERAL DESCRIPTION

The AD7792/AD7793 is a low power, low noise, complete
analog front end for high precision measurement applications.
The AD7792/AD7793 contains a low noise 16/24-bit ∑-∆ ADC
with three differential analog inputs. The on-chip, low noise
instrumentation amplifier means that signals of small ampli­tude can be interfaced directly to the ADC. With a gain
setting of 64, the rms noise is 40 nV when the update rate
equals 4.17 Hz.

The device contains a precision low noise, low drift internal
band gap reference and can also accept an external differential
reference. Other on-chip features include programmable excita­tion current sources, burnout currents, and a bias voltage gener­ator, the bias voltage generator being used to set the common­mode voltage of a channel to AV

The device can be operated with the internal clock or, alterna­tively, an external clock can be used. The output data rate from
the part is software-programmable and can be varied from

4.17 Hz to 500 Hz.

The part operates with a power supply from 2.7 V to 5.25 V. It
consumes a current of 400 µA typical and is housed in a 16-lead
TSSOP package.

DD

/2.

REFIN(–)/AIN3(–)

GND

SERIAL

INTERFACE

Σ-∆

ADC

CONTROL

LOGIC

AD7792: 16-BIT
AD7793: 24-BIT

AND

DOUT/RDY
DIN
SCLK
CS

DV

DD

04855-001

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] © 2004 Analog Devices, Inc. All rights reserved.

AD7792/AD7793

TABLE OF CONTENTS

Specifications..................................................................................... 3

Timing Characteristics..................................................................... 6

Absolute Maximum Ratings............................................................ 8

ESD Caution.................................................................................. 8

Pin Configuration and Function Descriptions............................. 9

Output Noise and Resolution Specifications .............................. 11

External Reference...................................................................... 11

Internal Reference ...................................................................... 12

Typical Performance Characteristics ........................................... 13

On-Chip Registers.......................................................................... 14

Communications Register......................................................... 14

Status Register............................................................................. 15

Mode Register ............................................................................. 15

Configuration Register ..............................................................17

Data Register............................................................................... 18

Overview ..................................................................................... 20

Digital Interface.......................................................................... 21

Circuit Description......................................................................... 24

Analog Input Channel ............................................................... 24

Instrumentation Amplifier........................................................ 24

Bipolar/Unipolar Configuration .............................................. 24

Data Output Coding .................................................................. 24

Burnout Currents....................................................................... 25

Excitation Currents .................................................................... 25

Bias Voltage Generator .............................................................. 25

Reference ..................................................................................... 25

Reset ............................................................................................. 25

AV

Monitor ............................................................................. 26

DD

Calibration................................................................................... 26

Grounding and Layout .............................................................. 26

ID Register................................................................................... 18

IO Register................................................................................... 18

Offset Register............................................................................. 19

Full-Scale Register ...................................................................... 19

ADC Circuit Information.............................................................. 20

REVISION HISTORY

10/04—Revision 0: Initial Version

Applications..................................................................................... 28

Temperature Measurement using a Thermocouple............... 28

Temperature Measurement using an RTD.............................. 29

Outline Dimensions....................................................................... 30

Ordering Guide .......................................................................... 30

Rev. 0 | Page 2 of 32

AD7792/AD7793

SPECIFICATIONS

AVDD = 2.7 V to 5.25 V; DVDD = 2.7 V to 5.25 V; GND = 0 V; all specifications T

Table 1.

Parameter AD7792B/AD7793B1 Unit Test Conditions/Comments

ADC CHANNEL

Output Update Rate 4.17 - 500 Hz nom
No Missing Codes2 24 Bits min f
16 Bits min AD7792.
Resolution

See Tables in ADC
Description

Output Noise and Update Rates

See Tables in ADC

Description
Integral Nonlinearity ±15 ppm of FSR max
Offset Error3 ±1 µV typ
Offset Error Drift vs. Temperature4 ±10 nV/°C typ
Full-Scale Error

3, 5

±10 µV typ
Gain Drift vs. Temperature4 ±1 ppm/°C typ Gain = 1 to 16, External Reference.
±3 ppm/°C typ Gain = 32 to 128, External Reference.
Power Supply Rejection 100 dB min AIN = 1 V/Gain, Gain ≥ 4, External Reference.

ANALOG INPUTS

Differential Input Voltage Ranges ±V

/Gain V nom

REF

Absolute AIN Voltage Limits2

Unbuffered Mode GND – 30 mV V min Gain = 1 or 2.

AVDD + 30 mV V max

Buffered Mode GND + 100 mV V min Gain = 1 or 2.

AVDD – 100 mV V max

In-Amp Active GND + 300 mV V min Gain = 4 to 128.

AVDD – 1.1 V max

Common-Mode Voltage, VCM 0.5 V min VCM = (AIN(+) + AIN(–))/2, Gain = 4 to 128.

Analog Input Current

Buffered Mode or In-Amp Active

Average Input Current2 ±1 nA max Gain = 1 or 2, Update Rate < 100 Hz.

±250 pA max Gain = 4 to 128, Update Rate < 100 Hz.

Average Input Current Drift ±2 pA/°C typ

Unbuffered Mode Gain = 1 or 2.

Average Input Current ±400 nA/V typ Input current varies with input voltage.
Average Input Current Drift ±50 pA/V/°C typ

Normal Mode Rejection2

Internal Clock

@ 50 Hz, 60 Hz 65 dB min 80 dB typ, 50 ± 1 Hz, 60 ± 1 Hz, FS [3:0] = 1010.6
@ 50 Hz 80 dB min 90 dB typ, 50 ± 1 Hz, FS [3:0] = 1001.6
@ 60 Hz 90 dB min 100 dB typ, 60 ± 1 Hz, FS [3:0] = 1000.6

External Clock

@ 50 Hz, 60 Hz 80 dB min 90 dB typ, 50 ± 1 Hz, 60 ± 1 Hz, FS[3:0] = 1010.6
@ 50 Hz 94 dB min 100 dB typ, 50 ± 1 Hz, FS [3:0] = 1001.6
@ 60 Hz 90 dB min 100 dB typ, 60 ± 1 Hz, FS [3:0] = 1000.6

Common-Mode Rejection

@ DC 100 dB min AIN = 1 V/Gain, Gain ≥ 4.
@ 50 Hz, 60 Hz2 100 dB min 50 ± 1 Hz, 60 ± 1 Hz, FS [3:0] = 1010.6
@ 50 Hz, 60 Hz2 100 dB min

MIN

to T

, unless otherwise noted.

MAX

< 250 Hz, AD7793.

ADC

= REFIN(+) – REFIN(–) or Internal Reference,

V

REF

Gain = 1 to 128.

50 ± 1 Hz (FS [3:0] = 1001

6

).

1000

6

), 60 ± 1 Hz (FS [3:0] =

Rev. 0 | Page 3 of 32

AD7792/AD7793

Parameter AD7792B/AD7793B1 Unit Test Conditions/Comments

REFERENCE

Internal Reference

Internal Reference Initial Accuracy 1.17 ± 0.01% V min/max AVDD = 4 V, TA = 25°C.
Internal Reference Drift2 4 ppm/°C typ

15 ppm/°C max

Power Supply Rejection 85 dB typ

External Reference

External REFIN Voltage 2.5 V nom REFIN = REFIN(+) – REFIN(–).
Reference Voltage Range2 0.1 V min

AVDD V max

When V
limited to 0.9 × V

Absolute REFIN Voltage Limits2 GND – 30 mV V min

AV

+ 30 mV V max

DD

Average Reference Input Current 400 nA/V typ
Average Reference Input Current

±0.03 nA/V/°C typ

Drift

Normal Mode Rejection

Same as for Analog
Inputs

Common-Mode Rejection 100 dB typ

EXCITATION CURRENT SOURCES

(IEXC1 and IEXC2)
Output Current 10/210/1000 µA nom
Initial Tolerance at 25°C ±5 % typ
Drift 200 ppm/°C typ
Current Matching ±0.5 % typ Matching between IEXC1 and iEXC2. V
Drift Matching 50 ppm/°C typ
Line Regulation (VDD) 2 %/V typ AVDD = 5 V ± 5%.
Load Regulation 0.2 %/V typ
Output Compliance AVDD – 0.65 V max 10 µA or 210 µA currents selected.
AVDD – 1.1 V max 1 mA currents selected.
GND – 30 mV V min

TEMPERATURE SENSOR

Accuracy
Sensitivity

± 2

0.81

°C typ
mV/°C typ

Applies if user calibrates the temperature sensor.

BIAS VOLTAGE GENERATOR

V

AVDD/2 V nom

BIAS

V

Generator Start-Up Time See Figure 10 ms/nF typ Dependent on the capacitance on the AIN pin.

BIAS

INTERNAL/EXTERNAL CLOCK

Internal Clock

Frequency2 64 ± 3% KHz min/max
Duty Cycle 50:50 % typ

External Clock

Frequency 64 KHz nom

A 128 kHz external clock can be used if the
divide by 2 function is used (Bit CLK1 = CLK0 =

1).

Duty Cycle 45:55 to 55:45 % typ

Applies for external 64 kHz clock. A 128 kHz clock
can have a less stringent duty cycle.

LOGIC INPUTS

2

CS

V

, Input Low Voltage 0.8 V max DVDD = 5 V.

INL

, Input High Voltage

V

INH

0.4

2.0

V max
V min

DV
DV

= AVDD , the differential input must be

REF

= 3 V.

DD

= 3 V or 5 V.

DD

/gain if the in-amp is active.

REF

OUT

= 0 V.

Rev. 0 | Page 4 of 32

AD7792/AD7793

Parameter AD7792B/AD7793B1 Unit Test Conditions/Comments

SCLK, CLK and DIN (Schmitt-Triggered

Input)

2

VT(+) 1.4/2 V min/V max DVDD = 5 V.
VT(–) 0.8/1.7 V min/V max DVDD = 5 V.
VT(+) – VT(–) 0.1/0.17 V min/V max DVDD = 5 V.
VT(+) 0.9/2 V min/V max DVDD = 3 V.
VT(–) 0.4/1.35 V min/V max DVDD = 3 V.
VT(+) -− VT(–)

Input Currents
Input Capacitance

LOGIC OUTPUTS (INCLUDING CLK)

VOH, Output High Voltage2 DVDD – 0.6 V min DVDD = 3 V, I
VOL, Output Low Voltage2 0.4 V max DVDD = 3 V, I
VOH, Output High Voltage2 4 V min DVDD = 5 V, I
VOL, Output Low Voltage2 0.4 V max

Floating-State Leakage Current ±10 µA max
Floating-State Output Capacitance 10 pF typ
Data Output Coding Offset Binary

SYSTEM CALIBRATION2

Full-Scale Calibration Limit +1.05 × FS V max
Zero-Scale Calibration Limit −1.05 × FS V min
Input Span 0.8 × FS V min

2.1 × FS V max

POWER REQUIREMENTS7

Power Supply Voltage

AVDD – GND 2.7/5.25 V min/max
DVDD – GND 2.7/5.25 V min/max

Power Supply Currents

IDD Current 140 µA max

185 µA max

400 µA max

500 µA max

IDD (Power-Down Mode) 1 µA max

1

Temperature range –40°C to +105°C.

2

Specification is not production tested but is supported by characterization data at initial product release.

3

Following a calibration, this error is in the order of the noise for the programmed gain and update rate selected.

4

Recalibration at any temperature removes these errors.

5

Full-scale error applies to both positive and negative full-scale and applies at the factory calibration conditions (AVDD = 4 V, Gain = 1, TA = 25°C).

6

FS[3:0] are the four bits used in the mode register to select the output word rate.

7

Digital inputs equal to DVDD or GND with excitation currents and bias voltage generator disabled.

0.06/0.13 V min/V max DV

±10
10

µA max
pF typ

= 3 V.

DD

VIN = DVDD or GND.
All digital inputs.

SOURCE

= 100 µA.

SINK

SOURCE

DV

= 5 V, I

DD

= 1.6 mA (DOUT/RDY)/800 µA

SINK

= 100 µA.

= 200 µA.

(CLK).

110 µA typ @ AV

= 3 V, 125 µA typ @ AVDD = 5

DD

V, Unbuffered Mode, Ext. Ref.
130 µA typ @ AV

= 3 V, 165 µA typ @ AVDD = 5

DD

V, Buffered Mode, Gain = 1 or 2, Ext Ref.
300 µA typ @ AV

= 3 V, 350 µA typ @ AVDD = 5

DD

V, Gain = 4 to 128, Ext. Ref.
400 µA typ @ AV

= 3 V, 450 µA typ @ AVDD = 5

DD

V, Gain = 4 to 128, Int Ref.

Rev. 0 | Page 5 of 32

AD7792/AD7793

TIMING CHARACTERISTICS

AVDD = 2.7 V to 5.25 V; DVDD = 2.7 V to 5.25 V; GND = 0 V, input logic 0 = 0 V, input logic 1 = DVDD, unless otherwise noted.

Table 2.

Parameter

t3 100 ns min SCLK High Pulse Width
t4 100 ns min SCLK Low Pulse Width
Read Operation

t1 0 ns min
60 ns max DVDD = 4.75 V to 5.25 V
80 ns max DVDD = 2.7 V to 3.6 V
t
60 ns max DVDD = 4.75 V to 5.25 V
80 ns max DVDD = 2.7 V to 3.6 V
t
80 ns max
t6 0 ns min
t7 10 ns min

Write Operation

t8 0 ns min
t9 30 ns min Data Valid to SCLK Edge Setup Time

t10 25 ns min Data Valid to SCLK Edge Hold Time
t11 0 ns min

1, 2

Limit at T

3

0 ns min SCLK Active Edge to Data Valid Delay4

2

5, 6

10 ns min

5

MIN

, T

(B Version) Unit Conditions/Comments

MAX

Falling Edge to DOUT/RDY Active Time

CS

Bus Relinquish Time after CS

SCLK Inactive Edge to CS
SCLK Inactive Edge to DOUT/RDY

Falling Edge to SCLK Active Edge Setup Time4

CS

Rising Edge to SCLK Edge Hold Time

CS

Inactive Edge

Inactive Edge

High

1

Sample tested during initial release to ensure compliance. All input signals are specified with tR = tF = 5 ns (10% to 90% of DVDD) and timed from a voltage level of 1.6 V.

2

See Figure 3 and Figure 4.

3

These numbers are measured with the load circuit of Figure 2 and defined as the time required for the output to cross the VOL or VOH limits.

4

SCLK active edge is falling edge of SCLK.

5

These numbers are derived from the measured time taken by the data output to change 0.5 V when loaded with the circuit of Figure 2. The measured number is then

extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the times quoted in the timing characteristics are the true bus
relinquish times of the part and, as such, are independent of external bus loading capacitances.

6

RDY

returns high after a read of the ADC. In single conversion mode and continuous conversion mode, the same data can be read again, if required, while
although care should be taken to ensure that subsequent reads do not occur close to the next output update. In continuous read mode, the digital word can be read
only once.

RDY

is high,

I

(1.6mA WITH DVDD = 5V,

SINK

100µA WITH DV

TO

OUTPUT

PIN

50pF

I

SOURCE

100µA WITH DV

Figure 2. Load Circuit for Timing Characterization

= 3V)

DD

1.6V

(200µA WITH DVDD = 5V,

= 3V)

DD

04855-002

Rev. 0 | Page 6 of 32

AD7792/AD7793

S

CS (I)

t

t

1

DOUT/RDY (O)

SCLK (I)

t

2

I = INPUT, O = OUTPUT

MSB LSB

t

3

t

4

Figure 3. Read Cycle Timing Diagram

CS (I)

6

t

5

t

7

04855-003

t

11

04855-004

CLK (I)

DIN (I)

I = INPUT, O = OUTPUT

t

8

t

9

t

10

MSB LSB

Figure 4. Write Cycle Timing Diagram

Rev. 0 | Page 7 of 32

AD7792/AD7793

ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted.

Table 3.

Parameter Ratings

AVDD to GND
DVDD to GND −0.3 V to +7 V

−0.3 V to +7 V
Analog Input Voltage to GND −0.3 V to AVDD + 0.3 V
Reference Input Voltage to GND −0.3 V to AVDD + 0.3 V
Digital Input Voltage to GND −0.3 V to DVDD + 0.3 V
Digital Output Voltage to GND −0.3 V to DVDD + 0.3 V
AIN/Digital Input Current 10 mA
Operating Temperature Range −40°C to +85°C
Storage Temperature Range −65°C to +150°C
Maximum Junction Temperature 150°C
TSSOP

θJA Thermal Impedance 128°C/W
θJC Thermal Impedance 14°C/W

Lead Temperature, Soldering

Vapor Phase (60 sec) 215°C
InfraRed (15 sec) 220°C

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.

Rev. 0 | Page 8 of 32

AD7792/AD7793

A

A

A

A

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

SCLK

1
2

CLK

IOUT1

IN1(+)
IN1(–)
IN2(+)
IN2(–)

CS

AD7792/

3

AD7793

4

TOP VIEW

5

(Not to Scale)

6
7
8

Figure 5. Pin Configuration

Table 4. Pin Function Descriptions

Pin
No.

Mnemonic Description

1 SCLK

Serial Clock Input for Data Transfers to and from the ADC. The SCLK has a Schmitt-triggered input, making the
interface suitable for opto-isolated applications. The serial clock can be continuous with all data transmitted in a
continuous train of pulses. Alternatively, it can be a noncontinuous clock with the information being
transmitted to or from the ADC in smaller batches of data.

2 CLK

Clock In/Clock Out. The internal clock can be made available at this pin. Alternatively, the internal clock can be
disabled and the ADC can be driven by an external clock. This allows several ADCs to be driven from a common
clock, allowing simultaneous conversions to be performed.

3

Chip Select Input. This is an active low logic input used to select the ADC. CS can be used to select the ADC in

CS

systems with more than one device on the serial bus or as a frame synchronization signal in communicating
with the device. CS

can be hardwired low, allowing the ADC to operate in 3-wire mode with SCLK, DIN, and

DOUT used to interface with the device.

4 IOUT1 Output of Internal Excitation Current Source.

The internal excitation current source can be made available at this pin. The excitation current source is
programmable so that the current can be 10 µA, 210 µA, or 1 mA. Either IEXC1 or IEXC2 can be switched to this

output.
5 AIN1(+) Analog Input. AIN1(+) is the positive terminal of the differential analog input pair AIN1(+)/AIN1(−).
6 AIN1(−) Analog Input. AIN1(−) is the negative terminal of the differential analog input pair AIN1(+)/AIN1(−).
7 AIN2(+) Analog Input. AIN2(+) is the positive terminal of the differential analog input pair AIN2(+)/AIN2(−).
8 AIN2(−) Analog Input. AIN2(−) is the negative terminal of the differential analog input pair AIN2(+)/AIN2(−).
9 REFIN(+)/AIN3(+) Positive Reference Input/Analog Input.

An external reference can be applied between REFIN(+) and REFIN(–). REFIN(+) can lie anywhere between AV

and GND + 0.1 V. The nominal reference voltage (REFIN(+) – REFIN(−)) is 2.5 V, but the part functions with a

reference from 0.1 V to AV

.

DD

Alernatively, this pin can function as AIN3(+) where AIN3(+) is the positive terminal of the differential analog

input pair AIN3(+)/AIN3(−).
10 REFIN(−)/AIN3(−) Negative Reference Input/Analog Input.

REFIN(−) is the negative reference input for REFIN. This reference input can lie anywhere between GND and

AV

− 0.1 V.

DD

This pin also functions as AIN3(−) which is the negative terminal of the differential analog input pair

AIN3(+)/AIN3(−).
11 IOUT2 Output of Internal Excitation Current Source.

The internal excitation current source can be made available at this pin. The excitation current source is

programmable so that the current can be 10 µA, 210 µA, or 1 mA. Either IEXC1 or IEXC2 can be switched to this

output
12 GND Ground Reference Point.
13 AVDD Supply Voltage, 2.7 V to 5.25 V.
14 DVDD

Digital Interface Supply Voltage. The logic levels for the serial interface pins are related to this supply, which is

between 2.7 V and 5.25 V. The DV

with DV

at 3 V or vice versa.

DD

voltage is independent of the voltage on AVDD; therefore, AVDD can equal 5 V

DD

DIN

16
15

DOUT/RDY

14

DV

DD

13

AV

DD

GND

12

IOUT2

11

REFIN(–)/AIN3(–)

10

REFIN(+)/AIN3(+)

0

04855-005

DD

Rev. 0 | Page 9 of 32

AD7792/AD7793

Pin
No. Mnemonic Description

15

DOUT/RDY

16 DIN

Serial Data Output/Data Ready Output. DOUT/RDY serves a dual purpose. It functions as a serial data output

pinto access the output shift register of the ADC. The output shift register can contain data from any of the on­chip data or control registers. In addition, DOUT/RDY
completion of a conversion. If the data is not read after the conversion, the pin will go high before the next
update occurs.

The DOUT/RDY
With an external serial clock, the data can be read using the DOUT/RDY
information is placed on the DOUT/RDY

Serial Data Input to the input shift register on the ADC. Data in this shift register is transferred to the control
registers within the ADC; the register selection bits of the communications register identify the appropriate
register.

operates as a data ready pin, going low to indicate the

falling edge can be used as an interrupt to a processor, indicating that valid data is available.

pin. With CS low, the data/control word

pin on the SCLK falling edge and is valid on the SCLK rising edge.

Rev. 0 | Page 10 of 32