Analog Devices AD7791 Datasheet

Low Power, Buffered 24-Bit

FEATURES

Power

Supply: 2.5 V to 5.25 V operation
Normal: 75 µA max
Power-down: 1 µA max

RMS noise: 1.1 µV at 9.5 Hz update rate

19.5-bit p-p resolution (22 bits effective resolution)
Integral nonlinearity: 3.5 ppm typical
Simultaneous 50 Hz and 60 Hz rejection
Internal clock oscillator
Rail-to-rail input buffer

monitor channel

V

DD

Temperature range: –40°C to +105°C
10-lead MSOP

INTERFACE

3-wire serial
SPI®, QSPI™, MICROWIRE™, and DSP compatible
Schmitt trigger on SCLK

APPLICATIONS

Smart transmitters
Battery applications
Portable instrumentation
Sensor measurement
Temperature measurement
Pressure measurement
Weigh scales
4 to 20 mA loops

Sigma-Delta ADC

AD7791

FUNCTIONAL BLOCK DIAGRAM

V

GND REFIN(+) REFIN(–)

DD

V

DD

AIN(+)

AIN(–)

GND

BUF

AD7791

Σ-∆

ADC

Figure 1.

GENERAL DESCRIPTION

The AD7791 is a low power, complete analog front end for
low frequency measurement applications. It contains a low
noise 24-bit ∑-∆ ADC with one differential input that can be
buffered or unbuffered.

The device operates from an internal clock. Therefore, the user
does not have to supply a clock source to the device. The output
data rate from the part is software programmable and can be
varied from 9.5 Hz to 120 Hz, with the rms noise equal to

1.1 µV at the lower update rate. The internal clock frequency
can be divided by a factor of 2, 4, or 8, which leads to a reduc­tion in the current consumption. The update rate, cutoff
frequency, and settling time will scale with the clock frequency.

The part operates with a power supply from 2.5 V to 5.25 V.
When operating from a 3 V supply, the power dissipation for
the part is 225 µW maximum. It is housed in a 10-lead MSOP.

CLOCK

SERIAL

INTERFACE

04227-0-001

DOUT/RDY

DIN

SCLK

CS

Rev. 0

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However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.

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Tel: [phone]
Fax: [phone] © 2003 Analog Devices, Inc. All rights reserved.

www.analog.com

AD7791

TABLE OF CONTENTS

AD7791—Specifications.................................................................. 3

ADC Circuit Information.............................................................. 14

Timing Characteristics..................................................................... 5

Absolute Maximum Ratings............................................................ 7

Pin Configuration and Function Descriptions............................. 8

Typical Performance Characteristics ............................................. 9

On-Chip Registers.......................................................................... 10

Communications Register

(RS1, RS0 = 0, 0) ......................................................................... 10

Status Register

(RS1, RS0 = 0, 0; Power-on/Reset = 0x8C).............................. 11

Mode Register

(RS1, RS0 = 0, 1; Power-on/Reset = 0x02)............................... 11

Filter Register

(RS1, RS0 = 1, 0; Power-on/Reset = 0x04)............................... 12

Data Register

(RS1, RS0 = 1, 1; Power-on/Reset = 0x000000) ...................... 13

Overview ..................................................................................... 14

Noise Performance ..................................................................... 14

Reduced Current Modes ........................................................... 14

Digital Interface.......................................................................... 15

Single Conversion Mode....................................................... 16

Continuous Conversion Mode............................................. 16

Continuous Read Mode ........................................................ 17

Circuit Description......................................................................... 18

Analog Input Channel ............................................................... 18

Bipolar/Unipolar Configuration .............................................. 18

Data Output Coding .................................................................. 18

Reference Input........................................................................... 18

VDD Monitor................................................................................ 19

Grounding and Layout .............................................................. 19

Outline Dimensions....................................................................... 20

REVISION HISTORY

Revision 0: Initial Version

Rev. 0 | Page 2 of 20

AD7791

AD7791—SPECIFICATIONS1

Table 1. (VDD = 2.5 V to 5.25 V; REFIN(+) = 2.5 V; REFIN(–) = GND; GND = 0 V; CDIV1 = CDIV0 = 0;
all specifications T

MIN

to T

Parameter AD7791B Unit Test Conditions/Comments

ADC CHANNEL SPECIFICATION

Output Update Rate 9.5 Hz min nom
120 Hz max nom
ADC CHANNEL

No Missing Codes2 24 Bits min

Resolution 19.5 Bits p-p 9.5 Hz Update Rate

Output Noise 1.1 µV rms typ

Integral Nonlinearity ±15 ppm of FSR max 3.5 ppm typ

Offset Error ±3 µV typ

Offset Error Drift vs. Temperature ±10 nV/°C typ

Full-Scale Error3 ±10 µV typ

Gain Drift vs. Temperature ±0.5 ppm/°C typ

Power Supply Rejection 90 dB min 100 dB typ, AIN = 1 V
ANALOG INPUTS

Differential Input Voltage Ranges ±REFIN V nom REFIN = REFIN(+) – REFIN(–);

Absolute AIN Voltage Limits2 GND + 100 mV V min Buffered Mode of Operation
V

Analog Input Current Buffered Mode of Operation

Average Input Current2 ±1 nA max
Average Input Current Drift ±5 pA/°C typ

Absolute AIN Voltage Limits2 GND – 30 mV V min Unbuffered Mode of Operation
V

Analog Input Current

Average Input Current ±400 nA/V typ
Average Input Current Drift ±50 pA/V/°C typ

Normal Mode Rejection2

@ 50 Hz, 60 Hz 65 dB min 73 dB typ, 50 ± 1 Hz, 60 ± 1 Hz, FS[2:0] = 1004
@ 50 Hz 80 dB min 90 dB typ, 50 ± 1 Hz, FS[2:0] = 1014
@ 60 Hz 80 dB min 90 dB typ, 60 ± 1 Hz, FS[2:0] = 0114

Common Mode Rejection AIN = 1 V

@DC 90 dB min 100 dB typ, FS[2:0] = 1004
@ 50 Hz, 60 Hz2 100 dB min 50 ± 1 Hz (FS[2:0] = 1014), 60 ± 1 Hz (FS[2:0] = 0114)

REFERENCE INPUT

REFIN Voltage 2.5 V nom REFIN = REFIN(+) – REFIN(–)

Reference Voltage Range2 0.1 V min
V

Absolute REFIN Voltage Limits2 GND – 30 mV V min
V

Average Reference Input Current 0.5 µA/V typ

Average Reference Input Current Drift ±0.03 nA/V/°C typ

1

Temperature Range –40°C to +105°C.

2

Specification is not production tested but is supported by characterization data at initial product release.

3

Full-scale error applies to both positive and negative full-scale and applies at the factory calibration conditions (VDD = 4 V).

4

FS[2:0] are the three bits used in the filter register to select the output word rate.

, unless otherwise noted.)

MAX

DD

DD

DD

DD

Update Rate ≤ 20 Hz

– 100 mV V max

+ 30 mV V max

Unbuffered Mode of Operation
Input current varies with input voltage.

V max

+ 30 mV V max

Rev. 0 | Page 3 of 20

AD7791

SPECIFICATIONS (continued)

Parameter AD7791B Unit Test Conditions/Comments

REFERENCE INPUT (continued)
Normal Mode Rejection2

@ 50 Hz, 60 Hz 65 dB min 73 dB typ, 50 ± 1 Hz, 60 ± 1 Hz, FS[2:0] = 1004
@ 50 Hz 80 dB min 90 dB typ, 50 ± 1 Hz, FS[2:0] = 1014
@ 60 Hz 80 dB min 90 dB typ, 60 ± 1 Hz, FS[2:0] = 0114

Common Mode Rejection AIN = 1 V

@ DC 100 dB typ FS[2:0] = 1004
@ 50 Hz, 60 Hz 110 dB typ 50 ± 1 Hz (FS[2:0] = 1014), 60 ± 1 Hz (FS[2:0] = 0114)

LOGIC INPUTS

All Inputs Except SCLK2

V

, Input Low Voltage 0.8 V max VDD = 5 V

INL

0.4 V max VDD = 3 V
V

, Input High Voltage 2.0 V min VDD = 3 V or 5 V

INH

SCLK Only (Schmitt-Triggered Input)2
VT(+) 1.4/2 V min/V max VDD = 5 V
VT(–) 0.8/1.4 V min/V max VDD = 5 V
VT(+) – VT(–) 0.3/0.85 V min/V max VDD = 5 V
VT(+) 0.9/2 V min/V max VDD = 3 V
VT(–) 0.4/1.1 V min/V max VDD = 3 V
VT(+) - VT(–) 0.3/0.85 V min/V max VDD = 3 V

Input Currents ±1 µA max VIN = VDD or GND
Input Capacitance 10 pF typ All Digital Inputs

LOGIC OUTPUTS

VOH, Output High Voltage2 V
VOL, Output Low Voltage2 0.4 V max VDD = 3 V, I
VOH, Output High Voltage2 4 V min VDD = 5 V, I
VOL, Output Low Voltage2 0.4 V max VDD = 5 V, I
Floating-State Leakage Current ±1 µA max
Floating-State Output Capacitance 10 pF typ
Data Output Coding Offset Binary

POWER REQUIREMENTS5

Power Supply Voltage

VDD – GND 2.5/5.25 V min/max

Power Supply Currents

IDD Current6 75 µA max 65 µA typ, VDD = 3.6 V, Unbuffered Mode

145 µA max 130 µA typ, VDD = 3.6 V, Buffered Mode
80 µA max 73 µA typ, VDD = 5.25 V, Unbuffered Mode
160 µA max 145 µA typ, VDD = 5.25 V, Buffered Mode

IDD (Power-Down Mode) 1 µA max

1

– 0.6 V min VDD = 3 V, I

DD

= 100 µA

SOURCE

= 100 µA

SINK

= 200 µA

SOURCE

= 1.6 mA

SINK

5

Digital inputs equal to VDD or GND.

6

The current consumption can be further reduced by using the ADC in one of the low power modes (see Table 14).

Rev. 0 | Page 4 of 20

AD7791

MIN

1, 2

, T

MAX

Unit Conditions/Comments

Falling Edge to DOUT/RDY Active Time

CS

Bus Relinquish Time after CS

SCLK Inactive Edge to CS
SCLK Inactive Edge to DOUT/RDY

Falling Edge to SCLK Active Edge Setup Time4

CS

Rising Edge to SCLK Edge Hold Time

CS

Inactive Edge

Inactive Edge

High

TIMING CHARACTERISTICS

Table 2. (VDD = 2.5 V to 5.25 V; GND = 0 V, REFIN(+) = 2.5 V, REFIN(–) = GND, CDIV1 = CDIV0 = 0, Input Logic 0 = 0 V,
Input Logic 1 = V

Parameter

t3 100 ns min SCLK High Pulsewidth
t4 100 ns min SCLK Low Pulsewidth
Read Operation
t1 0 ns min
60 ns max VDD = 4.75 V to 5.25 V
80 ns max VDD = 2.5 V to 3.6 V

3

t

0 ns min SCLK Active Edge to Data Valid Delay4

2

60 ns max VDD = 4.75 V to 5.25 V
80 ns max VDD = 2.5 V to 3.6 V

5, 6

t

10 ns min

5

80 ns max
t6 100 ns max
t7 10 ns min

Write Operation
t8 0 ns min

t9 30 ns min Data Valid to SCLK Edge Setup Time
t10 25 ns min Data Valid to SCLK Edge Hold Time
t11 0 ns min

, unless otherwise noted.)

DD

Limit at T
(B Version)

1

Sample tested during initial release to ensure compliance. All input signals are specified with tR = tF = 5 ns (10% to 90% of VDD) and timed from a voltage level of 1.6 V.

2

See Figure 3 and Figure 4.

3

These numbers are measured with the load circuit of Figure 2 and defined as the time required for the output to cross the VOL or VOH limits.

4

SCLK active edge is falling edge of SCLK.

5

These numbers are derived from the measured time taken by the data output to change 0.5 V when loaded with the circuit of Figure 2. The measured number is then

extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the times quoted in the timing characteristics are the true bus
relinquish times of the part and, as such, are independent of external bus loading capacitances.

6

RDY

returns high after a read of the ADC. In single conversion mode and continuous conversion mode, the same data can be read again, if required, while
although care should be taken to ensure that subsequent reads do not occur close to the next output update. In continuous read mode, the digital word can be read
only once.

RDY

is high,

Rev. 0 | Page 5 of 20

AD7791

I

(1.6mA WITH VDD = 5V,

SINK

TO OUTPUT

PIN

50pF

100µA WITH V

I

SOURCE

100µA WITH V

= 3V)

DD

1.6V

(200µA WITH VDD = 5V,

= 3V)

DD

04227-0-002

Figure 2. Load Circuit for Timing Characterization

CS (I)

t

6

t

5

7

04227-0-003

DOUT/RDY (O)

SCLK (I)

t

1

MSB LSB

t

2

I = INPUT, O = OUTPUT

t

t

3

t

4

Figure 3. Read Cycle Timing Diagram

CS (I)

t

11

04227-0-004

SCLK (I)

DIN (I)

I = INPUT, O = OUTPUT

t

8

t

9

t

10

MSB LSB

Figure 4. Write Cycle Timing Diagram

Rev. 0 | Page 6 of 20