Analog Devices AD7788 9 a Datasheet

A

A

Low Power, 16-Bit and 24-Bit,

FEATURES

AD7788: 16-bit resolution
AD7789: 24-bit resolution
Power

Supply: 2.5 V to 5.25 V operation
Normal: 75 µA maximum

Power-down: 1 µA maximum
RMS noise: 1.5 µV
AD7788: 16-bit p-p resolution
AD7789: 19-bit p-p resolution (21.5 bits effective)
Integral nonlinearity: 3.5 ppm typical
Simultaneous 50 Hz and 60 Hz rejection
Internal clock oscillator

monitor channel

V

DD

10-lead MSOP

INTERFACE

3-wire serial
SPI®-, QSPI™-, MICROWIRE™-, and DSP-compatible
Schmitt trigger on SCLK

APPLICATIONS

Smart transmitters
Battery applications
Portable instrumentation
Sensor measurement
Temperature measurement
Pressure measurement
Weigh scales
4 to 20 mA loops

Sigma-Delta ADCs

AD7788/AD7789

FUNCTIONAL BLOCK DIAGRAM

REFIN(+) REFIN(–) V

AD7788/
AD7789

IN(+)

IN(–)

*AD7788: 16-BIT ADC
AD7789: 24-BIT ADC

Σ-∆

ADC*

Figure 1.

GENERAL DESCRIPTION

The AD7788/AD7789 are low power, low noise, analog front
ends for low frequency measurement applications. The AD7789
contains a low noise, 24-bit, ∑-∆ ADC with one differential
input. The AD7788 is a 16-bit version of the AD7789.

The devices operate from an internal clock. Therefore, the
user does not have to supply a clock source to the devices.
The output data rate is 16.6 Hz, which gives simultaneous
50 Hz/60 Hz rejection.

The parts operate with a single power supply from 2.5 V to

5.25 V. When operating from a 3 V supply, the power dissi­pation for the part is 225 µW maximum. The AD7788/AD7789
are housed in 10-lead MSOPs.

GND

CLOCK

SERIAL

INTERFACE

AND

CONTROL

LOGIC

DD

DOUT/RDY
DIN
SCLK
CS

03539-001

Rev. A

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infringements of patents or other rights of third parties that may result from its use.
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AD7788/AD7789

TABLE OF CONTENTS

AD7789 Specifications..................................................................... 3

AD7788 Specifications..................................................................... 4

AD7788/AD7789 Specifications..................................................... 5

Timing Characteristics..................................................................... 6

Absolute Maximum Ratings............................................................ 8

ESD Caution.................................................................................. 8

Pin Configuration and Function Descriptions............................. 9

Typical Performance Characteristics ...........................................10

On-Chip Registers.......................................................................... 11

Communications Register......................................................... 11

Status Register ............................................................................. 12

Mode Register ............................................................................. 13

Data Register ............................................................................... 13

REVISION HISTORY

ADC Circuit Information.............................................................. 14

Noise Performance ..................................................................... 14

Digital Interface.......................................................................... 14

Circuit Description......................................................................... 17

Analog Input Channel ............................................................... 17

Bipolar/Unipolar Configuration .............................................. 17

Data Output Coding .................................................................. 17

Reference Input........................................................................... 17

V

Monitor ................................................................................ 18

DD

Grounding and Layout .............................................................. 18

Outline Dimensions ....................................................................... 19

Ordering Guide .......................................................................... 19

11/04—Rev. 0 to Rev. A

Updated Format..................................................................Universal

Added Footnote 2 to Integral Nonlinearity A Grade................... 4

Changes to Figure 5.......................................................................... 9

Updated Outline Dimensions....................................................... 19

Changes to Ordering Guide.......................................................... 19

8/03—Revision 0: Initial Version

Rev. A | Page 2 of 20

AD7788/AD7789

AD7789 SPECIFICATIONS

VDD = 2.5 V to 5.25 V; REFIN(+) = 2.5 V; REFIN(−) = GND; GND = 0 V; all specifications T

Table 1.

Parameter1 AD7789B Unit Test Conditions/Comments

ADC CHANNEL SPECIFICATION

Output Update Rate 16.6 Hz nom

ADC CHANNEL

No Missing Codes

2

24 Bits min
Resolution 19 Bits p-p
Output Noise 1.5 µV rms typ
Integral Nonlinearity ±15 ppm of FSR max
Offset Error ±3 µV typ
Offset Error Drift vs. Temperature ±10 nV/°C typ
Full-Scale Error

3

±10 µV typ
Gain Drift vs. Temperature ±0.5 ppm/°C typ
Power-Supply Rejection 90 dB min 100 dB typ, AIN = 1 V

ANALOG INPUTS

Differential Input Voltage Ranges ±REFIN V nom REFIN = REFIN(+) – REFIN(−)
Absolute AIN Voltage Limits2 GND − 30 mV V min
V

+ 30 mV V max

DD

Analog Input Current Input current varies with input voltage

Average Input Current2 ±400 nA/V typ
Average Input Current Drift ±50 pA/V/°C typ

Normal-Mode Rejection2

@ 50 Hz, 60 Hz 65 dB min 50 ± 1 Hz, 60 ± 1 Hz

Common-Mode Rejection AIN = 1 V

@ DC 90 dB min 100 dB typ
@ 50 Hz, 60 Hz2 100 dB min 50 ± 1 Hz, 60 ± 1 Hz

REFERENCE INPUT

REFIN Voltage 2.5 V nom REFIN = REFIN(+)− REFIN(−)
Reference Voltage Range
V
Absolute REFIN Voltage Limits
V

2

2

0.1 V min

DD

V max

GND − 30 mV V min

+ 30 mV V max

DD

Average Reference Input Current 0.5 µA/V typ
Average Reference Input Current Drift ±0.03 nA/V/°C typ
Normal-Mode Rejection2

@ 50 Hz, 60 Hz 65 dB min 50 ± 1 Hz, 60 ± 1 Hz

Common-Mode Rejection AIN = 1 V

@ DC 110 dB typ
@ 50 Hz, 60 Hz 110 dB typ 50 ± 1 Hz, 60 ± 1 Hz

1

Temperature range −40°C to +105°C.

2

Specification is not production tested but is supported by characterization data at initial product release.

3

Full-scale error applies to both positive and negative full scale and applies at the factory calibration conditions (VDD = 4 V).

MIN

to T

, unless otherwise noted.

MAX

Rev. A | Page 3 of 20

AD7788/AD7789

AD7788 SPECIFICATIONS

VDD = 2.5 V to 5.25 V (B grade); VDD = 2.7 V to 5.25 V (A grade); REFIN(+) = 2.5 V; REFIN(−) = GND; GND = 0 V; all specifications

to T

T

MIN

Table 2.

Parameter1 AD7788 A, AD7788B Unit Test Conditions/Comments

ADC CHANNEL SPECIFICATION
Output Update Rate 16.6 Hz nom
ADC CHANNEL
No Missing Codes
Resolution 16 Bits p-p
Output Noise 1.5 µV rms typ
Integral Nonlinearity ±15 ppm of FSR max B grade
±50 ppm of FSR max A grade2
Offset Error ±3 µV typ
Offset Error Drift vs. Temperature ±10 nV/°C typ
Full-Scale Error
Gain Drift vs. Temperature ±0.5 ppm/°C typ
Power-Supply Rejection 90 dB min B grade
90 dB typ A grade
ANALOG INPUTS
Differential Input Voltage Ranges ±REFIN V nom REFIN = REFIN(+) − REFIN(−)
Absolute AIN Voltage Limits2 GND – 30 mV V min
V
Analog Input Current

Average Input Current2 ±400 nA/V typ
Average Input Current Drift ±50 pA/V/°C typ
Normal-Mode Rejection2
@ 50 Hz, 60 Hz 65 dB min B grade, 50 ± 1 Hz, 60 ± 1 Hz
60 dB min A grade, 50 ± 1 Hz, 60 ± 1 Hz
Common-Mode Rejection AIN = 1 V
@ DC 90 dB min B grade, 100 dB typ
90 dB typ A grade
@ 50 Hz, 60 Hz2 100 dB min B grade, 50 ± 1 Hz, 60 ± 1 Hz
100 dB typ A grade, 50 ± 1 Hz, 60 ± 1 Hz
REFERENCE INPUT
REFIN Voltage 2.5 V nom REFIN = REFIN(+) − REFIN(−)
Reference Voltage Range2 0.1 V min
V
Absolute REFIN Voltage Limits2 GND − 30 mV V min
V
Average Reference Input Current 0.5 µA/V typ
Average Reference Input Current Drift ±0.03 nA/V/°C typ
Normal-Mode Rejection2
@ 50 Hz, 60 Hz 65 dB min B grade, 50 ± 1 Hz, 60 ± 1 Hz
60 dB min A grade
Common-Mode Rejection AIN = 1 V
@ DC 100 dB typ
@ 50 Hz, 60 Hz 110 dB typ 50 ± 1 Hz, 60 ± 1 Hz

1

Temperature range: B grade, −40°C to +105°C; A grade, −40°C to +85°C.

2

Specification is not production tested but is supported by characterization data at initial product release.

3

Full-scale error applies to both positive and negative full scale and applies at the factory calibration conditions (VDD = 4 V).

, unless otherwise noted.

MAX

2

3

16 Bits min

±10 µV typ

+ 30 mV V max

DD

DD

+ 30 mV V max

DD

V max

Input current varies with input
voltage

Rev. A | Page 4 of 20

AD7788/AD7789

AD7788/AD7789 SPECIFICATIONS

Table 3.

Parameter AD7788A, AD7788B/AD7789B Unit Test Conditions/Comments

LOGIC INPUTS

All Inputs Except SCLK

V

, Input Low Voltage 0.8 V max VDD = 5 V

INL

0.4 V max VDD = 3 V
V

, Input High Voltage 2.0 V min VDD = 3 V or 5 V

INH

SCLK Only (Schmitt-Triggered Input)

VT(+) 1.4/2 V min/V max VDD = 5 V
VT(−) 0.8/1.4 V min/V max VDD = 5 V
VT(+) − VT(−) 0.3/0.85 V min/V max VDD = 5 V
VT(+) 0.9/2 V min/V max VDD = 3 V
VT(−) 0.4/1.1 V min/V max VDD = 3 V

VT(+) − VT(−) 0.3/0.85 V min/V max VDD = 3 V
Input Currents ±1 µA max VIN = V
Input Capacitance 10 pF typ All digital inputs

LOGIC OUTPUTS

VOH, Output High Voltage1 V
VOL, Output Low Voltage1 0.4 V max VDD = 3 V, I
VOH, Output High Voltage1 4 V min VDD = 5 V, I
VOL, Output Low Voltage1 0.4 V max VDD = 5 V, I
Floating-State Leakage Current ±1 µA max
Floating-State Output Capacitance 10 pF typ
Data Output Coding Offset binary

POWER REQUIREMENTS

Power-Supply Voltage

VDD − GND 2.5/5.25 V min/max AD7789, AD7788B grade

2.7/5.25 V min/max AD7788 A grade
Power-Supply Currents

IDD Current 75 µA max 65 µA typ, VDD = 3.6 V

80 µA max 73 µA typ, VDD = 5.25 V

IDD (Power-Down Mode) 1 µA max

1

Specification is not production tested but is supported by characterization data at initial product release.

2

Digital inputs equal to VDD or GND.

1

2

1

DD

− 0.6 V min VDD = 3 V, I

DD

= 100 µA

SOURCE

= 100 µA

SINK

= 200 µA

SOURCE

= 1.6 mA

SINK

Rev. A | Page 5 of 20

AD7788/AD7789

TIMING CHARACTERISTICS

VDD = 2.5 V to 5.25 V (AD7788B and AD7789); VDD = 2.7 V to 5.25 V (AD7788A); GND = 0 V; REFIN(+) = 2.5 V; REFIN(−) = GND;
Input logic 0 = 0 V; Input logic 1 = V

Table 4.

Parameter

t

3

t

4

1, 2

Limit at T

100 ns min SCLK high pulse width
100 ns min SCLK low pulse width

Read Operation

t

1

0 ns min

60 ns max VDD = 4.75 V to 5.25 V
80 ns max VDD = 2.7 V to 3.6 V

3

t

2

0 ns min SCLK active edge to data valid delay
60 ns max VDD = 4.75 V to 5.25 V
80 ns max VDD = 2.7 V to 3.6 V

5, 6

t

5

10 ns min
80 ns max

t

6

t

7

0 ns min

10 ns min

Write Operation

t

8

t

9

t

10

t

11

0 ns min

30 ns min Data valid to SCLK edge setup time

25 ns min Data valid to SCLK edge hold time

0 ns min

, unless otherwise noted.

DD

, T

MIN

(B Version) Unit Conditions/Comments

MAX

CS falling edge to DOUT/RDY active time

4

Bus relinquish time after

SCLK inactive edge to
SCLK inactive edge to DOUT/

CS inactive edge

CS inactive edge

RDY high

CS falling edge to SCLK active edge setup time

CS rising edge to SCLK edge hold time

4

1

Sample tested during initial release to ensure compliance. All input signals are specified with tR = tF = 5 ns (10% to 90% of VDD) and timed from a voltage level of 1.6 V.

2

See Figure 3 and Figure 4.

3

These numbers are measured with the load circuit of, and defined as, the time required for the output to cross the VOL or VOH limits.

4

SCLK active edge is falling edge of SCLK.

5

These numbers are derived from the measured time taken by the data output to change 0.5 V when loaded with the circuit of Figure 2. The measured number is then

extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the times quoted in the timing characteristics are the true bus
relinquish times of the part and, as such, are independent of external bus loading capacitances.

6

RDY

returns high after a read of the ADC. In single-conversion mode and continuous-conversion mode, the same data can be read again, if required, while
although care should be taken to ensure that subsequent reads do not occur close to the next output update. In continuous-read mode, the digital word can be read
only once.

RDY

is high,

Rev. A | Page 6 of 20