Analog Devices AD7787 Datasheet

Low Power, 2-Channel

FEATURES

Power

Supply: 2.5 V to 5.25 V operation Normal mode: 75 µA max Power-down mode: 1 µA max

RMS noise: 1.1 µV at 9.5 Hz update rate

19.5-bit p-p resolution (22 bits effective resolution) Integral nonlinearity: 3.5 ppm typical Simultaneous 50 Hz and 60 Hz rejection Internal clock oscillator Rail-to-rail input buffer VDD monitor channel Temperature range: −40°C to +105°C 10-lead MSOP

INTERFACE

3-wire serial SPI®, QSPI™, MICROWIRE™, and DSP compatible Schmitt trigger on SCLK

24-Bit Sigma-Delta ADC

AD7787

APPLICATIONS

Smart transmitters Battery applications Portable instrumentation Sensor measurement Temperature measurement Pressure measurement Weigh scales 4 to 20 mA loops

GENERAL DESCRIPTION

The AD7787 is a low power, complete analog front end for low frequency measurement applications. It contains a low noise 24-bit Σ-Δ ADC with one differential input and one singleended input that can be buffered or unbuffered.

The device operates from an internal clock. Therefore, the user does not have to supply a clock source to the device. The output data rate from the part is software programmable and can be varied from 9.5 Hz to 120 Hz, with the rms noise equal to

1.1 µV at the lower update rate. The internal clock frequency can be divided by a factor of 2, 4, or 8, which leads to a reduction in the current consumption. The update rate, cutoff frequency, and settling time scales with the clock frequency.

FUNCTIONAL BLOCK DIAGRAM

GND

BUF

GND REFIN

AIN1(+)

AIN1(–)

AIN2

MUX

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

ADC

Figure 1.

The part operates with a power supply from 2.5 V to 5.25 V. When operating from a 3 V supply, the power dissipation for the part is 225 µW maximum. It is housed in a 10-lead MSOP.

AD7787

SERIAL

INTERFACE

Σ-∆

AND

LOGIC

CONTROL

CLOCK

DOUT/RDY DIN SCLK CS

04477-0-001

AD7787

TABLE O F CO N TENTS

Specifications..................................................................................... 3

Timing Characteristics..................................................................... 5

Absolute Maximum Ratings............................................................ 7

ESD Caution.................................................................................. 7

Pin Configuration and Function Descriptions............................. 8

Typical Performance Characteristics ............................................. 9

On-Chip Registers.......................................................................... 10

Communications Register (RS1, RS0 = 0, 0)........................... 10

Status Register (RS1, RS0 = 0, 0; Power-On/Reset

= 0×8C)........................................................................................ 11

Mode Register (RS1, RS0 = 0, 1; Power-On/Reset

= 0×02)......................................................................................... 12

Filter Register (RS1, RS0 = 1, 0; Power-On/Reset

= 0×04)......................................................................................... 13

Data Register (RS1, RS0 = 1, 1; Power-On/Reset

= 0×000000) ................................................................................13

Overview ..................................................................................... 14

Noise Performance ..................................................................... 14

Reduced Current Modes ........................................................... 14

Digital Interface.......................................................................... 15

Circuit Description......................................................................... 18

Analog Input Channel ............................................................... 18

Bipolar/Unipolar Configuration .............................................. 18

Data Output Coding .................................................................. 18

Reference Input........................................................................... 18

Monitor................................................................................ 19

Grounding and Layout .............................................................. 19

Applications ................................................................................ 19

Outline Dimensions....................................................................... 20

Ordering Guide .......................................................................... 20

ADC Circuit Information.............................................................. 14

REVISION HISTORY

4/04—Revision 0: Initial Version

Rev. 0 | Page 2 of 20

AD7787

SPECIFICATIONS

Temperature range is −40°C to +105°C. VDD = 2.5 V to 5.25 V; REFIN = 2.5 V; GND = 0 V; CDIV1 = CDIV0 = 0; all specifications T

, unless otherwise noted.

MAX

Table 1.

Parameter AD7787B Unit Test Conditions/Comments

ADC CHANNEL SPECIFICATION

Output Update Rate 9.5 Hz min nom 120 Hz max nom ADC CHANNEL

No Missing Codes1 24 Bits min Update rate ≤ 20 Hz.

Resolution 19.5 Bits p-p 9.5 Hz update rate.

Output Noise 1.1 µV rms typ

Integral Nonlinearity ±15 ppm of FSR max 3.5 ppm typ.

Offset Error ±3 µV typ

Offset Error Drift vs. Temperature ±10 nV/°C typ

Full-Scale Error2 ±10 µV typ

Gain Drift vs. Temperature ±0.5 ppm/°C typ

Power Supply Rejection 90 dB min 100 dB typ, AIN = 1 V. ANALOG INPUTS

Bipolar Input Voltage Range ±REFIN V nom

Because AIN2 is single-ended, it can have a negative

voltage of 100 mV minimum (see Page 18). Unipolar Voltage Range 0 to REFIN V nom Absolute AIN Voltage Limits1 GND + 100 mV V min Buffered mode. V

– 100 mV V max

Analog Input Current Buffered mode.

Average Input Current1 ±1 nA max

Average Input Current Drift ±5 pA/°C typ Absolute AIN Voltage Limits V

1, 3

GND – 100 mV V min Unbuffered mode.

+ 30 mV V max

Analog Input Current Unbuffered mode. Current varies with input voltage.

Average Input Current ±400 nA/V typ

Average Input Current Drift ±50 pA/V/°C typ Normal Mode Rejection1

@ 50 Hz, 60 Hz 65 dB min 73 dB typ, 50 ± 1 Hz, 60 ± 1 Hz, FS[2:0] = 1004.

@ 50 Hz 80 dB min 90 dB typ, 50 ± 1 Hz, FS[2:0] = 1014.

@ 60 Hz 80 dB min 90 dB typ, 60 ± 1 Hz, FS[2:0] = 0114. Common-Mode Rejection (AIN1) AIN = 1 V.

@ DC 90 dB min 100 dB typ.

@ 50 Hz, 60 Hz1 100 dB min 50 ± 1 Hz (FS[2:0] = 1014), 60 ± 1 Hz (FS[2:0] = 0114).

REFERENCE INPUT

REFIN Voltage 2.5 V nom Reference Voltage Range1 0.1 V min V

V max

Average Reference Input Current 0.5 µA/V typ Average Reference Input Current Drift ±0.03 nA/V/°C typ Normal Mode Rejection1

@ 50 Hz, 60 Hz 65 dB min 73 dB typ, 50 ± 1 Hz, 60 ± 1 Hz, FS[2:0] = 1004.

@ 50 Hz 80 dB min 90 dB typ, 50 ± 1 Hz, FS[2:0] = 1014.

@ 60 Hz 80 dB min 90 dB typ, 60 ± 1 Hz, FS[2:0] = 0114.

MIN

Rev. 0 | Page 3 of 20

AD7787

Parameter AD7787B Unit Test Conditions/Comments

LOGIC INPUTS

All Inputs Except SCLK1

, Input Low Voltage 0.8 V max VDD = 5 V.

INL

0.4 V max VDD = 3 V. V

, Input High Voltage 2.0 V min VDD = 3 V or 5 V.

INH

SCLK Only (Schmitt-Triggered Input)1 VT(+) 1.4/2 V min/V max VDD = 5 V. VT(−) 0.8/1.4 V min/V max VDD = 5 V. VT(+) − VT(−) 0.3/0.85 V min/V max VDD = 5 V. VT(+) 0.9/2 V min/V max VDD = 3 V. VT(−) 0.4/1.1 V min/V max VDD = 3 V. VT(+) − VT(−) 0.3/0.85 V min/V max VDD = 3 V.

Input Currents ±1 µA max VIN = VDD or GND. Input Capacitance 10 pF typ All Digital Inputs.

LOGIC OUTPUTS

VOH, Output High Voltage1 V VOL, Output Low Voltage1 0.4 V max VDD = 3 V, I VOH, Output High Voltage1 4 V min VDD = 5 V, I VOL, Output Low Voltage1 0.4 V max VDD = 5 V, I Floating-State Leakage Current ±1 µA max Floating-State Output Capacitance 10 pF typ Data Output Coding Offset Binary

POWER REQUIREMENTS5

Power Supply Voltage

VDD − GND 2.5/5.25 V min/max

Power Supply Currents

IDD Current6 75 µA max 65 µA typ, VDD = 3.6 V, unbuffered mode.

145 µA max 130 µA typ, VDD = 3.6 V, buffered mode. 80 µA max 73 µA typ, VDD = 5.25 V, unbuffered mode. 160 µA max 145 µA typ, VDD = 5.25 V, buffered mode.

IDD (Power-Down Mode) 1 µA max

Specification is not production tested but is supported by characterization data at initial product release.

Full-scale error applies to both positive and negative full scale and applies at the factory calibration conditions (VDD = 4 V).

The AD7787 can tolerate absolute analog input voltages down to GND − 200 mV but the leakage current will increase.

FS[2:0] are the three bits used in the filter register to select the output word rate.

Digital inputs equal to VDD or GND.

The current consumption can be further reduced by using the ADC in one of the low power modes (see Table 14).

− 0.6 V min VDD = 3 V, I

= 100 µA.

SOURCE

= 100 µA.

SINK

= 200 µA.

SOURCE

= 1.6 mA.

SINK

Rev. 0 | Page 4 of 20

AD7787

TIMING CHARACTERISTICS

Sample tested during initial release to ensure compliance. All input signals are specified with tR = tF = 5 ns (10% to 90% of VDD) and timed from a voltage level of 1.6 V (see Figure 3 and Figure 4).

= 2.5 V to 5.25 V; GND = 0 V, REFIN = 2.5 V, CDIV1 = CDIV0 = 0, Input Logic 0 = 0 V, Input Logic 1 = VDD, unless otherwise noted.

Table 2.

Parameter Limit at T

t3 100 ns min SCLK High Pulse Width t4 100 ns min SCLK Low Pulse Width Read Operation t1 0 ns min

60 ns max VDD = 4.75 V to 5.25 V 80 ns max VDD = 2.5 V to 3.6 V

0 ns min SCLK Active Edge to Data Valid Delay2

60 ns max VDD = 4.75 V to 5.25 V 80 ns max VDD = 2.5 V to 3.6 V

3, 4

10 ns min

80 ns max t6 100 ns max

t7 10 ns min Write Operation

t8 0 ns min t9 30 ns min Data Valid to SCLK Edge Setup Time t10 25 ns min Data Valid to SCLK Edge Hold Time t11 0 ns min

MIN

, T

(B Version) Unit Conditions/Comments

MAX

Falling Edge to DOUT/RDY Active Time

Bus Relinquish Time after CS

SCLK Inactive Edge to CS SCLK Inactive Edge to DOUT/RDY

Falling Edge to SCLK Active Edge Setup Time2

Rising Edge to SCLK Edge Hold Time

Inactive Edge

High

These numbers are measured with the load circuit of Figure 2 and defined as the time required for the output to cross the VOL or VOH limits.

The SCLK active edge is the falling edge of SCLK.

These numbers are derived from the measured time taken by the data output to change 0.5 V when loaded with the circuit of Figure 2. The measured number is then

extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the times quoted in the timing characteristics are the true bus relinquish times of the part and, as such, are independent of external bus loading capacitances.

RDY

returns high after a read of the ADC. In single conversion mode and continuous conversion mode, the same data can be read again, if required, while although care should be taken to ensure that subsequent reads do not occur close to the next output update. In continuous read mode, the digital word can be read only once.

RDY

is high,

Rev. 0 | Page 5 of 20

AD7787

(1.6mA WITH VDD = 5V,

SINK

100µA WITH V

= 3V)

TO OUTPUT

50pF

SOURCE

100µA WITH V

1.6V

(200µA WITH VDD = 5V,

= 3V)

04477-0-002

Figure 2. Load Circuit for Timing Characterization

CS (I)

04477-0-003

DOUT/RDY (O)

SCLK (I)

MSB LSB

I = INPUT, O = OUTPUT

Figure 3. Read Cycle Timing Diagram

CS (I)

04477-0-004

SCLK (I)

DIN (I)

I = INPUT, O = OUTPUT

MSB LSB

Figure 4. Write Cycle Timing Diagram

Rev. 0 | Page 6 of 20

+ 14 hidden pages

Analog Devices AD7787 Datasheet

Specifications and Main Features

Frequently Asked Questions

User Manual

FEATURES

INTERFACE

APPLICATIONS

GENERAL DESCRIPTION

FUNCTIONAL BLOCK DIAGRAM

TABLE O F CO N TENTS

SPECIFICATIONS

TIMING CHARACTERISTICS