Analog Devices AD7709BRU, AD7709BR Datasheet

PRELIMINARY TECHNICAL DATA

16-Bit Sigma Delta ADC with Current Sources,

a

Switchable Reference Inputs and I/O Port

Preliminary Technical Data

FEATURES

16-BIT SINGLE CHANNEL SIGMA DELTA-ADC
Factory Calibrated (field calibration not required)
Output settles in one conversion cycle (single conver
sion mode)
Programmable Gain Front End
16-bit No Missing Codes
13-bit Pk-Pk Resolution @ 20Hz, 20mV Range
16-bit Pk-PK Resolution @ 20Hz, 2.56V Range

INTERFACE

Three-Wire Serial

TM

, QSPITM, MICROWIRETM and DSP Compatible

SPI
Schmitt Trigger on SCLK

POWER

Specified for Single 3V and 5V operation
Normal : 2mA @ 3V
Powerdown : 20uA (32kHz Crystal Running)

On-Chip Functions

Rail-to-Rail Input Buffer and PGA
Switchable Reference Inputs
3 Configurable Current Sources
Low Side Power Swtches
Digital I/O Port

AD7709

GENERAL DESCRIPTION

The AD7709 is a complete analog front-end for low
frequency measurement applications. The AD7709
contains a 16-bit sigma delta ADC with PGA and can be
configured as 2 fully-differential input channels or 4
pseudo-differential input channels. Inputs signal ranges
from 20mV to 2.56V can be directly converted using the
AD7709. These signals can be converted directly from a
transducer without the need for signal conditioning. Other
on-chip features include three software configurable
current sources, switchable reference inputs, low side
power switches and a 4-bit digital I/O port.

The device operates from a 32kHz crystal with an on­board PLL generating the required internal operating
frequency. The output data rate from the part is software
programmable. The pk-pk resolution from the part varies
with the programmed gain and output data rate.

The part operates from a single +3V or +5V supply.
When operating from +3V supplies, the power dissipation
for the part is XmW. The AD7709 are housed in a 24­pin SOIC and TSSOP packages.

APPLICATIONS

Industrial Process Control
Instrumentation
Pressure Transducers
Portable Instrumentation

IOUT 1

IOUT 2

AIN1
AIN2

AIN3 / P3
AIN4 / P4

AINCOM

VDD

MUX

FUNCTIONAL BLOCK DIAGRAM

REFIN2(+)

I2 I3

I1

BUF

PGA

REFIN1(+)

16-BIT

Σ−∆

REFIN2(-)

ADC

AD7709

GND

PWRGND

REFIN1(-)

VDD

XTAL1 XTAL2

INTERFACE

CONTROL

I/O PORT

OSC

&

PLL

SERIAL

&

LOGIC

.

DOUT
DIN

SCLK
CS

RDY

RESET

SW2/P2SW1/P1

REV. PrA January 2001

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.

® SPIand QSPI are a Registered Trademark of Motorola Inc.

® MICROWIRE is a Registered Trademark of National Semiconductor Corp.

One T ec hnology Wa y , P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] World Wide Web Site: http://www.analog.com
Fax: [phone]

 

 Analog Devices, Inc., 2001

 

PRELIMINARY TECHNICAL DATA

AD7709-SPECIFICATIONS

1

PARAMETER B Grade Units Test Conditions

Output Update Rate 5.4 Hz min.

105 Hz max. 0.021Hz (0.732msec.) increments

No Missing Codes 16 bits min.
Resolution 13 bits pk-pk +20mV range, 20Hz Update Rate

16 bits pk-pk +2.56V range, 20Hz Update Rate

Output Noise and Update Rates See Tables Below in ADC Description
Integral Nonlinearity 15 ppm of FSR max.
Offset Error TBD
Offset Error Drift Vs Temp 10 nV/°C typ.
Offset Error Drift Vs Time TBD nV/1000 Hours typ.
Gain Error TBD
Gain Error Drift Vs Temp 1 ppm/°Ctyp.
Gain Error Drift Vs Time TBD ppm/1000 Hours typ.
Power Supply Rejection(PSR) 90 dB min. Input Range = ±20mV

90 dB min. Input Range = ±2.56V
Common Mode Rejection(CMR)
On AIN 90 dB min. At DC, Range = ±20mV
On AIN 90 dB min. At DC, Range = ±2.56V
On REFIN 90 dB min. At DC, Range = ±20mV
On REFIN 90 dB min. At DC, Range = ±2.56V
Analog Input Current
DC Bias Current 1 nA max.
DC Bias Current Drift TBD nA typ.
DC Offset Current TBD nA typ.
DC Offset Current Drift TBD nA typ.

(VDD = +3V or +5.0V , REFIN(+) = +2.5V; REFIN(-) = 0V;
XTAL1/XTAL2 = 32 kHz Crystal;
All specifications T

MIN

to T

unless otherwise noted.)

MAX

REFERENCE INPUTS (REFIN1& REFIN2)
Normal Mode
50Hz/60Hz Rejection 60 dB min.
Reference DC Input Current T BD µA typ.
REFIN(+) to REFIN(-) Voltage +2.5V nom. REFIN referes to both REFIN1 and REFIN2
REFIN(+) to REFIN(-) Range +1 V min.

V
REFIN Common Mode Range GND-30mV V min.

REFIN Common Mode
50/60Hz Rejection T B D dB min.

ANALOG INPUTS

Normal Mode 50Hz/60Hz Rejection 60 dB min. 50/60Hz ±1Hz , 20Hz Update Rate
Common Mode 50/60Hz Rejection 90 dB min. 50/60Hz ±1Hz, Range = ±20mV

Differential Input Voltage Ranges

Pseudo-Differential Input Voltage Ranges
Full-scale Range Matching 5 uV typ.

Absolute Ain Voltage Limits

Buffered Inputs GND+50mV V min.
Unbuffered Inputs GND-30mV Vmin

DD

V

+30mV V max.

DD

90 dB min. 50/60Hz ±1Hz, Range = ±2.5V
±REFIN/GAIN V nom. REFIN refers to both REFIN1 and

0V to REFIN/GAINV nom.

V

-50mV V max

DD

V

+30mV Vmax

DD

V max.

REFIN2.
REFIN=REFIN(+ )-REFIN(-)
GAIN=1to 128.

–2–

REV. PrA January 2001

PRELIMINARY TECHNICAL DATA

PARAMETER B Grade Units Test Conditions

LOGIC INPUTS

All Inputs Except SCLK and XTAL1

V

, Input Low Voltage 0.8 V max. V

INL

V

, Input Low Voltage 0.4 V max. V

INL

V

, Input High Voltage 2.0 V min. V

INH

SCLK Only (Schmitt Triggered Input)

V

T(+)

V

T(-)

V

T(+)- VT(-)

V

T(+)

V

T(-)

V

T(+)-VT(-)

1.4/3 V min/V max VDD = 5V

0.8/1.4 V min/V max VDD = 5V

0.4/0.85 V min/V max VDD = 5V

0.95/2.5 V min/V max VDD = 3V

0.4/1.1 V min/V max VDD = 3V

0.4/0.85 V min/V max VDD = 3V

XTAL1 Only

V

, Input Low Voltage 0.8 V max. V

INL

V

, Input High Voltage 3.5 V min. V

INH

V

, Input Low Voltage 0.4 V max. V

INL

V

, Input High Voltage 2.5 V min. V

INH

Input Currents ±10 µA max. V
Input Capacitance 10 pF typ. All Digital Inputs

LOGIC OUTPUTS (Excluding XTAL2)

V

, Output High Voltage VDD- 0.6 V min. VDD = 3V, I

OH

V

, Output Low Voltage 0.4 V max. VDD = 3V, I

OL

V

, Output High Voltage 4 V min. VDD = 5V, I

OH

V

, Output Low Voltage 0.4 V max. VDD = 5V, I

OL

Floating State Leakage Current ±10 uA max.
Floating State Output Capacitance ±10 pF typ.
Data Output Coding Binary Unipolar Mode

Offset Binary Bipolar Mode

EXCITATION CURRENT SOURCES

I1 and I2 Output Current 200 µA nom.
I3 Output Current 25 µA nom.
Initial Tolerance at 25°C ±10 % typ.
Drift 20 ppm/°C typ.
Initial Current Matching at 25°C ±1 % Matching between I1 and I2
Drift Matching 1 ppm/°C typ.
Line Regulation (V

) TBD nA/V max. VDD = 5V±10%

DD

Load Regulation TBD nA/V max.
Output Compliance AVDD-0.5 V max.

Low-Side Power Switches (SW1 and SW2)

Ron 5 Ω typ VDD = 5V

7 Ω typ V

Allowable Current 20 mA max Per Switch

SYSTEM CALIBRATION

Full-Scale Calibration Limit 1.05 X FS V max.
Zero-Scale Calibration Limit -1.05 X FS V min.
Input Span 0.8 X FS V min.

2.1 X FS V max.

START UP TIME

From Power-On 500 msec typ.
From Idle Mode 1 msec. typ.
From Power-Down Mode 1 msec. typ.

500 msec. typ. Osc. powered down

POWER REQUIREMENTS

Power Supply Voltages

V

- GND 2.7/3.6 V min/max V

DD

4.5/5.5 V min/max V

= 5V

DD

= 3V

DD

= 3V or 5V

DD

= 5V

DD

= 5V

DD

= 3V

DD

= 3V

DD

= 0V or V

IN

= 3V

DD

= 3V nom.

DD

= 5V nom.

DD

DD

SOURCE

= 100µA

SINK
SOURCE

= 1.6mA

SINK

= 100µA
= 200µA

AD7709

REV. PrA January 2001

–3–

PRELIMINARY TECHNICAL DATA

AD7709

PARAMETER B Grade Units Test Conditions
Power Supply Currents

VDD Current (Normal Mode) TBD mA VDD=3V
V

Current (Normal Mode) TBD mA VDD=5V

DD

Current (Idle Mode) TBD mA VDD=3V

V

DD

V

Current (Idle Mode) TBD mA VDD=5V

DD

Current (Power-Down Mode) 20 µA max. VDD=3V, 32.768kHz Osc. Running

V

DD

VDD Current (Power-Down Mode) 30 µA max. VDD=5V, 32.768kHz Osc. Running

NOTES

1

Temperature Range -40

2
3
4

°C

to +85

°C

–4–

REV. PrA January 2001

PRELIMINARY TECHNICAL DATA

ABSOLUTE MAXIMUM RATINGS

(TA = +25°C unless otherwise noted)

V

to GND.............................................-0.3V to +7V

DD

Analog Input Voltage to GND...........-0.3V to V

Reference Input Voltage to GND.......-0.3V to V

AIN/REFIN Current (Indefinite)...........................30mA

Digital Input Voltage to GND...........-0.3V to V

Digital Output Voltage to GND........-0.3V to V

PWRGND

to GND...............................-0.3V to +0.3V

Operating Temperature Range..................-40°C to 85°C

Storage Temperature Range....................-65°C to 150°C

Junction Temperature........................................+150°C

PACKAGE Power Dissipation........................TBD mW

θ

Thermal Impedance..................................90°C/W

JA

Lead Temperature, Soldering

Vapor Phase (60sec)..................................+215°C

Infrared (15 sec).......................................+220°C

1

Stresses above those listed under "Absolute Maximum Ratings" may cause permanent

damage to the device. This is a stress rating only and functional operation of the device
at these or any other conditions above those listed in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.

1

+0.3V

DD

+0.3V

DD

+0.3V

DD

+0.3V

DD

OUTLINE DIMENSIONS

24-lead plastic SOIC (R-24)

0.6141 (15.60)

0.5985 (15.20)

24

1

0.0118 (0.30)

0.0040 (0.10)

PIN 1

0.0500

(1.27)

BSC

0.0192 (0.49)

0.0138 (0.35)

13

12

0.1043 (2.65)

0.0926 (2.35)

SEATING

PLANE

24-lead plastic TSSOP (RU-24)

7.40)

7.60)

0.2914 (

0.2992 (

0.0125 (0.32)

0.0091 (0.23)

AD7709

10.00)

10.65)

0.3937 (

0.4193 (

0.0291 (0.74)

0.0098 (0.25)

0.0500 (1.27)

8¡

0¡

0.0157 (0.40)

x 45¡

24-lead plastic
TSSOP (RU-24)

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD7709 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.

ORDERING GUIDE

Model Temperature Package Package Drawing

Range Description Option

AD7709BR -40°C to +85°C SOIC R-24
AD7709BRU -40°C to +85°C TSSOP RU-24

–5–REV. PrA January 2001

AD7709

PRELIMINARY TECHNICAL DATA

TIMING CHARACTERISTICS

1, 2

(VDD = +3V ±10% or VDD = +5V ±10%;GND = 0 V:X

= 32.768kHz; Input Logic 0 = 0 V, Logic 1 = V

TAL

DD

unless otherwise noted)

Limit at T

MIN

, T

MAX

Parameter (B Version) Units Conditions/Comments

t

1

t

2

32.768 kHz typ Crystal Oscillator Frequency.
50 ns min RESET Pulse Width

Read Operation

t

3

t

4

4

t

5

0 ns min RDY to CS Setup Time
0 ns min CS Falling Edge to SCLK Active Edge Setup

0 ns min SCLK Active Edge to Data Valid Delay

Time

3

3

60 ns max VDD = +4.5 V to +5.5 V

4, 5

t

5A

80 ns max V
0 ns min CS Falling Edge to Data Valid Delay

= +2.7 V to +3.6 V

DD

3

60 ns max VDD = +4.5 V to +5.5 V
80 ns max V

t

6

t

7

t

8

6

t

9

100 ns min SCLK High Pulse Width
100 ns min SCLK Low Pulse Width
0 ns min CS Rising Edge to SCLK Inactive Edge Hold

10 ns min Bus Relinquish Time after SCLK Inactive Edge
80 ns max

t

10

100 ns max SCLK Active Edge to RDY High

= +2.7 V to +3.6 V

DD

3

Time

3

3, 7

Write Operation

t

11

t

12

t

13

t

14

t

15

t

16

NOTES

1

Sample tested during initial release to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of VDD) and timed from a voltage level of 1.6 V.

2

See Figures 1 and 2.

3

SCLK active edge is falling edge of SCLK.

4

These numbers are measured with the load circuit of Figure 3 and defined as the time required for the output to cross the VOL or VOH limits.

5

This specification only comes into play if CS goes low while SCLK is low. It is required primarily for interfacing to DSP machines.

6

These numbers are derived from the measured time taken by the data output to change 0.5 V when loaded with the circuit of Figure 3. The measured number is then extrapolated back to remove effects of charging or
discharging the 50 pF capacitor. This means that the times quoted in the timing characteristics are the true bus relinquish times of the part and as such are independent of external bus loading capacitances.

7

RDY returns high after the first read from the device after an output update. The same data can be read again, if required, while RDY is high, although care should be taken that subsequent reads do not occur close to
the next output update.

0 ns min CS Falling Edge to SCLK Active Edge Setup

Time

3

30 ns min Data Valid to SCLK Edge Setup Time
25 ns min Data Valid to SCLK Edge Hold Time
100 ns min SCLK High Pulse Width
100 ns min SCLK Low Pulse Width
0 ns min CS Rising Edge to SCLK Edge Hold Time

–6–

REV. PrA January 2001