ANALOG DEVICES AD7708, AD7718 Service Manual

查询AD7708供应商

8-/10-Channel, Low Voltage,

a

FEATURES
8-/10-Channel, High Resolution ⌺-⌬ ADCs
AD7708 Has 16-Bit Resolution
AD7718 Has 24-Bit Resolution
Factory-Calibrated
Single Conversion Cycle Setting
Programmable Gain Front End
Simultaneous 50 Hz and 60 Hz Rejection

VREF Select

Measurement Capability

Operation Can Be Optimized for

Analog Performance (CHOP = 0) or
Channel Throughput (CHOP = 1)

INTERFACE
3-Wire Serial

TM

SPI
Schmitt Trigger on SCLK

POWER
Specified for Single 3 V and 5 V Operation
Normal: 1.28 mA Typ @ 3 V
Power-Down: 30 ␮A (32 kHz Crystal Running)
On-Chip Functions

Rail-to-Rail Input Buffer and PGA
2-Bit Digital I/O Port

APPLICATIONS
Industrial Process Control
Instrumentation
Pressure Transducers
Portable Instrumentation
Smart Transmitters

™ Allows Absolute and Ratiometric

, QSPITM, MICROWIRETM, and DSP-Compatible

Low Power, ⌺-⌬ ADCs

AD7708/AD7718

GENERAL DESCRIPTION

The AD7708/AD7718 are complete analog front-ends for low
frequency measurement applications. The AD7718 contains a
24-bit Σ-∆ ADC with PGA and can be configured as 4/5 fully­differential input channels or 8/10 pseudo-differential input
channels. Two pins on the device are configurable as analog
inputs or reference inputs. The AD7708 is a 16-bit version of
the AD7718. Input signal ranges from 20 mV to 2.56 V can be
directly converted using these ADCs. Signals can be converted
directly from a transducer without the need for signal conditioning.

The device operates from a 32 kHz crystal with an on-board PLL
generating the required internal operating frequency. The output
data rate from the part is software programmable. The peak-to­peak resolution from the part varies with the programmed gain
and output data rate.

The part operates from a single 3 V or 5 V supply. When operating
from 3 V supplies, the power dissipation for the part is 3.84 mW typ.
Both parts are pin-for-pin compatible allowing an upgradable
path from 16 to 24 bits without the need for hardware modifica­tions. The AD7708/AD7718 are housed in 28-lead SOIC and
TSSOP packages.

FUNCTIONAL BLOCK DIAGRAM

DVD D XTAL1 XTAL2

DGND

AIN1
AIN2
AIN3
AIN4
AIN5
AIN6
AIN7
AIN8

AINCOM

SPI and QSPI are trademarks of Motorola Inc.
MICROWIRE is a trademark of National Semiconductor Corp.
VREF Select is a trademark of Analog Devices, Inc.

MUX

AV DD

NEG BUF

REFIN2(+)/ AIN9 REFIN1(+) REFIN2(–)/ AIN10 REFIN1(–)

POS BUF

REFIN(+) REFIN(–)

PGA

AD7708/ AD7718

AGND

REV. 0

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.

OSC
AND

PLL

DOUT
DIN
SCLK

CS
RDY
RESET

I/O PORT

SERIAL

INTERFACE

AND

CONTROL

LOGIC

P2 P1

⌺-⌬ ADC*

*AD7708 16-BIT ADC
*AD7718 24-BIT ADC

AV DD

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] © Analog Devices, Inc., 2001

AD7708/AD7718

TABLE OF CONTENTS

FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

FUNCTIONAL BLOCK DIAGRAM . . . . . . . . . . . . . . . . . 1

GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . 1

AD7718 SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . 3

AD7708 SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . 6

TIMING CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . 9

ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . 10

ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

PIN FUNCTION DESCRIPTIONS . . . . . . . . . . . . . . . . . 12

PIN CONFIGURATION . . . . . . . . . . . . . . . . . . . . . . . . . . 13

ADC CIRCUIT INFORMATION . . . . . . . . . . . . . . . . . . . 15

Signal Chain Overview (CHOP Enabled, CHOP = 0) . . . 15

ADC NOISE PERFORMANCE CHOP ENABLED

(CHOP = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Signal Chain Overview (CHOP Disabled CHOP = 1) . . . 19

ADC NOISE PERFORMANCE CHOP DISABLED

(CHOP = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

ON-CHIP REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Communications Register . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Mode Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Operating Characteristics when Addressing the

Mode and Control Registers . . . . . . . . . . . . . . . . . . . . . . . 28

ADC Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Filter Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

I/O Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

ADC Data Result Register . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Unipolar Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Bipolar Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

ADC Offset Calibration Coefficient Registers . . . . . . . . . . . 31

ADC Gain Calibration Coefficient Register . . . . . . . . . . . . . 31

ID Register (ID) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

User Nonprogrammable Test Registers . . . . . . . . . . . . . . . . 31

Configuring the AD7708/AD7718 . . . . . . . . . . . . . . . . . . . . 32

DIGITAL INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

MICROCOMPUTER/MICROPROCESSOR

INTERFACING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

AD7708/AD7718 to 68HC11 Interface . . . . . . . . . . . . . . . . 34

AD7708/AD7718-to-8051 Interface . . . . . . . . . . . . . . . . . . 35

AD7708/AD7718-to-ADSP-2103/ADSP-2105 Interface . . . 36

BASIC CONFIGURATION . . . . . . . . . . . . . . . . . . . . . . . . 36

Analog Input Channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Single-Ended Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Chop Mode of Operation (CHOP = 0) . . . . . . . . . . . . . . . . 37

Nonchop Mode of Operation (CHOP = 1) . . . . . . . . . . . . . 38

Programmable Gain Amplifier . . . . . . . . . . . . . . . . . . . . . . . 38

Bipolar/Unipolar Configuration . . . . . . . . . . . . . . . . . . . . . . 38

Data Output Coding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Oscillator Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Reference Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

RESET Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Power-Down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Grounding and Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

APPLICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Data Acquisition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Programmable Logic Controllers . . . . . . . . . . . . . . . . . . . . . 41

Converting Single-Ended Inputs. . . . . . . . . . . . . . . . . . . . . 42

Combined Ratiometric and Absolute Value

Measurement System . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Optimizing Throughput while Maximizing 50 Hz

and 60 Hz Rejection in a Multiplexed Data

Acquisition System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . 44

–2–

REV. 0

AD7708/AD7718

AD7718 SPECIFICATIONS

REFIN(+) = 2.5 V; REFIN(–) = AGND; AGND = DGND = 0 V; XTAL1/XTAL2 = 32.768 kHz Crystal Input Buffer Enabled. All specifications T
T

unless otherwise noted.)

MAX

Parameter B Grade Unit Test Conditions

AD7718 (CHOP DISABLED)

Output Update Rate 16.06 Hz min CHOP = 1

No Missing Codes
Resolution 13 Bits p-p ±20 mV Range, SF = 69

Output Noise and Update Rates See Tables in

Integral Nonlinearity ±10 ppm of FSR max 2 ppm Typical
Offset Error

Offset Error Drift vs. Temp
Full-Scale Error
Gain Drift vs. Temp
Negative Full-Scale Error ±0.003 % FSR max

ANALOG INPUTS

Differential Input Full-Scale Voltage ±1.024 × REFIN/GAIN V nom REFIN Refers to Both REFIN1 and

Absolute AIN Voltage Limits AGND + 100 mV V min AIN1–AIN10 and AINCOM with

Absolute AINCOM Voltage Limits AGND – 30 mV V min NEGBUF = 0

Analog Input Current AIN1–AIN10 and AINCOM with NEGBUF = 1

DC Input Current
DC Bias Current Drift ±5pA/°C typ

AINCOM Input Current NEGBUF = 0

DC Input Current
DC Bias Current Drift ±2 pA/V/°C typ

Normal-Mode Rejection

@ 50 Hz 100 dB min 50 Hz ± 1 Hz, SF Word = 82
@ 60 Hz 100 dB min 60 Hz ± 1 Hz, SF Word = 68

Common-Mode Rejection

@ DC 90 dB min 100 dB typ, Analog Input = 1 V,

@ 50 Hz 100 dB typ 50 Hz ± 1 Hz, SF Word = 82
@ 60 Hz 100 dB typ 60 Hz ± 1 Hz, SF Word = 68

REFERENCE INPUTS (REFIN1 AND REFIN2)

REFIN(+) to REFIN(–) Voltage 2.5 V nom REFIN Refers to Both REFIN1 and REFIN2
REFIN(+) to REFIN(–) Range

REFIN Common-Mode Range AGND – 30 mV V min

Reference DC Input Current 0.5 µA/V typ
Reference DC Input Current Drift ± 0.1 nA/V/°C typ
Normal-Mode Rejection

@ 50 Hz 100 dB min 50 Hz ± 1 Hz, SF Word = 82
@ 60 Hz 100 dB min 60 Hz ± 1 Hz, SF Word = 68

Common-Mode Rejection Input Range = ±2.56 V

@ DC 100 dB typ Analog Input = 1 V. Input Range = ±2.56 V
@ 50 Hz 100 dB typ
@ 60 Hz 100 dB typ

2

3

4

3

4

2

2

2

2

2

(AVDD = 2.7 V to 3.6 V or 4.75 V to 5.25 V, DVDD = 2.7 V to 3.6 V or 4.75 V to 5.25 V,

to

MIN

1.365 kHz max
24 Bits min

18 Bits p-p ±2.56 V Range, SF = 69

ADC Description

Table VII µV typ Offset Error is in the order of the noise for the

±200 nV/°C typ
±10 µV typ
±0.5 ppm/°C typ

– 100 mV V max NEGBUF = 1

AV

DD

+ 30 mV V max

AV

DD

±1 nA max

±125 nA/V typ ±2.56 V Range

1V min
AV

DD

+ 30 mV V max

AV

DD

V max

programmed gain and update rate following a
calibration

REFIN2. REFIN = REFIN(+) –REFIN(–)
GAIN = 1 to 128

Input Range = ±2.56 V
110 dB typ on ±20 mV Range

1

REV. 0

–3–

1

AD7718–SPECIFICATIONS

2.5 V ; REFIN(–) = AGND; AGND = DGND = 0 V; XTAL1/XTAL2 = 32.768 kHz Crystal Input Buffer Enabled. All specifications T

Parameter B Grade Unit Test Conditions

AD7718 (CHOP ENABLED)

Output Update Rate 5.4 Hz min CHOP = 0

No Missing Codes
Resolution 13 Bits p-p ±20 mV Range, 20 Hz Update Rate

Output Noise and Update Rates See Tables in

Integral Nonlinearity ±10 ppm of FSR max 2 ppm Typical
Offset Error
Offset Error Drift vs. Temp
Full-Scale Error
Gain Drift vs. Temp

ANALOG INPUTS

Differential Input Full-Scale Voltage ±1.024 × REFIN/GAIN V nom REFIN Refers to Both REFIN1 and

Range Matching ±2 µV typ Analog Input = 18 mV
Absolute AIN Voltage Limits AGND + 100 mV V min AIN1–AIN10 and AINCOM with

Absolute AINCOM Voltage Limits AGND – 30 mV V min NEGBUF = 0

Analog Input Current AIN1–AIN10 and AINCOM with

DC Input Current
DC Input Current Drift ±5 pA/°C typ

AINCOM Input Current NEGBUF = 0

DC Input Current
DC Bias Current Drift ±2 pA/V/°C typ

Normal-Mode Rejection

@ 50 Hz 100 dB min 50 Hz ± 1 Hz, SF Word = 82
@ 60 Hz 100 dB min 60 Hz ± 1 Hz, SF Word = 68

Common-Mode Rejection

@ DC 90 dB min 100 dB typ, Analog Input = 1 V,

@ 50 Hz
@ 60 Hz

REFERENCE INPUTS (REFIN1 AND REFIN2)

REFIN(+) to REFIN(–) Voltage 2.5 V nom REFIN Refers to Both REFIN1 and

REFIN(+) to REFIN(–) Range

REFIN Common-Mode Range AGND – 30 mV V min

Reference DC Input Current
Reference DC Input Current Drift ± 0.01 nA/V/°C typ
Normal-Mode Rejection

@ 50 Hz 100 dB min 50 Hz ± 1 Hz, SF Word = 82
@ 60 Hz 100 dB min 60 Hz ± 1 Hz, SF Word = 68

Common-Mode Rejection

@ DC 110 dB typ Analog Input = 1 V
@ 50 Hz 110 dB typ 50 Hz ± 1 Hz, 20 Hz Update Rate
@ 60 Hz 110 dB typ 60 Hz ± 1 Hz, 20 Hz Update Rate

LOGIC INPUTS

All Inputs Except SCLK and XTAL1

V

, Input Low Voltage 0.8 V max DVDD = 5 V

INL

, Input Low Voltage 0.4 V max DVDD = 3 V

V

INL

V

, Input High Voltage 2.0 V min DVDD = 3 V or 5 V

INH

2

3

4

3

4

2

2

2

2

2

2

2

2

2

5

2

(AVDD = 2.7 V to 3.6 V or 4.75 V to 5.25 V, DVDD = 2.7 V to 3.6 V or 4.75 V to 5.25 V, REFIN(+) =

to T

MIN

105 Hz max
24 Bits min 20 Hz Update Rate

18 Bits p-p ±2.56 V Range, 20 Hz Update Rate

ADC Description

±3 µV typ
10 nV/°C typ

±10 µV/°C typ
±0.5 ppm/°C typ

REFIN2. REFIN = REFIN(+) REFIN(–)
GAIN = 1 to 128

– 100 mV V max NEGBUF = 1

AV

DD

+ 30 mV V max

AV

DD

NEGBUF = 1

±1 nA max

±125 nA/V typ ±2.56 V Range

Input Range = ±2.56 V

110 dB typ on ±20 mV Range
100 dB min 50 Hz ± 1 Hz, 20 Hz Update Rate
100 dB min 60 Hz ± 1 Hz, 20 Hz Update Rate

REFIN2
1V min
AV

DD

+ 30 mV V max

AV

DD

V max

±0.5 µA/V typ

Input Range = ±2.56 V

unless otherwise noted.)

MAX

–4–

REV. 0

AD7708/AD7718

Parameter B Grade Unit Test Conditions

LOGIC INPUTS (Continued)

SCLK Only (Schmitt-Triggered Input)

V

T(+)

V

T(–)

V

– V

T(+)

V
V
V

XTAL1 Only

V
V
V
V

T(–)

T(+)

T(–)

T(+)–VT(–)

INL

INH

INL

INH

2

, Input Low Voltage 0.8 V max DVDD = 5 V

, Input High Voltage 3.5 V min DVDD = 5 V

, Input Low Voltage 0.4 V max DVDD = 3 V

, Input High Voltage 2.5 V min DVDD = 3 V

Input Currents ±10 µA max Logic Input = DV

Input Capacitance 10 pF typ All Digital Inputs

LOGIC OUTPUTS (Excluding XTAL2)

VOH, Output High Voltage

, Output Low Voltage

V

OL

, Output High Voltage

V

OH

, Output Low Voltage

V

OL

2

2

2

2

Floating State Leakage Current ±10 µA max
Floating State Output Capacitance ±10 pF typ
Data Output Coding Binary Unipolar Mode

SYSTEM CALIBRATION

2

Full-Scale Calibration Limit 1.05 × FS V max
Zero-Scale Calibration Limit –1.05 × FS V min
Input Span 0.8 × FS V min

START-UP TIME

From Power-On 300 ms typ
From Power-Down Mode 1 ms typ Oscillator Enabled

POWER REQUIREMENTS

Power Supply Voltages AV

–AGND 2.7/3.6 V min/max AVDD = 3 V nom

AV

DD

–DGND 2.7/3.6 V min/max DVDD = 3 V nom

DV

DD

(Normal Mode) 0.55 mA max DVDD = 3 V, 0.43 mA typ

DI

DD

(Normal Mode) 1.1 mA max AVDD = 3 V or 5 V, 0.85 mA typ

AI

DD

(Power-Down Mode) 10 µA max DVDD = 3 V, 32.768 kHz Osc. Running

DI

DD

(Power-Down Mode) 1 µA max AVDD = 3 V or 5 V

AI

DD

Power Supply Rejection (PSR) Input Range = ±2.56 V, AIN = 1 V

Chop Disabled 70 dB min 95 dB typ
Chop Enabled 100 dB typ

NOTES

1

Temperature range is –40°C to +85°C.

2

Not production tested, guaranteed by design and/or characterization data at release.

3

Following a self-calibration this error will be in the order of the noise for the programmed gain and update selected. A system calibration will completely remove this error.

4

Recalibration at any temperature will remove these errors.

5

I/O Port Logic Levels are with respect to AV

Specifications are subject to change without notice.

2

5

and AGND.

DD

1.4/2 V min/V max DVDD = 5 V

0.8/1.4 V min/V max DVDD = 5 V

0.3/0.85 V min/V max DVDD = 5 V

0.95/2 V min/V max DVDD = 3 V

0.4/1.1 V min/V max DVDD = 3 V

0.3/0.85 V min/V max DVDD = 3 V

–70 µA max

Logic Input = DGND, Typical –40 µA @ 5 V

DD

and –20 µA at 3 V

DV

– 0.6 V min DVDD = 3 V, I

DD

0.4 V max DVDD = 3 V, I
4V minDV

= 5 V, I

DD

0.4 V max DVDD = 5 V, I

SOURCE

= 100 µA

SINK

SOURCE

= 1.6 mA

SINK

= 100 µA

= 200 µA

Offset Binary Bipolar Mode

2.1 × FS V max

300 ms typ Oscillator Powered Down

and DVDD can be operated independently of each other.

DD

4.75/5.25 V min/max AV

4.75/5.25 V min DV

0.65 mA max DV

2 µA max DV
30 µA max DV
8 µA max DV

= 5 V nom

DD

= 5 V nom

DD

= 5 V, 0.5 mA typ

DD

= 3 V, Oscillator Powered Down

DD

= 5 V, 32.768 kHz Osc. Running

DD

= 5 V, Oscillator Powered Down

DD

REV. 0

–5–

AD7708/AD7718

AD7708 SPECIFICATIONS

REFIN(+) = 2.5 V; REFIN(–) = AGND; AGND = DGND = 0 V; XTAL1/XTAL2 = 32.768 kHz Crystal Input Buffers Enabled. All specifications T
T

unless otherwise noted.)

MAX

Parameter B Grade Unit Test Conditions

AD7708 (CHOP DISABLED)

Output Update Rate 16.06 Hz min CHOP = 1

No Missing Codes
Resolution 13 Bits p-p ±20 mV Range, SF Word = 69

Output Noise and Update Rates See Tables in ADC Description
Integral Nonlinearity ±15 ppm of FSR max 2ppm Typical
Offset Error
Offset Error Drift vs. Temp
Full-Scale Error
Gain Drift vs. Temp
Negative Full-Scale Error ±0.003 % FSR typ

ANALOG INPUTS

Differential Input Full-Scale Voltage ±1.024 × REFIN/GAIN V nom REFIN Refers to Both REFIN1 and

Absolute AIN Voltage Limits AGND + 100 mV V min AIN1–AIN10 and AINCOM with

Absolute AINCOM Voltage Limits AGND – 30 mV V min NEGBUF = 0

Analog Input Current AIN1–AIN10 and AINCOM with

DC Input Current
DC Bias Current Drift ±5 pA/°C typ

AINCOM Input Current NEGBUF = 0

DC Input Current
DC Bias Current Drift ±2 pA/V/°C typ

Normal-Mode Rejection

@ 50 Hz 100 dB min 50 Hz ± 1 Hz, SF Word = 82
@ 60 Hz 100 dB min 60 Hz ± 1 Hz, SF Word = 68

Common-Mode Rejection

@ DC 90 dB min 100 dB typ, Analog Input = 1 V,

@ 50 Hz 100 dB typ 50 Hz ± 1 Hz, SF Word = 82
@ 60 Hz 100 dB typ 60 Hz ± 1 Hz, SF Word = 68

REFERENCE INPUTS (REFIN1 AND REFIN2)

REFIN(+) to REFIN(–) Voltage 2.5 V nom REFIN Refers to Both REFIN1 and

REFIN(+) to REFIN(–) Range

REFIN Common-Mode Range AGND – 30 mV V min

Reference DC Input Current 0.5 µA/V typ
Reference DC Input Current Drift ± 0.1 nA/V/°C typ
Normal-Mode Rejection

@ 50 Hz 100 dB min 50 Hz ± 1 Hz, SF Word = 82
@ 60 Hz 100 dB min 60 Hz ± 1 Hz, SF Word = 68

Common-Mode Rejection Input Range = ±2.56 V

@ DC 100 dB typ Analog Input = 1 V. Input Range = ± 2.56 V
@ 50 Hz 100 dB typ
@ 60 Hz 100 dB typ

2

3

4

3

4

2

2

2

2

2

1

(AVDD = 2.7 V to 3.6 V or 4.75 V to 5.25 V, DVDD = 2.7 V to 3.6 V or 4.75 V to 5.25 V,

1.365 kHz max
16 Bits min

16 Bits p-p ±2.56 V Range, SF Word = 69

±0.65 LSB typ Following a Self-Calibration
±200 nV/°C typ
±0.75 LSB typ
±0.5 ppm/°C typ

REFIN2. REFIN = REFIN(+) – REFIN(–)

GAIN = 1 to 128

– 100 mV V max NEGBUF = 1

AV

DD

+ 30 mV V max

AV

DD

±1 nA max

±125 nA/V typ ±2.56 V Range

1V min
AV

DD

+ 30 mV V max

AV

DD

V max

NEGBUF = 1

Input Range = ±2.56 V

110 dB typ on ±20 mV Range

REFIN2

MIN

to

–6–

REV. 0

AD7708/AD7718

Parameter B Grade Unit Test Conditions

AD7708 (CHOP ENABLED)

Output Update Rate 5.4 Hz min CHOP = 1

No Missing Codes

2

Resolution 13 Bits p-p ±20 mV Range, 20 Hz Update Rate

Output Noise and Update Rates See Tables in

Integral Nonlinearity ±15 ppm of FSR max 2 ppm Typical
Offset Error
Offset Error Drift vs. Temp
Full-Scale Error
Gain Drift vs. Temp

3

4

3

4

ANALOG INPUTS

Differential Input Full-Scale Voltage ±1.024 × REFIN/GAIN V nom REFIN Refers to Both REFIN1 and

Range Matching ±2 µV typ Analog Input = 18 mV
Absolute AIN Voltage Limits AGND + 100 mV V min AIN1–AIN10 and AINCOM with

Absolute AINCOM Voltage Limits AGND – 30 mV V min NEGBUF = 0

Analog Input Current AIN1–AIN10 and AINCOM with

DC Input Current

2

DC Input Current Drift ±5 pA/°C typ

AINCOM Input Current NEGBUF = 0

DC Input Current
DC Bias Current Drift ±2 pA/V/°C typ

Normal-Mode Rejection

2

2

@ 50 Hz 100 dB min 50 Hz ± 1 Hz, SF Word = 82
@ 60 Hz 94 dB min 60 Hz ± 1 Hz, SF Word = 68

Common-Mode Rejection

@ DC 90 dB min 100 dB typ, Analog Input = 1 V,

@ 50 Hz
@ 60 Hz

2

2

REFERENCE INPUTS (REFIN1 AND REFIN2)

REFIN(+) to REFIN(–) Voltage 2.5 V nom REFIN Refers to Both REFIN1 and

REFIN(+) to REFIN(–) Range

2

REFIN Common-Mode Range AGND – 30 mV V min

Reference DC Input Current
Reference DC Input Current Drift ± 0.01 nA/V/°C typ
Normal-Mode Rejection

2

2

@ 50 Hz 100 dB min 50 Hz ± 1 Hz, SF Word = 82
@ 60 Hz 100 dB min 60 Hz ± 1 Hz, SF Word = 68

Common-Mode Rejection Input Range = ±2.56 V

@ DC 110 dB typ Analog Input = 1 V
@ 50 Hz 110 dB typ 50 Hz ± 1 Hz, 20 Hz Update Rate
@ 60 Hz 110 dB typ 60 Hz ± 1 Hz, 20 Hz Update Rate

LOGIC INPUTS

All Inputs Except SCLK and XTAL1

V

INL

V

INH

5

2

, Input Low Voltage 0.8 V max DVDD = 5 V

, Input High Voltage 2.0 V min DVDD = 3 V or 5 V

105 Hz max 0.732 ms Increments
16 Bits min 20 Hz Update Rate

16 Bits p-p ±2.56 V Range, 20 Hz Update Rate

ADC Description

±3 µV typ Calibration is Accurate to ±0.5 LSB
10 nV/°C typ

±0.75 LSB typ Includes Positive and Negative ERRORS
±0.5 ppm/°C typ

REFIN2. REFIN = REFIN(+) REFIN(–)
GAIN = 1 to 128

AV

– 100 mV V max NEGBUF = 1

DD

AV

+ 30 mV V max

DD

NEGBUF = 1

±1 nA max

±125 nA/V typ

Input Range = ±2.56 V

110 dB typ on ±20 mV Range
100 dB min 50 Hz ± 1 Hz, 20 Hz Update Rate
100 dB min 60 Hz ± 1 Hz, 20 Hz Update Rate

REFIN2
1V min
AV

DD

AV

+ 30 mV V max

DD

V max

±0.5 µA/V typ

0.4 V max DV

DD

= 3 V

REV. 0

–7–

1

AD7718–SPECIFICATIONS

AD7708

2.5 V ; REFIN(–) = AGND; AGND = DGND = 0 V; XTAL1/XTAL2 = 32.768 kHz Crystal Input Buffer Enabled. All specifications T

Parameter B Grade Unit Test Conditions

LOGIC INPUTS (Continued)

SCLK Only (Schmitt-Triggered Input)

V

T(+)

V

T(–)

V

T(+)–VT(–)

V

T(+)

V

T(–)

V

T(+)–VT(–)

XTAL1 Only

V

INL

V

INH

V

INL

V

INH

2

, Input Low Voltage 0.8 V max DVDD = 5 V

, Input High Voltage 3.5 V min DVDD = 5 V

, Input Low Voltage 0.4 V max DVDD = 3 V

, Input High Voltage 2.5 V min DVDD = 3 V

Input Currents ±10 µA max Logic Input = DV

Input Capacitance 10 pF typ All Digital Inputs

LOGIC OUTPUTS (Excluding XTAL2)

VOH, Output High Voltage

, Output Low Voltage

V

OL

, Output High Voltage

V

OH

, Output Low Voltage

V

OL

2

2

2

2

Floating State Leakage Current ±10 µA max
Floating State Output Capacitance ±10 pF typ
Data Output Coding Binary Unipolar Mode

SYSTEM CALIBRATION

2

Full-Scale Calibration Limit 1.05 × FS V max
Zero-Scale Calibration Limit –1.05 × FS V min
Input Span 0.8 × FS V min

START-UP TIME

From Power-On 300 ms typ
From Power-Down Mode 1 ms typ

POWER REQUIREMENTS

Power Supply Voltages AV

–AGND 2.7/3.6 V min/max AVDD = 3 V nom

AV

DD

–DGND 2.7/3.6 V min/max DVDD = 3 V nom

DV

DD

(Normal Mode) 0.55 mA max DVDD = 3 V, 0.43 mA typ

DI

DD

(Normal Mode) 1.1 mA AVDD = 3 V or 5 V, 0.85 mA typ

AI

DD

(Power-Down Mode) 10 µA max DVDD = 3 V, 32.768 kHz Osc. Running

DI

DD

(Power-Down Mode) 1 µA max AVDD = 3 V or 5 V

AI

DD

Power Supply Rejection (PSR) Input Range = ±2.56 V, AIN = 1 V

Chop Disabled 70 dB min 95 dB typ
Chop Enabled 100 dB typ

NOTES

1

Temperature range is –40°C to +85°C.

2

Not production tested, guaranteed by design and/or characterization data at release.

3

Following a self-calibration this error will be in the order of the noise for the programmed gain and update selected. A system calibration will completely
remove this error.

4

Recalibration at any temperature will remove these errors.

5

I/O Port Logic Levels are with respect to AV

Specifications are subject to change without notice.

2

5

and AGND.

DD

(AVDD = 2.7 V to 3.6 V or 4.75 V to 5.25 V, DVDD = 2.7 V to 3.6 V or 4.75 V to 5.25 V, REFIN(+) =

to T

MIN

1.4/2 V min/V max DVDD = 5 V

0.8/1.4 V min/V max DVDD = 5 V

0.3/0.85 V min/V max DVDD = 5 V

0.95/2 V min/V max DVDD = 3 V

0.4/1.1 V min/V max DVDD = 3 V

0.3/0.85 V min/V max DVDD = 3 V

–70 µA max

Logic Input = DGND, Typical –40 µA @ 5 V
and –20 µA at 3 V

DVDD – 0.6 V min DVDD = 3 V, I

0.4 V max DVDD = 3 V, I
4V minDV

= 5 V, I

DD

0.4 V max DVDD = 5 V, I

Offset Binary Bipolar Mode

2.1 × FS V max

300 ms typ Oscillator Powered Down

and DVDD can be operated independently of each other.

DD

4.75/5.25 V min/max AV

4.75/5.25 V min DV

0.65 mA DV

2 µA max DV
30 µA max DV
8 µA max DV

= 5 V nom

DD

= 5 V nom

DD

= 5 V, 0.5 mA typ

DD

= 3 V, Oscillator Powered Down

DD

= 5 V, 32.768 kHz Osc. Running

DD

= 5 V, Oscillator Powered Down

DD

unless otherwise noted.)

MAX

DD

= 100 µA

SOURCE

= 100 µA

SINK

= 200 µA

SOURCE

= 1.6 mA

SINK

–8–

REV. 0

AD7708/AD7718

TIMING CHARACTERISTICS

1, 2

(AVDD = 2.7 V to 3.6 V or AVDD = 5 V ⴞ 5%; DVDD = 2.7 V to 3.6 V or DVDD = 5 V ⴞ 5%; AGND =

DGND = 0 V; XTAL = 32.768 kHz; Input Logic 0 = 0 V, Logic 1 = DVDD unless otherwise noted.

Limit at T

MIN

, T

MAX

Parameter (B Version) Unit Conditions/Comments

t

1

t

2

32.768 kHz typ Crystal Oscillator Frequency
50 ns min RESET Pulsewidth

Read Operation

t

3

t

4

4

t

5

0 ns min RDY to CS Setup Time
0 ns min CS Falling Edge to SCLK Active Edge Setup Time
0 ns min SCLK Active Edge to Data Valid Delay

3

3

60 ns max DVDD = 4.5 V to 5.5 V

4, 5

t

5A

80 ns max DV
0 ns min CS Falling Edge to Data Valid Delay

= 2.7 V to 3.6 V

DD

3

60 ns max DVDD = 4.5 V to 5.5 V
80 ns max DV

t

6

t

7

t

8

6

t

9

100 ns min SCLK High Pulsewidth
100 ns min SCLK Low Pulsewidth
0 ns min CS Rising Edge to SCLK Inactive Edge Hold Time
10 ns min Bus Relinquish Time after SCLK Inactive Edge
80 ns max

t

10

100 ns max SCLK Active Edge to RDY High

Write Operation

t

11

t

12

t

13

t

14

t

15

t

16

NOTES

1

Sample tested during initial release to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of DVDD) and timed from a voltage
level of 1.6 V.

2

See Figures 1 and 2.

3

SCLK active edge is falling edge of SCLK.

4

These numbers are measured with the load circuit of Figure 1 and defined as the time required for the output to cross the VOL or VOH limits.

5

This specification only comes into play if CS goes low while SCLK is low. It is required primarily for interfacing to DSP machines.

6

These numbers are derived from the measured time taken by the data output to change 0.5 V when loaded with the load circuit of Figure 1. The measured number is
then extrapolated back to remove effects of charging or discharging the 50 pF capacitor. This means that the times quoted in the timing characteristics are the true
bus relinquish times of the part and as such are independent of external bus loading capacitances.

7

RDY returns high after the first read from the device after an output update. The same data can be read again, if required, while RDY is high, although care should
be taken that subsequent reads do not occur close to the next output update.

Specifications subject to change without notice.

0 ns min CS Falling Edge to SCLK Active Edge Setup Time
30 ns min Data Valid to SCLK Edge Setup Time
25 ns min Data Valid to SCLK Edge Hold Time
100 ns min SCLK High Pulsewidth
100 ns min SCLK Low Pulsewidth
0 ns min CS Rising Edge to SCLK Edge Hold Time

= 2.7 V to 3.6 V

DD

3

3, 7

3

3

REV. 0

DD

DD

DD

= 5V

= 3V)

DD

= 5V

= 3V)

TO OUTPUT

PIN

50pF

(1.6mA WITH DV

I

SINK

100␮A WITH DV

1.6V

I

SOURCE

(200␮A WITH DV
100␮A WITH DV

Figure 1. Load Circuit for Timing Characterization

–9–

AD7708/AD7718

WARNING!

ESD SENSITIVE DEVICE

ABSOLUTE MAXIMUM RATINGS*

(TA = 25°C unless otherwise noted)

AVDD to AGND . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V

AV

to DGND . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V

DD

DV

to AGND . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V

DD

to DGND . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V

DV

DD

AGND to DGND . . . . . . . . . . . . . . . . . . –0.05 V to +0.05 V

AV

to DVDD . . . . . . . . . . . . . . . . . . . . . . . . . –5 V to +5 V

DD

Analog Input Voltage to AGND . . . . –0.3 V to AV

Reference Input Voltage to AGND . . –0.3 V to AV

+0.3 V

DD

+0.3 V

DD

Total AIN/REFIN Current (Indefinite) . . . . . . . . . . . . 30 mA

Digital Input Voltage to DGND . . . . –0.3 V to DV

Digital Output Voltage to DGND . . . –0.3 V to DV

+0.3 V

DD

+0.3 V

DD

Operating Temperature Range . . . . . . . . . . . –40°C to +85°C

Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C

ORDERING GUIDE

Temperature Package Package

Model Range Description Option

AD7708BR –40°C to +85°C SOIC R-28
AD7708BRU –40°C to +85°C TSSOP RU-28
EVAL-AD7708EB Evaluation Board
AD7718BR –40°C to +85°C SOIC R-28
AD7718BRU –40°C to +85°C TSSOP RU-28
EVAL-AD7718EB Evaluation Board

Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . 150°C

SOIC Package

Thermal Impedance . . . . . . . . . . . . . . . . . . . 71.4°C/W

θ

JA

θ

Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 23°C/W

JC

TSSOP Package

Thermal Impedance . . . . . . . . . . . . . . . . . . . 97.9°C/W

θ

JA

θ

Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 14°C/W

JC

Lead Temperature, Soldering

Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . 215°C

Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220°C

*Stresses above those listed under Absolute Maximum Ratings may cause perma-

nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD7708/AD7718 features proprietary ESD protection circuitry, permanent damage may occur
on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions
are recommended to avoid performance degradation or loss of functionality.

–10–

REV. 0

SCLK

RDY

SCLK

CS

CS

DIN

AD7708/AD7718

t

11

t

12

t

13

MSB

t

14

t

15

Figure 2. Write Cycle Timing Diagram

t

3

t

4

t

6

LSB

t

t

16

10

t

8

DOUT

t

t

5

t

5A

MSB

7

t

6

t

9

LSB

Figure 3. Read Cycle Timing Diagram

REV. 0

–11–

AD7708/AD7718

PIN FUNCTION DESCRIPTIONS

Pin No Mnemonic Function

1 AIN7 Analog Input Channel 7. Programmable-gain analog input that can be used as a pseudo-

differential input when used with AINCOM, or as the positive input of a fully-differential input
pair when used with AIN8. (See ADC Control Register section.)

2 AIN8 Analog Input Channel 8. Programmable-gain analog input that can be used as a pseudo-

differential input when used with AINCOM, or as the negative input of a fully-differential input
pair when used with AIN7. (See ADC Control Register section.)

3AV

DD

4 AGND Analog Ground
5 REFIN1(–) Negative Reference Input. This reference input can lie anywhere between AGND and AV
6 REFIN1(+) Positive reference input. REFIN(+) can lie anywhere between AVDD and AGND. The nominal

7 AIN1 Analog Input Channel 1. Programmable-gain analog input that can be used as a pseudo-

8 AIN2 Analog Input Channel 2. Programmable-gain analog input that can be used as a pseudo-

9 AIN3 Analog Input Channel 3. Programmable-gain analog input that can be used as a pseudo-

10 AIN4 Analog Input Channel 4. Programmable-gain analog input that can be used as a pseudo-

11 AIN5 Analog Input Channel 5. Programmable-gain analog input that can be used as a pseudo-

12 AINCOM All analog inputs are referenced to this input when configured in pseudo-differential input mode.
13 REFIN2(+)/AIN9 Positive reference input/analog input. This input can be configured as a reference input with the

14 REFIN2(–)/AIN10 Negative reference input/analog input. This pin can be configured as a reference or analog input.

15 AIN6 Analog Input Channel 6. Programmable-gain analog input that can be used as a pseudo-

16 P2 P2 can act as a general-purpose Input/Output bit referenced between AV

17 AGND It is recommended that this pin be tied directly to AGND.
18 P1 P1 can act as a general-purpose Input/Output bit referenced between AV

19 RESET Digital input used to reset the ADC to its power-on-reset status. This pin has a weak pull-up

20 SCLK Serial clock input for data transfers to and from the ADC. The SCLK has a Schmitt-trigger

Analog Supply Voltage

– 1 V.

DD

reference voltage [REFIN(+)–REFIN(–)] is 2.5 V but the part is functional with a reference
range from 1 V to AV

DD

.

differential input when used with AINCOM, or as the positive input of a fully-differential input
pair when used with AIN2. (See ADC Control Register Section.)

differential input when used with AINCOM, or as the negative input of a fully-differential input
pair when used with AIN1. (See ADC Control Register section.)

differential input when used with AINCOM, or as the positive input of a fully-differential input
pair when used with AIN4. (See ADC Control Register section.)

differential input when used with AINCOM, or as the negative input of a fully-differential input
pair when used with AIN3. (See ADC Control Register section.)

differential input when used with AINCOM, or as the positive input of a fully-differential input
pair when used with AIN6. (See ADC Control Register section ADCCON.)

same characteristics as REFIN1(+) or as an additional analog input. When configured as an
analog input this pin provides a programmable-gain analog input that can be used as a pseudo­differential input when used with AINCOM, or as the positive input of a fully-differential input
pair when used with AIN10. (See ADC Control Register section.)

When configured as a reference input it provides the negative reference input for REFIN2.
When configured as an analog input it provides a programmable-gain analog input that can be
used as a pseudo-differential input when used with AINCOM, or as the negative input of a fully­differential input pair when used with AIN9. (See ADC Control Register section.)

differential input when used with AINCOM, or as the negative input of a fully-differential input
pair when used with AIN5. (See ADC Control Register section.)

and AGND. There

is a weak pull-up to AV

is a weak pull-up to AV

internally to DV

DD

.

internally on this pin.

DD

internally on this pin.

DD

DD

and AGND. There

DD

input making an opto-isolated interface more robust. The serial clock can be continuous with all
data transmitted in a continuous train of pulses. Alternatively, it can be a noncontinuous clock
with the information being transmitted to or from the AD7708/AD7718 in smaller batches of data.

–12–

REV. 0

AD7708/AD7718

Pin No Mnemonic Function

21 CS Chip Select Input. This is an active low logic input used to select the AD7708/AD7718. CS can

be used to select the AD7708/AD7718 in systems with more than one device on the serial bus or
as a frame synchronization signal in communicating with the device. CS can be hardwired low,
allowing the AD7708/AD7718 to be operated in 3-wire mode with SCLK, DIN, and DOUT
used to interface with the device.

22 RDY RDY is a logic low status output from the AD7708/AD7718. RDY is low when valid data exists

in the data register for the selected channel. This output returns high on completion of a read
operation from the data register. If data is not read, RDY will return high prior to the next update
indicating to the user that a read operation should not be initiated. The RDY pin also returns
low following the completion of a calibration cycle. RDY does not return high after a calibration
until the mode bits are written to enabling a new conversion or calibration.

23 DOUT Serial data output with serial data being read from the output shift register of the ADC. The output

shift register can contain data from any of the on-chip data, calibration or control registers.

24 DIN Serial Data Input with serial data being written to the input shift register on the AD7708/AD7718

Data in this shift register is transferred to the calibration or control registers within the ADC

depending on the selection bits of the Communications register.
25 DGND Ground Reference Point for the Digital Circuitry.
26 DV

DD

27 XTAL2 Output from the 32 kHz Crystal Oscillator or Resonator Inverter.
28 XTAL1 Input to the 32 kHz Crystal Oscillator or Resonator Inverter.

Digital Supply Voltage, 3 V or 5 V Nominal.

PIN CONFIGURATION

1

AIN7

AIN8

2

AV

3

DD

AGND

4

AIN1

AIN2

AIN3

AIN4

AIN5

AD7708/

5

AD7718

6

TOP VIEW

(Not to Scale)

7

8

9

10

11

12

13

14

REFIN1(–)

REFIN1(+)

AINCOM

REFIN2(+)/AIN9

REFIN2(–)/AIN10

28

27

26

25

24

23

22

21

20

19

18

17

16

15

XTAL1

XTAL2

DV

DD

DGND

DIN

DOUT

RDY

CS

SCLK

RESET

P1

AGND

P2

AIN6

REV. 0

–13–

AD7708/AD7718

–Typical Performance Characteristics

8389600

8389400

8389200

8389000

8388800

8388600

CODE READ

8388400

8388200

8388000

AVDD = DVDD = 5V
INPUT RANGE = ⴞ20mV

RMS NOISE = 0.58␮V rms

0 1000100

200 300

REFIN1(+)–REFIN1(–) = 2.5V
UPDATE RATE = 19.79Hz

400 500 600 700 800 900

READING NUMBER

TA = 25ⴗC
V

= 2.5V

REF

TPC 1. AD7718 Typical Noise Plot on ±20 mV Input Range
with 19.79 Hz Update Rate

9

8

7

6

5

4

3

2

1

0

8388721

8388499

8388547

8388615

8388579

8388687

8388657

8388779

8388754

8388841

8388805

8388906

8388874

8388985

8388941

8389033

8389110

8388382

8388039

8388449

TPC 2. AD7718 Noise Distribution Histogram

26

CHOP = 0

24

22

20

NO MISSING CODES – Min

18

16

040302010 50 10090807060

UPDATE RATE – Hz

110

TPC 4. AD7718 No-Missing Codes Performance

32772

32771

32770

32769

32768

CODE READ

32767

32766

32765

32764

1000 200 400300

AVDD = DVDD = 5V
INPUT RANGE = ⴞ20mV

UPDATE RATE = 19.79Hz

500

READING NUMBER

600 700 800 900 1000

V

REF

T

A

= 2.5V

= 25 C

TPC 5. AD7708 Typical Noise Plot on ±20 mV Input Range

3.0

= 2.5V

= 25ⴗC

ⴞ2.56V RANGE

V

REF –

ⴞ20mV RANGE

V

2.5

2.0

AVDD = DVDD = 5V
V

REF

1.5

INPUT RANGE = ⴞ2.56V
UPDATE RATE = 19.79Hz
T

A

RMS NOISE – ␮V

1.0

0.5

0

1.0 3.02.52.01.5 3.5 5.04.54.0

TPC 3. RMS Noise vs. Reference Input
(AD7718 andAD7708)

–14–

700

600

500

400

300

OCCURRENCE

200

100

0

3276732766 32768 3277032769

CODE

TPC 6. AD7708 Noise Histogram

32771

REV. 0