ANALOG DEVICES AD7707 Service Manual

3 V/5 V, ±10 V Input Range, 1 mW

A

V

3-Channel 16-Bit, Sigma-Delta ADC

FEATURES

Charge balancing ADC

16 bits, no missing codes

±0.003% nonlinearity
High level (±10 V) and low level (±10 mV) input channels
True bipolar ±100 mV capability on low level input

Channels without requiring charge pumps
Programmable gain front end

Gains from 1 to 128
3-wire serial interface

SPI, QSPI™, MICROWIRE™ and DSP compatible

Schmitt trigger input on SCLK
Ability to buffer the analog input

2.7 V to 3.3 V or 4.75 V to 5.25 V operation
Power dissipation 1 mW at 3 V
Standby current 8 μA maximum
20-lead SOIC and TSSOP packages

GENERAL DESCRIPTION

The AD7707 is a complete analog front end for low frequency
measurement applications. This 3-channel device can accept
either low level input signals directly from a transducer or high
level (±10 V) signals and produce a serial digital output. It employs
a Σ-Δ conversion technique to realize up to 16 bits of no missing
codes performance. The selected input signal is applied to a
proprietary programmable gain front end based around an analog
modulator. The modulator output is processed by an on-chip
digital filter. The first notch of this digital filter can be pro­grammed via an on-chip control register allowing adjustment
of the filter cutoff and output update rate.

The AD7707 operates from a single 2.7 V to 3.3 V or 4.75 V to

5.25 V supply. The AD7707 features two low level pseudo differen­tial analog input channels, one high level input channel and a
differential reference input. Input signal ranges of 0 mV to 20 mV
through 0 V to 2.5 V can be accommodated on both low level input
channels when operating with a VDD of 5 V and a reference of

2.5 V. They can also handle bipolar input signal ranges of ±20 mV
through ±2.5 V, which are referenced to the LCOM input. The
AD7707, with a 3 V supply and a 1.225 V reference, can handle
unipolar input signal ranges of 0 mV to 10 mV through 0 V to

1.225 V. Its bipolar input signal ranges are ±10 mV through ±1.225 V.

The high level input channel can accept input signal ranges of ±10 V,
±5 V, 0 V to 10 V and 0 V to 5 V. The AD7707 thus performs all
signal conditioning and conversion for a 3-channel system.

The AD7707 is ideal for use in smart, microcontroller or DSP­based systems. It features a serial interface that can be configured

AD7707

FUNCTIONAL BLOCK DIAGRAM

DV

DD

DD

REF IN(–) REF IN(+)

AD7707

CHARGE

BALANCING

AIN1

AIN2

LOCOM

AIN3

VBIAS

HICOM

MCLK IN

MCLK OUT

30kΩ

5kΩ

5kΩ

15kΩ

30kΩ

MUX

CLOCK

GENERATION

AGND DGND

BUF

PGA

A = 1 ≈ 128

Figure 1.

for 3-wire operation. Gain settings, signal polarity and update
rate selection can be configured in software using the input
serial port. The part contains self-calibration and system calibra­tion options to eliminate gain and offset errors on the part itself
or in the system.

CMOS construction ensures very low power dissipation, and the
power-down mode reduces the standby power consumption to
20 μW typical. This part is available in a 20-lead wide body (0.3
inch) small outline (SOIC) package and a low profile 20-lead TSSOP.

PRODUCT HIGHLIGHTS

1. The AD7707 consumes less than 1 mW at 3 V supplies and

1 MHz master clock, making it ideal for use in low power
systems. Standby current is less than 8 μA.

2. On-chip thin-film resistors allow ±10 V, ±5 V, 0 V to 10 V,

and 0 V to 5 V high level input signals to be directly accom­modated on the analog inputs without requiring split supplies
or charge-pumps.

3. The low level input channels allow the AD7707 to accept

input signals directly from a strain gage or transducer
removing a considerable amount of signal conditioning.

4. The part features excellent static performance specifications

with 16 bits, no missing codes, ±0.003% accuracy, and low
rms noise. Endpoint errors and the effects of temperature
drift are eliminated by on-chip calibration options, which
remove zero-scale and full-scale errors.

A/D CONVERT ER

Σ-Δ

MODULATOR

DIGITAL FILTER

SERIAL INT ERFACE

REGISTE R BANK

DRDY RESET

SCLK

CS

DIN

DOUT

08691-001

Rev. B

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] ©2000–2010 Analog Devices, Inc. All rights reserved.

AD7707

TABLE OF CONTENTS

Features .............................................................................................. 1

General Description ......................................................................... 1

Functional Block Diagram .............................................................. 1

Product Highlights ........................................................................... 1

Revision History ............................................................................... 3

Specifications ..................................................................................... 4

Timing Characteristics ................................................................ 8

Absolute Maximum Ratings ............................................................ 9

ESD Caution .................................................................................. 9

Pin Configuration and Function Descriptions ........................... 10

Typical Performance Characteristics ........................................... 12

OVtput Noise .................................................................................. 14

Output Noise For Low Level Input Channels

(5 V Operation) .......................................................................... 14

Output Noise For Low Level Input Channels

(3 V Operation) .......................................................................... 15

Output Noise For High Level Input Channel AIN3

(5 V Operation) .......................................................................... 16

Output Noise For High Level Input Channel AIN3

(3 V Operation) .......................................................................... 17

On-Chip Registers .......................................................................... 18

Communications Register (RS2, RS1, RS0 = 0, 0, 0) ............. 18

Calibration Sequences .................................................................... 23

Circuit Description ......................................................................... 24

Analog Input ................................................................................... 25

Analog Input Ranges .................................................................. 25

Input Sample Rate ...................................................................... 26

Bipolar/Unipolar Inputs ............................................................ 26

Reference Input ............................................................................... 27

Digital Filtering ............................................................................... 28

Filter Characteristics .................................................................. 28

Postfiltering ................................................................................. 29

Analog Filtering .......................................................................... 29

Calibration ....................................................................................... 30

Self-Calibration ........................................................................... 30

System Calibration ..................................................................... 30









Span and Offset Limits on the Low Level Input Channels,

AIN1 and AIN2 .......................................................................... 31

Span and Offset Limits on the High Level Input Channel

AIN3 ............................................................................................. 31

Power-Up and Calibration ........................................................ 32

Using the AD7707 .......................................................................... 33

Clocking and Oscillator Circuit ............................................... 33

System Synchronization ............................................................ 33

Reset Input .................................................................................. 34

Standby Mode ............................................................................. 34

Accuracy ...................................................................................... 34

Drift Considerations .................................................................. 34

Power Supplies ................................................................................ 35

Supply Current ............................................................................ 35

Grounding and Layout .............................................................. 35

Digital Interface .............................................................................. 36

Configuring the AD7707 ............................................................... 37

Microcomputer/Microprocessor Interfacing .............................. 39

AD7707to68HC11 Interface .................................................. 39

AD7707to8XC51 Interface ..................................................... 40

Code For Setting Up the AD7707 ................................................ 41

C Code for Interfacing AD7707 to 68HC11 ........................... 41

Applications Information .............................................................. 43

Data Acquisition ......................................................................... 43

Smart Valve/Actuator Control .................................................. 43

Pressure Measurement ............................................................... 45

Thermocouple Measurement ................................................... 45

RTD Measurement ..................................................................... 45

Chart Recorders .......................................................................... 46

Accommodating Various High Level Input Ranges .............. 46

Typical Input Currents ............................................................... 46

Output Noise For High Level Input Channel, AIN3 ................. 47

5 V Operation ............................................................................. 47

3 V Operation ............................................................................. 48

Outline Dimensions ....................................................................... 49

Ordering Guide .......................................................................... 50





Rev. B | Page 2 of 52

AD7707

REVISION HISTORY

1/10—Rev. A to Rev B

U

pdated Format .................................................................. Universal

Changes to Features Section ............................................................ 1

Changes to Table 1

Changes to Table 5 ............................................................................ 9

Changes to Output Noise For Low Level Input Channels

(3 V Operation) Section ................................................................. 14

Changes to Output Noise For High Level Input Channel AIN3

(5 V Operation) Section ................................................................. 15

Changed Output Noise For High Level Input Channel AIN3
(5 V Operation) Section Heading to Output Noise For High

Level Input Channel AIN3 (3 V Operation) ............................... 17

Changes to Table 16 ........................................................................ 19

Changes to Zero-Scale Calibration Register (RS2, RS1, RS0 =

1, 1, 0); Power-On/Reset Status: 0x1F4000 Section .................... 22

Changes to Calibration Sequences Section .................................. 23

Changes to Circuit Description Section ....................................... 24

...................................................................................... 4

Deleted Evaluating the AD7707 Performance Section .............. 27

Changes to Digital Filtering Section and

Filter Characteristics Section ......................................................... 28

Deleted AD7707 to ADSP-2103/ADSP-2105 Interface

Section .............................................................................................. 31

Deleted Figure 23; Renumbered Sequentially ............................. 31

Moved Figure 18 .............................................................................. 33

Changes to Figure 19 and Supply Current Section ..................... 35

Change to Smart Valve/Actuator Control Section and

Figure 25 ........................................................................................... 43

Changes to Figure 27 ...................................................................... 44

Added Titles to Table 28, Table 29, and Table 30 ........................ 46

Updated Outline Dimensions ........................................................ 49

Changes to Ordering Guide ........................................................... 50

2/00—Rev. 0 to Rev. A

Rev. B | Page 3 of 52

AD7707

SPECIFICATIONS

AVDD = DVDD = 3 V or 5 V, REF IN(+) = 1.225 V with AVDD = 3 V and 2.5 V with AVDD = 5 V; REF IN(−) = GND; VBIAS = REFIN(+);
MCLK IN = 2.4576 MHz unless otherwise noted. All specifications T

MIN

to T

, unless otherwise noted.

MAX

Table 1.

Parameter B Version

STATIC PERFORMANCE

Low Level Input Channels (AIN1 and AIN2)

No Missing Codes 16 Bits min Guaranteed by design; filter notch < 60 Hz
Output Noise

See

1

Tab le 7 to

Unit Conditions/Comments

Depends on filter cutoffs and selected gain

Tab le 10

Integral Nonlinearity
Unipolar Offset Error
Unipolar Offset Drift
Bipolar Zero Error
Bipolar Zero Drift

2

3

4

3

4

±0.003 % of FSR max Filter notch < 60 Hz; typically ±0.0003%

0.5 μV/°C typ

0.5 μV/°C typ For gains of 1, 2, and 4

0.1 μV/°C typ For gains of 8, 16, 32, 64, and 128
Positive Full-Scale Error

4, 8

3, 7

4, 6

Full-Scale Drift
Gain Error
Gain Drift

3, 5

Bipolar Negative Full-Scale Error
Bipolar Negative Full-Scale Drift

2

4

0.5 μV/°C typ

0.5 ppm of FSR/°C typ
±0.003 % of FSR max Typically ±0.0007%
1 μV/°C typ For gains of 1 to 4

0.6 μV/°C typ For gains of 8 to 128
HIGH LEVEL INPUT CHANNEL (AIN3)

No Missing Codes 16 Bits min Guaranteed by design; filter notch < 60 Hz
Output Noise

See

Table 11 to

Depends on filter cutoffs and selected gain

Table 13

Integral Nonlinearity
Unipolar Offset Error

2

9

±0.003 % of FSR max Filter notch < 60 Hz; typically ±0.0003%

±10 mV max Typically within ±1.5 mV
Unipolar Offset Drift 4 μV/°Ctyp
Bipolar Zero Error

9

±10 mV max Typically within ±1.5 mV
Bipolar Zero Drift 4 μV/°C typ For gains of 1, 2, and 4
1 μV/°C typ For gains of 8, 16, 32, 64, and 128
Gain Error ±0.2 % typ Typically within ±0.05%
Gain Drift 0.5 ppm of FSR/°C typ
Negative Full-Scale Error

2

±0.0012 % of FSR typ

LOW LEVEL ANALOG INPUTS/REFERENCE INPUTS Specifications for AIN and REF IN,

unless otherwise noted

Input Common-Mode Rejection (CMR)

2

Low level input channels, AIN1 and AIN2

AVDD = 5 V

Gain = 1 100 dB typ
Gain = 2 105 dB typ
Gain = 4 110 dB typ
Gain = 8 to 128 130 dB typ

AVDD = 3 V

Gain = 1 105 dB typ
Gain = 2 110 dB typ
Gain = 4 120 dB typ

Gain = 8 to 128 130 dB typ
Normal-Mode 50 Hz Rejection
Normal-Mode 60 Hz Rejection
Common-Mode 50 Hz Rejection

2

2

2

98 dB typ For filter notches of 10 Hz, 25 Hz, 50 Hz; ±0.02 × f
98 dB typ For filter notches of 10 Hz, 20 Hz, 60 Hz; ±0.02 × f
150 dB typ For filter notches of 10 Hz, 25 Hz, 50 Hz; ±0.02 × f

NOTCH

NOTCH

NOTCH

Rev. B | Page 4 of 52

AD7707

Parameter B Version1 Unit Conditions/Comments

Common-Mode 60 Hz Rejection2

Absolute/Common-Mode REF IN Voltage2

Absolute/Common-Mode AIN Voltage

2, 10

150 dB typ For filter notches of 10 Hz, 20 Hz, 60 Hz, ±0.02 × f
AGND to AV

V min to V max

DD

AGND – 100 mV V min BUF bit of setup register = 0
AVDD + 30 mV V max
AGND + 50 mV V min BUF bit of setup register = 1
AVDD − 1.5 V V max

AIN DC Input Current2
AIN Sampling Capacitance2
AIN Differential Voltage Range

11, 12

0 to +V

±V

AIN Input Sampling Rate, fS Gain × f
f

1 nA max

10 pF max BUF = 0

/gain V nom

REF

/gain V nom

REF

/64 Hz nom For gains of 1 to 4

CLKIN

/8 For gains of 8 to 128

CLKIN

Unipolar input range (

Bipolar input range (

B/U bit of setup register = 1)

B/U bit of setup register = 0)

Reference Input Range

REF IN(+) − REF IN(−) Voltage 1/1.75 V min/max AVDD = 2.7 V to 3.3 V; V

= 1.225 V ± 1% for

REF

specified performance
REF IN(+) − REF IN(−) Voltage 1/3.5 V min/max AVDD = 4.75 V to 5.25 V; V

= 2.5 V ± 1% for

REF

specified performance
REF IN Input Sampling Rate, fS f

/64

CLKIN

±100 mV INPUT RANGE Low level input channels, AIN1 and AIN2; gain = 16,

unbuffered mode
INL2
Input Common-Mode Rejection (CMR)2
Power Supply Rejection (PSR)2

±0.003 % of FSR max Filter notch < 60 Hz
80 dB typ
90 dB typ

HIGH LEVEL ANALOG INPUT CHANNEL (AIN3) AIN3 is with respect to HICOM

AIN3 Voltage Range +10 V max

−10 V min
Normal Mode 50 Hz Rejection 78 dB typ For filter notches of 10 Hz, 25 Hz, 50 Hz; ±0.02 × f
Normal Mode 60 Hz Rejection 78 dB typ For filter notches of 10 Hz, 20 Hz, 60 Hz; ±0.02 × f
AIN3 Input Sampling Rate, fS Gain × f
f
AIN3 Input Impedance2

CLKIN

27 kΩ min Typically 30 kΩ ± 10%; typical resistor

/64 Hz nom For gains of 1 to 4

CLKIN

/8 Hz nom For gains of 8 to 128

Tempco is −30 ppm/°C
AIN3 Sampling Capacitance2

10 pF max

VBIAS Input Range 0 V/AVDD V min/max Typically REFIN(+) = 2.5 V

LOGIC INPUTS

Input Current

All Inputs Except MCLK IN ±1 μA max Typically ±20 nA
MCLK ±10 μA max Typically ±2 m A

All Inputs Except SCLK and MCLK IN

V

, Input Low Voltage 0.8 V max DVDD = 5 V

INL

0.4 V max DVDD = 3 V
V

, Input High Voltage 2.0 V max DVDD = 3 V and 5 V

INH

SCLK Only (Schmitt Triggered Input) DVDD = 5 V nominal

V

T+

1.4/3 V min/V max
VT− 0.8/1.4 V min/V max
VT+ − VT− 0.4/0.8 V min/V max

SCLK Only (Schmitt Triggered Input) DVDD = 3 V nominal

VT+ 1/2.5 V min/V max
VT− 0.4/1.1 V min/V max
VT+ − VT− 0.375/0.8 V min /V max

NOTCH

NOTCH

NOTCH

Rev. B | Page 5 of 52

AD7707

Parameter B Version1 Unit Conditions/Comments

MCLK IN Only DVDD = 5 V nominal

V

, Input Low Voltage 0.8 V max

INL

V

, Input High Voltage 3.5 V min

INH

MCLK IN Only DVDD = 3 V nominal

V

, Input Low Voltage 0.4 V max

INL

V

, Input High Voltage 2.5 V min

INH

LOGIC OUTPUTS (Including MCLK OUT)

VOL, Output Low Voltage 0.4 V max I

0.4 V max
VOH, Output High Voltage 4 V min

DVDD − 0.6 V min

Floating State Leakage Current ±10 μA max
Floating State Output Capacitance14 9 pF typ

Data Output Coding Binary Unipolar mode
Offset binary Bipolar mode
SYSTEM CALIBRATION

Low Level Input Channels (AIN1 and AIN2)

Positive Full-Scale Calibration Limit15 (1.05 ×

)/gain

V

REF

Negative Full-Scale Calibration Limit15

−(1.05 ×
)/gain

V

REF

Offset Calibration Limit16 −(1.05 ×

)/gain

V

REF

Input Span16

(0.8 × V

(2.1 × V

)/gain V min Gain is the selected PGA gain (1 to 128)

REF

)/gain V max Gain is the selected PGA gain (1 to 128)

REF

V max Gain is the selected PGA gain (1 to 128)

V max Gain is the selected PGA gain (1 to 128)

V max Gain is the selected PGA gain (1 to 128)

High Level Input Channels (AIN3)

Positive Full-Scale Calibration Limit15
Negative Full-Scale Calibration Limit15

(8.4 × V

−(8.4 ×

V

Offset Calibration Limit16

−(8.4 ×

V

Input Span16

(6.4 × V

(16.8 ×

V

)/gain V max Gain is the selected PGA gain (1 to 128)

REF

V max Gain is the selected PGA gain (1 to 128)

)/gain

REF

V max Gain is the selected PGA gain (1 to 128)

)/gain

REF

)/gain V min Gain is the selected PGA gain (1 to 128)

REF

V max Gain is the selected PGA gain (1 to 128)

)/gain

REF

POWER REQUIREMENTS

Power Supply Voltages

AVDD Voltage 2.7 to 3.3 or

4.75 to 5.25 V min to V max For specified performance
DVDD Voltage 2.7 to 5.25 V min to V max For specified performance

Power Supply Currents

AVDD Current AVDD = 3 V or 5 V; gain = 1 to 4

0.27 mA max Typically 0.22 mA; BUF = 0; f

0.6 mA max Typically 0.45 mA; BUF = 1; f
AVDD = 3 V or 5 V; gain = 8 to 128

0.5 mA max Typically 0.38 mA; BUF = 0; f

1.1 mA max Typically 0.81 mA; BUF = 1; f
POWER REQUIREMENTS (Continued)

DVDD Current17 Digital inputs = 0 V or DVDD; external MCLK IN

0.080 mA max Typically 0.06 mA; DVDD = 3 V; f

0.15 mA max Typically 0.13 mA; DVDD = 5 V; f

0.18 mA max Typically 0.15 mA; DVDD = 3 V; f

0.35 mA max Typically 0.3 mA; DVDD = 5 V; f
Power Supply Rejection

18, 19

dB typ

= 800 μA except for MCLK OUT13; DVDD = 5 V

SINK

I

= 100 μA except for MCLK OUT13; DVDD = 3 V

SINK

I

= 200 μA except for MCLK OUT13; DVDD = 5 V

SOURCE

I

= 100 μA except for MCLK OUT13; DVDD = 3 V

SOURCE

= 1 MHz or 2.4576 MHz

CLK IN

= 1 MHz or 2.4576 MHz

CLK IN

= 2.4576 MHz

CLK IN

= 2.4576 MHz

CLK IN

= 1 MHz

CLK IN

= 1 MHz

CLK IN

= 2.4576 MHz

CLK IN

= 2.4576 MHz

CLK IN

Rev. B | Page 6 of 52

AD7707

Parameter B Version

Normal Mode Power Dissipation

17

AVDD = DVDD = 3 V; digital inputs = 0 V or DVDD; external

1

Unit Conditions/Comments

MCLK IN excluding dissipation in the AIN3 attenuator

1.05 mW max Typically 0.84 mW; BUF = 0; f

2.04 mW max Typically 1.53 mW; BUF = 1; f

1.35 mW max Typically 1.11 mW; BUF = 0; f

= 1 MHz, all gains

CLK IN

= 1 MHz; all gains

CLK IN

= 2.4576 MHz,

CLK IN

gain = 1 to 4

2.34 mW max Typically 1.9 mW; BUF = 1; f

= 2.457 6 MHz;

CLK IN

gain = 1 to 4

Normal Mode Power Dissipation17

AV

= DVDD = 5 V; digital inputs = 0 V or DVDD;

DD

external MCLKIN

2.1 mW max Typically 1.75 mW; BUF = 0; f

3.75 mW max Typically 2.9 mW; BUF = 1; f

3.1 mW max Typically 2.6 mW; BUF = 0; f

4.75 mW max Typically 3.75 mW; BUF = 1; f
Standby (Power-Down) Current

20

18 μA max External MCLK IN = 0 V or DVDD; typically 9 μA;

= 5 V

AV

DD

= 1 MHz; all gains

CLK IN

= 1 MHz; all gains

CLK IN

= 2.4576 MHz

CLK IN

= 2.4576 MHz

CLK IN

8 μA max External MCLK IN = 0 V or DVDD; typically 4 μA;

= 3 V

AV

1

Temperature range as follows: B Version, −40°C to +85°C.

2

These numbers are established from characterization or design at initial product release.

3

A calibration is effectively a conversion so these errors are of the order of the conversion noise shown in Table 7 and Table 9 for the low level input channels AIN1 and

AIN2. This applies after calibration at the temperature of interest.

4

Recalibration at any temperature removes these drift errors.

5

Positive full-scale error includes zero-scale errors (unipolar offset error or bipolar zero error) and applies to both unipolar and bipolar input ranges.

6

Full-scale drift includes zero-scale drift (unipolar offset drift or bipolar zero drift) and applies to both unipolar and bipolar input ranges.

7

Gain error does not include zero-scale errors. It is calculated as full-scale error—unipolar offset error for unipolar ranges and full-scale error—bipolar zero error for

bipolar ranges.

8

Gain error drift does not include unipolar offset drift/bipolar zero drift. It is effectively the drift of the part if POMZzero-scale calibrations were performed.

9

Error is removed following a system calibration.

10

This common-mode voltage range is allowed provided that the input voltage on analog inputs does not go more positive than AVDD + 30 mV or go more negative
than AGND − 100 mV. Parts are functional with voltages down to AGND − 200 mV, but with increased leakage at high temperature.

11

The analog input voltage range on AIN(+) is given here with respect to the voltage on LCOM on the low level input channels (AIN1 and AIN2) and is given with

DD

respect to the HCOM input on the high level input channel, AIN3. The absolute voltage on the low level analog inputs should not go more positive than AVDD +
100 mV, or go more negative than GND − 100 mV for specified performance. Input voltages of AGND − 200 mV can be accommodated, but with increased leakage at
high temperature.

12

V

= REF IN(+) − REF IN(−).

REF

13

These logic output levels apply to the MCLK OUT only when it is loaded with one CMOS load.

14

Sample tested at +25°C to ensure compliance.

15

After calibration, if the analog input exceeds positive full scale, the converter outputs all 1s. If the analog input is less than negative full scale, the device outputs all 0s.

16

These calibration and span limits apply provided that the absolute voltage on the analog inputs does not exceed AVDD + 30 mV or go more negative than AGND −
mV. The offset calibration limit applies to both the unipolar zero point and the bipolar zero point.

17

When using a crystal or ceramic resonator across the MCLK pins as the clock source for the device, the DVDD current and power dissipation varies depending on the
crystal or resonator type (see the Clocking and Oscillator Circuit section).

18

Measured at dc and applies in the selected pass band. PSRR at 50 Hz exceeds 120 dB with filter notches of 25 Hz or 50 Hz. PSRR at 60 Hz exceeds 120 dB with filter
notches of 20 Hz or 60 Hz.

19

PSRR depends on both gain and AVDD. See Table 2 and Table 3.

20

If the external master clock continues to run in standby mode, the standby current increases to 150 μA typical at 5 V and 75 μA typical at 3 V. When using a crystal or
ceramic resonator across the MCLK pins as the clock source for the device, the internal oscillator continues to run in standby mode and the power dissipation depends
on the crystal or resonator type (see the Standby Mode section).

Table 2. Low Level Input Channels, AIN1 and AIN2

Gain 1 2 4 8 to 128

AVDD = 3 V 86 78 85 93
AVDD = 5 V 90 78 84 91

Table 3. High Level Input Channel, AIN3

Gain 1 2 4 8 to 128

AVDD = 3 V 68 60 67 75
AVDD = 5 V 72 60 66 73

Rev. B | Page 7 of 52

AD7707

T

TIMING CHARACTERISTICS

AVDD = DVDD = 2.7 V to 5.25 V, AGND = DGND = 0 V; f

Table 4.

Parameter

3, 4

f

CLKIN

1, 2

Limit at T
(B Version) Unit Conditions/Comments

400 kHz min Master clock frequency: crystal oscillator or externally supplied for specified performance

MIN

, T

MAX

5 MHz max
t

0.4 × t

CLKIN LO

t

0.4 × t

CLKIN HI

t1 500 × t

ns min Master clock input low time, t

CLKIN

ns min Master clock input high time

CLKIN

ns nom

CLKIN

t2 100 ns min

Read Operation

t3 0 ns min
t4 120 ns min

5

t

5

0 ns min SCLK falling edge to data valid delay
80 ns max DVDD = 5 V
100 ns max DVDD = 3.0 V
t6 100 ns min SCLK high pulse width
t7 100 ns min SCLK low pulse width
t8 0 ns min

6

t

9

10 ns min Bus relinquish time after SCLK rising edge
60 ns max DVDD = 5 V
100 ns max DVDD = 3.0 V
t10 100 ns max

Write Operation

t11 120 ns min
t12 30 ns min Data valid to SCLK rising edge setup time

t13 20 ns min Data valid to SCLK rising edge hold time
t

100 ns min SCLK high pulse width

14

t

100 ns min SCLK low pulse width

15

t

0 ns min

16

1

Sample tested at +25°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of DVDD) and timed from a voltage level of 1.6 V.

2

See Figure 20 and Figure 21.

3

f

duty cycle range is 45% to 55%. f

CLKIN

higher current than specified and possibly become uncalibrated.

4

The AD7707 is production tested with f

5

These numbers are measured with the load circuit of Figure 2 and defined as the time required for the output to cross the VOL or VOH limits.

6

These numbers are derived from the measured time taken by the data output to change 0.5 V when loaded with the circuit of Figure 2. The measured number is then

must be supplied whenever the AD7707 is not in standby mode. If no clock is present in this case, the device can draw

CLKIN

at 2.4576 MHz (1 MHz for some IDD tests). It is guaranteed by characterization to operate at 400 kHz.

CLKIN

extrapolated back to remove effects of charging or discharging the 50 pF capacitor. This means that the times quoted in the timing characteristics are the true bus
relinquish times of the part and as such are independent of external bus loading capacitances.

7

DRDY

returns high after the first read from the device after an output update. The same data can be read again, if required, while

be taken that subsequent reads do not occur close to the next output update.

= 2.4576 MHz; input logic = 0, Logic 1 = DVDD, unless otherwise noted.

CLKIN

= 1/f

CLKIN

high time

DRDY

pulse width

RESET

to CS setup time

DRDY

falling edge to SCLK rising edge setup time

CS

rising edge to SCLK rising edge hold time

CS

7

SCLK falling edge to DRDY

falling edge to SCLK rising edge setup time

CS

rising edge to SCLK rising edge hold time

CS

I

SINK

high

(800µA AT VDD = 5V

100µA AT V

DD

= 3V)

CLKIN

DRDY

is high, although care should

O OUTPUT

PIN

50pF

I

SOURCE

1.6V

(200µA AT VDD = 5V

100µA AT V

DD

= 3V)

08691-002

Figure 2. Load Circuit for Access Time and Bus Relinquish Time

Rev. B | Page 8 of 52

AD7707

ABSOLUTE MAXIMUM RATINGS

TA = +25°C, unless otherwise noted.

Table 5.

Parameter Rating

AVDD to AGND −0.3 V to +7 V
AVDD to DGND −0.3 V to +7 V
DVDD to AGND −0.3 V to +7 V
DVDD to DGND −0.3 V to +7 V
AVDD to DVDD −0.3 V to +7 V
DGND to AGND −0.3 V to +0.3 V
AIN1, AIN2 Input Voltage to LOCOM −0.3 V to AVDD + 0.3 V
AIN3 Input Voltage to HICOM −11 V to +30 V
VBIAS to AGND −0.3 V to AVDD + 0.3 V
HICOM, LOCOM to AGND −0.3 V to AVDD + 0.3 V
REF IN(+), REF IN(−) to AGND −0.3 V to AVDD + 0.3 V
Digital Input Voltage to DGND −0.3 V to DVDD + 0.3 V
Digital Output Voltage to DGND −0.3 V to DVDD + 0.3 V
Operating Temperature Range

Industrial (B Version) −40°C to +85°C
Storage Temperature Range −65°C to +150°C
Junction Temperature 150°C
SOIC Package, Power Dissipation 450 mW

θJA Thermal Impedance 75°C/W

Lead Temperature, Soldering

Reflow 260°C

TSSOP Package, Power Dissipation 450 mW

θJA Thermal Impedance 139°C/W

Lead Temperature, Soldering

Reflow 260°C

ESD Rating 2.5 kV

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

ESD CAUTION

Rev. B | Page 9 of 52

AD7707

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

SCLK 1

MCLK IN

MCLK OUT 3

2

CS 4

DD

AD7707

TOP VIEW

6

(Not to Scale)

7

RESET 5 DRDY16

AV

AIN1

LOCOM 8 REF IN(+)13

AIN2 9 VBIAS12

AIN3 10 HICOM11

DGND20

19

DV

DIN18

DOUT17

AGND15

14

REF IN(–)

DD

08691-003

Figure 3. Pin Configuration

Table 6. Pin Function Descriptions

Pin No. Mnemonic Description

1 SCLK

Serial Clock, Schmitt-Triggered Logic Input. An external serial clock is applied to this input to access serial data
from the AD7707. This serial clock can be a continuous clock with all data transmitted in a continuous train of
pulses. Alternatively, it can be a noncontinuous clock with the information being transmitted to the AD7707 in
smaller batches of data.

2 MCLK IN

Master Clock Signal for the Device. This can be provided in the form of a crystal/resonator or external clock. A
crystal/resonator can be tied across the MCLK IN and MCLK OUT pins. Alternatively, the MCLK IN pin can be
driven with a CMOS-compatible clock and MCLK OUT left unconnected. The part can be operated with clock
frequencies in the range of 500 kHz to 5 MHz.

3 MCLK OUT

When the master clock for the device is a crystal/resonator, the crystal/resonator is connected between MCLK IN
and MCLK OUT. If an external clock is applied to MCLK IN, MCLK OUT provides an inverted clock signal. This clock
can be used to provide a clock source for external circuitry and is capable of driving one CMOS load. If the user
does not require it, this MCLK OUT can be turned off via the CLKDIS bit of the clock register. This ensures that the
part is not wasting unnecessary power driving capacitive loads on MCLK OUT.

4

Chip Select. This pin is an active low logic input used to select the AD7707. With this input hard-wired low, the

CS

AD7707 can operate in its 3-wire interface mode with SCLK, DIN, and DOUT used to interface to the device. CS
can be used to select the device in systems with more than one device on the serial bus or as a frame
synchronization signal in communicating with the AD7707.

5

Logic Input. Active low input that resets the control logic, interface logic, calibration coefficients, digital filter, and

RESET

analog modulator of the part to power-on status.

6 AV

Analog Supply Voltage, 2.7 V to 5.25 V Operation.

DD

7 AIN1 Low Level Analog Input Channel 1. This is used as a pseudo differential input with respect to LOCOM.
8 LOCOM Common Input for Low Level Input Channels. Analog inputs on AIN1 and AIN2 must be referenced to this input.
9 AIN2 Low Level Analog Input Channel 2. This is used as a pseudo differential input with respect to LOCOM.
10 AIN3 Single-Ended High Level Analog Input Channel with respect to HICOM.

11 HICOM Common Input for )igh -evel *nput $hannel. Analog input on AIN3 must be referenced to this input.

12 VBIAS

VBIAS is used to level shift the high level input channel signal. This signal is used to ensure that the AIN(+) and
AIN(−) signals seen by the internal modulator are within its common-mode range. VBIAS is normally connected

= 5 V and 1.225 V when AVDD = 3 V.

DD

13 REF IN(+)

to 2.5 V when AV
Reference Input. Positive input of the differential reference input to the AD7707. The reference input is

differential with the provision that REF IN(+) must be greater than REF IN(−). REF IN(+) can lie anywhere between

and AGND.

AV

DD

14 REF IN(−)

Reference Input. Negative input of the differential reference input to the AD7707. The REF IN(−) can lie anywhere
between AV

and AGND provided that REF IN(+) is greater than REF IN(−).

DD

15 AGND Analog Ground. Ground reference point for the AD7707’s internal analog circuitry.
16

DRDY

Logic Output. A logic low on this output indicates that a new output word is available from the AD7707 data
register. The DRDY
taken place between output updates, the DRDY line returns high for 500 × t

update. While DRDY

pin returns high upon completion of a read operation of a full output word. If no data read has

cycles prior to the next output

CLK IN

is high, a read operation should neither be attempted nor in progress to avoid reading from
the data register as it is being updated. The DRDY line returns low again when the update has taken place. DRDY
is also used to indicate when the AD7707 has completed its on-chip calibration sequence.

17 DOUT

Serial Data Output with Serial Data Being Read from the Output Shift Register on the Part. This output shift
register can contain information from the setup register, communications register, clock register, or data register,
depending on the register selection bits of the communications register.

Rev. B | Page 10 of 52

AD7707

Pin No. Mnemonic Description

18 DIN

19 DVDD Digital Supply Voltage, 2.7 V to 5.25 V Operation.
20 DGND Ground Reference Point for the AD7707’s Internal Digital Circuitry.

Serial Data Input with Serial Data Being Written to the Input Shift Register on the Part. Data from this input shift
register is transferred to the setup register, clock register, or communications register, depending on the register
selection bits of the communications register.

Rev. B | Page 11 of 52

AD7707

TYPICAL PERFORMANCE CHARACTERISTICS

32,771

32,770

32,769

32,768

VDD = 5V
V

= 2.5V

REF

GAIN = 128
50Hz UPD ATE RATE

TA = 25°C
RMS NOISE = 600nV

400

300

32,767

CODE READ

32,766

32,765

32,764

32,763

0100

200 300 400 500 600 700 800 900 1000

READING NUMBER

Figure 4. Typical Noise Plot at Gain = 128 with 50 Hz Update Rate for Low

Level Input Channel

32,769

10Hz UPDATE RATE, UNBUFFERED MODE
GAIN = 2 (±10V INPUT RANGE)
BIPOLAR MO DE
ANALOG INPUT SET ON CODE TRANSITION

32,768

CODE

32,767

32,766

0

200 400 600 800 1000

READING NUMBER

Figure 5. Typical Noise Plot for AIN3, High Level Input Channel

200

OCCURRENCE

100

08691-004

08691-005

0

32,764

800

10Hz UPDAT E RATE
UNBUFFERED MODE

700

BIPOLAR MODE
GAIN = 2
(±10V INPUT RANGE)

600

500

400

OCCURRENCE

300

200

100

0

32,765 32,766 32,767 32,768 32,769 32,770

Figure 7. Histogram of Data in Figure 4

1

32,767

Figure 8. Histogram of Data in Figure 5

CODE

CODE

2

32,768

08691-007

08691-008

10

9

8

7

6

5

4

RMS NOISE (µV)

3

2

1

0
–10

AVDD= DVDD= 5V
REF IN(+) = 2.5V
REF IN(–) = AGND

TA= 25°C

–6 –2 2 6 10

HIGH LEVEL INPUT CHANNEL
±10V INPUT RANGE
10Hz UPDATE RATE

BUFFERED MODE

UNBUFFERED MODE

AIN3 (V)

08691-006

Figure 6. Typical RMS Noise vs. Analog Input Voltage for High Level Input

Channel, AIN3

Rev. B | Page 12 of 52

0.6
LOW LEV EL INPUT CHANNEL

GAIN = 128
10Hz UPDATE RATE

0.5

0.4

0.3

RMS NOISE (µ V)

0.2

0.1

0
–20

AVDD= DVDD= 5V
REF IN( +) = 2. 5V
REF IN(–) = AGND
T

= +25°C

A

BUFFERED MODE

UNBUFFERED MODE

–5 0 5

INPUT VOLTAG E (mV)

02510101–51–

08691-009

Figure 9. Typical RMS Noise vs. Analog Input Voltage for Low Level Input

Channels, AIN1 and AIN2

AD7707

TEK STOP: SINGLE SEQ 50.0kSPS

V

DD

1

2

OSCILLATOR = 4.9152M Hz

20

16

12

8

MCLK IN = 0V OR V

DD

VDD = 5V

VDD = 3V

TEMPERATURE (°C)

Figure 11. Standby Current vs. Temperature

08691-011

2

CH1 5.00V CH2 2. 00V

OSCILLATOR = 2.4576M Hz

Figure 10. Typical Crystal Oscillator Power-Up Time

5ms/DIV

STANDBY CURRENT (µA)

4

08691-010

0

–40

–30 –20 –10 0 10 20 30 40 50 60 70 80

Rev. B | Page 13 of 52

AD7707

OUTPUT NOISE

OUTPUT NOISE FOR LOW LEVEL INPUT CHANNELS (5 V OPERATION)

Tabl e 7 shows the AD7707 output rms noise and peak-to-peak
resolution in unbuffered mode for the selectable notch and

−3 dB frequencies for the part, as selected by FS0, FS1, and FS2
of the clock register. The numbers given are for the bipolar
input ranges with a V
numbers are typical and are generated at an analog input voltage of
0 V. Tabl e 8 shows the rms noise and peak-to-peak resolution
when operating in buffered mode. It is important to note that
the peak-to-peak numbers represent the resolution for which
there is no code flicker. They are not calculated based on rms
noise but on peak-to-peak noise. The numbers given are for
bipolar input ranges with a V

Table 7. Output RMS Noise/Peak-to-Peak Resolution vs. Gain and Output Update Rate @ 5 V AIN1 and AIN2 Unbuffered Mode Only

Filter First Notch
and Output Data
Rate

MCLK IN = 2.4576 MHz

10 Hz 2.62 Hz 1.2 (16) 0.7 (16) 0.7 (16) 0.54 (16) 0.28 (16) 0.28 (16) 0.28 (15.5) 0.27 (14.5)
50 Hz 13.1 Hz 3.6 (16) 2.1 (16) 1.25 (16) 0.89 (16) 0.62 (16) 0.60 (15.5) 0.56 (14.5) 0.56 (13.5)
60 Hz 15.72 Hz 4.7 (16) 2.6 (16) 1.5 (16) 0.94 (16) 0.73 (16) 0.68 (15.5) 0.66 (14.5) 0.63 (13.5)
250 Hz 65.5 Hz 95 (13) 65 (13) 23.4 (13) 11.6 (13) 6.5 (13) 3.4 (13) 2.1 (12.5) 1.5 (12)
500 Hz 131 Hz 600 (10.5) 316 (10.5) 138 (10.5) 71 (10.5) 38 (10.5) 18 (10.5) 10 (10) 5.7 (10)

MCLK IN = 1 MHz

4.05 Hz 1.06 Hz 1.19 (16) 0.69 (16) 0.71 (16) 0.63 (16) 0.27 (16) 0.27 (16) 0.26 (15.5) 0.24 (15)
20 Hz 5.24 Hz 3.68 (16) 2.18 (16) 1.19 (16) 0.94 (16) 0.6 (16) 0.6 (15.5) 0.56 (14.5) 0.56 (13.5)
25 Hz 6.55 Hz 4.78 (16) 2.66 (16) 1.51 (16) 1.07 (16) 0.7 (16) 0.67 (15.5) 0.66 (14.5) 0.65 (13.5)
100 Hz 26.2 Hz 100 (13) 50.1 (13) 23.5 (13) 11.9 (13) 5.83 (13) 3.64 (13) 2.16 (12.5) 1.5 (12)
200 Hz 52.5 Hz 543 (10.5) 318 (10.5) 132 (10.5) 68.1 (10.5) 33.1 (10.5) 17.6 (10.5) 9.26 (10.5) 6.13 (10)

of 2.5 V and AVDD = 5 V. These

REF

of 2.5 V. These numbers are

REF

−3 dB
Frequency

Gain of 1 Gain of 2 Gain of 4 Gain of 8 Gain of 16 Gain of 32 Gain of 64 Gain of 128

Typical Output RMS Noise in μV (Peak-to-Peak Resolution in Bits)

typical and are rounded to the nearest LSB. The numbers apply
for the CLKDIV bit of the clock register set to 0. The output
noise comes from two sources. The first is the electrical noise in
the semiconductor devices (device noise) used in the
implementation of the modulator. Secondly, when the analog
input is converted into the digital domain, quantization noise is
added. The device noise is at a low level and is independent of
frequency. The quantization noise starts at an even lower level
but rises rapidly with increasing frequency to become the
dominant noise source. The numbers in Tabl e 7 and Ta b le 8

are

given for the bipolar input ranges. For the unipolar ranges, the
rms noise numbers are the same as the bipolar range but the
peak-to-peak resolution is now based on half the signal range,
which effectively means losing one bit of resolution.

Table 8. Output RMS Noise/Peak-to-Peak Resolution vs. Gain and Output Update Rate @ 5 V AIN1 and AIN2 Buffered Mode Only

Filter First Notch
and Output Data
Rate

MCLK IN = 2.4576 MHz

10 Hz 2.62 Hz 1.47 (16) 0.95 (16) 0.88 (16) 0.55 (16) 0.42 (16) 0.42 (16) 0.42 (15) 0.41 (14)
50 Hz 13.1 Hz 4.2 (16) 2.6 (16) 1.6 (16) 1 (16) 0.89 (15.5) 0.94 (15) 0.9 (14) 0.9 (13)
60 Hz 15.72 Hz 4.9 (16) 3 (16) 1.8 (16) 1.1 (16) 1 (15.5) 1 (14.5) 0.94 (14) 0.94 (13)
250 Hz 65.5 Hz 104 (13) 52 (13) 26 (13) 14 (13) 6.5 (13) 4.1 (12.5) 2.7 (12.5) 2.3 (11.5)
500 Hz 131 Hz 572 (10.5) 293 (10.5) 125 (10.5) 69 (10.5) 40 (10.5) 19 (10.5) 10 (10.5) 5.9 (10)

MCLK IN = 1 MHz

4.05 Hz 1.06 Hz 1.48 (16) 8.95 (16) 0.87 (16) 0.67 (16) 0.41 (16) 0.40 (16) 0.40 (15) 0.40 (14)
20 Hz 5.24 Hz 3.9 (16) 2.46 (16) 1.77 (16) 1.19 (16) 0.94 (16) 0.93 (15) 0.95 (14) 0.9 (13)
25 Hz 6.55 Hz 5.37 (16) 3.05 (16) 1.89 (16) 1.33 (16) 1.11 (15.5) 1.06 (14.5) 1.04 (13.5) 1.02 (12.5)
100 Hz 26.2 Hz 98.9 (13) 52.4 (13) 26.1 (13) 12.7 (13) 6.08 (13) 4.01 (12.5) 2.62 (12.5) 2.33 (11.5)
200 Hz 52.4 Hz 596 (10.5) 298 (10.5) 133 (10.5) 69.3 (10.5) 34.7 (10.5) 16.9 (10.5) 9.67 (10.5) 6.34 (10)

−3 dB
Frequency

Gain of 1 Gain of 2 Gain of 4 Gain of 8 Gain of 16 Gain of 32 Gain of 64 Gain of 128

Typical Output RMS /oise in μV (Peak-to-Peak Resolution in Bits)

Rev. B | Page 14 of 52

AD7707

OUTPUT NOISE FOR LOW LEVEL INPUT CHANNELS (3 V OPERATION)

Table 9 shows the AD7707 output rms noise and peak-to-peak
resolution in unbuffered mode for the selectable notch and

−3 dB frequencies for the part, as selected by FS0, FS1, and FS2
of the clock register. The numbers given are for the bipolar
input ranges with a V
numbers are typical and are generated at an analog input
voltage of 0 V. Table 10 shows the rms noise and peak-to-peak
resolution when operating in buffered mode. It is important to
note that the peak-to-peak numbers represent the resolution for
which there is no code flicker. They are not calculated based on
rms noise but on peak-to-peak noise. The numbers given are
for bipolar input ranges with a V
buffered or unbuffered mode. These numbers are typical and

Table 9. Output RMS Noise/Peak-to-Peak Resolution vs. Gain and Output Update Rate @ 3 V AIN1 and AIN2 Unbuffered Mode Only

Filter First Notch
and Output Data
Rate

MCLK IN = 2.4576 MHz

10 Hz 2.62 Hz 1.60 (16) 0.8 (16) 0.48 (16) 0.29 (16) 0.29 (16) 0.27 (15.5) 0.26 (14.5) 0.26 (13.5)
50 Hz 13.1 Hz 3.8 (16) 1.9 (16) 1.1 (16) 0.64 (16) 0.60 (15.5) 0.6 (14.5) 0.6 (13.5) 0.6 (12.5)
60 Hz 15.72 Hz 4.4 (16) 2.2 (16) 1.35 (16) 0.78 (16) 0.7 (15) 0.68 (14.5) 0.64 (13.5) 0.64 (12.5)
250 Hz 65.5 Hz 53 (13) 24 (13) 15 (13) 6.8 (13) 3.6 (12.5) 2.1 (12.5) 1.5 (12) 1.3 (11)
500 Hz 131 Hz 300 (10.5) 138 (10.5) 80 (10.5) 34 (10.5) 18 (10.5) 8.7 (10.5) 4.8 (10) 3.4 (10)

MCLK IN = 1 MHz

4.05 Hz 1.06 Hz 1.56 (16) 0.88 (16) 0.52 (16) 0.3 (16) 0.28 (16) 0.27 (15.5) 0.27 (14.5) 0.26 (13.5)
20 Hz 5.24 Hz 3.85 (16) 2.02 (16) 1.15 (16) 0.74 (16) 0.63 (15.5) 0.57 (14.5) 0.61 (13.5) 0.58 (12.5)
25 Hz 6.55 Hz 4.56 (16) 2.4 (16) 1.4 (16) 0.79 (16) 0.68 (15) 0.66 (14.5) 0.64 (13.5) 0.64 (12.5)
100 Hz 26.2 Hz 45.7 (13) 22 (13) 13.7 (13) 5.27 (13) 2.64 (13) 2 (12.5) 1.59 (12) 1.4 (11)
200 Hz 52.4 Hz 262 (10.5) 125 (10.5) 66 (10.5) 32.4 (10.5) 18.4 (10.5) 8.6 (10.5) 4.64 (10.5) 3.3 (10)

of 1.225 V and an AVDD = 3 V. These

REF

of 1.225 V and for either

REF

−3 dB
Frequency

Gain of 1 Gain of 2 Gain of 4 Gain of 8 Gain of 16 Gain of 32 Gain of 64 Gain of 128

Typical Output RMS Noise in μV (Peak-to-Peak Resolution in Bits)

are rounded to the nearest LSB. The numbers apply for the
CLKDIV bit of the clock register set to 0. The output noise
comes from two sources. The first is the electrical noise in the
semiconductor devices (device noise) used in the implementa­tion of the modulator. Secondly, when the analog input is
converted into the digital domain, quantization noise is added.
The device noise is at a low level and is independent of fre­quency. The quantization noise starts at an even lower level but
rises rapidly with increasing frequency to become the dominant
noise source. The numbers in Table 9 and Table 10 are given
for the bipolar input ranges. For the unipolar ranges, the rms
noise numbers are the same as the bipolar range but the peak­to-peak resolution is now based on half the signal range, which
effectively means losing 1 bit of resolution.

Table 10. Output RMS Noise/Peak-to-Peak Resolution vs. Gain and Output Update Rate @ 3 V AIN1 and AIN2 Buffered Mode Only

Filter First Notch
and Output Data
Rate

MCLK IN = 2.4576 MHz

10 Hz 2.62 Hz 1.80 (16) 1 (16) 0.7 (16) 0.41 (16) 0.41 (16) 0.41 (15) 0.41 (14) 0.41 (13)
50 Hz 13.1 Hz 4.1 (16) 2.4 (16) 1.5 (16) 1 (15.5) 0.91 (15) 0.89 (14) 0.86 (13) 0.83 (12)
60 Hz 15.72 Hz 5.1 (16) 3 (16) 1.8 (16) 1.1 (15.5) 0.94 (14.5) 0.94 (13.5) 0.99 (13) 0.99 (11.5)
250 Hz 65.5 Hz 50 (13) 27 (13) 12.3 (13) 6.4 (13) 4 (12.5) 2.7 (12.5) 2.2 (11.5) 1.8 (11)
500 Hz 131 Hz 275 (10.5) 125 (10.5) 80 (10.5) 39 (10.5) 16 (10.5) 8.9 (10.5) 5.2 (10) 4.2 (9.5)

MCLK IN = 1 MHz

4.05 Hz 1.06 Hz 1.75 (16) 1.18 (16) 0.67 (16) 0.44 (16) 0.41 (16) 0.44 (15) 0.43 (14) 0.43 (13)
20 Hz 5.24 Hz 4.21 (16) 2.5 (16) 1.48 (16) 1 (15.5) 0.94 (15) 0.96 (14) 0.89 (13) 0.86 (12)
25 Hz 6.55 Hz 5.15 (16) 2.8 (16) 1.8 (16) 1.15 (15.5) 1 (14.5) 1.02 (13.5) 0.96 (13) 1.03 (11.5)
100 Hz 26.2 Hz 46.1 (13) 24.3 (13) 13.6 (13) 6.71 (13) 4.1 (12.5) 2.54 (12.5) 2.3 (11.5) 2.15 (10.5)
200 Hz 52.4 Hz 282 (10.5) 123 (10.5) 66 (10.5) 35.3 (10.5) 14.8 (10.5) 9.91 (10.5) 5.48 (10) 4.01 (9.5)

−3 dB
Frequency

Gain of 1 Gain of 2 Gain of 4 Gain of 8 Gain of 16 Gain of 32 Gain of 64 Gain of 128

Typical Output RMS Noise in μV (Peak-to-Peak Resolution in Bits)

Rev. B | Page 15 of 52

AD7707

OUTPUT NOISE FOR HIGH LEVEL INPUT CHANNEL AIN3 (5 V OPERATION)

Table 11 shows the AD7707 output rms noise and peak-to-peak
resolution in unbuffered mode for the selectable notch and −3 dB
frequencies for the part, as selected by FS0, FS1, and FS2 of the
clock register. The numbers given are for the ±10 V, ±5 V, 0 to
5 V and 0 V to 10 V ranges with a V
HICOM = AGND, and AV

= 5 V. These numbers are typical

DD

and are generated at an analog input voltage of 0 V. Table 12
meanwhile shows the output rms noise and peak-to-peak
resolution in buffered mode. It is important to note that these
numbers represent the resolution for which there is no code
flicker. They are not calculated based on rms noise, but on
peak-to-peak noise. Operating the high level channel with a
gain of 2 in bipolar mode gives an operating range of ±10 V.
Operating at a gain of 2 in unipolar mode gives a range of 0 V
to +10 V. Operating the high level channel with a gain of 4 in

Table 11. Output RMS Noise/Peak-to-Peak Resolution vs. Gain and Output Update Rate @ 5 V AIN3 Unbuffered Mode Only

Filter First Notch
and Output Data
Rate

MCLK IN = 2.4576 MHz

10 Hz 2.62 Hz 5.10 16 3.52 16 5.10 16 3.52 16
50 Hz 13.1 Hz 15.82 16 9.77 16 15.82 16 9.77 16
60 Hz 15.72 Hz 20.36 16 12.29 16 20.36 16 12.29 16
250 Hz 65.5 Hz 430 13 212 13 430 12 212 12
500 Hz 131 Hz 2350 10 1287 10 2350 9 1287 9

MCLK IN = 1 MHz

4.05 Hz 1.06 Hz 5.13 16 3.53 16 5.13 16 3.53 16
20 Hz 5.24 Hz 18.9 16 13.25 16 18.9 16 13.25 16
25 Hz 6.55 Hz 23.7 16 15.3 16 23.7 16 15.3 15.5
100 Hz 26.2 Hz 406 13 174 13 406 12 174 12
200 Hz 52.4 Hz 2184 10.5 1144 10.5 2184 9.5 1144 9.5

−3 dB
Frequency

of 2.5 V, VBIAS = 2.5 V,

REF

±10 V Range ±5 V Range 0 V to 10 V Range 0 V to 5 V Range

RMS Noise
(μV)

P-P (Bits)
Resolution

RMS Noise
(μV)

bipolar mode gives the ±5 V operating range. Operating at a gain
of 4 in unipolar mode gives an operating range of 0 V to 5 V.
Noise for all input ranges is shown in Output Noise For High Level
Input Channel, AIN3 section. The output noise comes from two
sources. The first is the electrical noise in the semiconductor
devices (device noise) used in the implementation of the modula­tor. Secondly, when the analog input is converted into the digital
domain, quantization noise is added. The device noise is at a low
level and is independent of frequency. The quantization noise
starts at an even lower level but rises rapidly with increasing
frequency to become the dominant noise source. The numbers
in Table 11 and Table 12 are given for the bipolar input ranges.
For the unipolar ranges the rms noise numbers are the same as
the bipolar range, but the peak-to-peak resolution is now based
on half the signal range, which effectively means losing 1 bit of
resolution.

P-P (Bits)
Resolution

RMS Noise
(μV)

P-P (Bits)
Resolution

RMS
Noise (μV)

P-P (Bits)
Resolution

Table 12. Output RMS Noise/Peak-to-Peak Resolution vs. Gain and Output Update Rate @ 5 V AIN3 Buffered Mode Only

Filter First Notch
and Output Data
Rate

MCLK IN = 2.4576 MHz

10 Hz 2.62 Hz 7.4 16 5.2 16 7.4 16 5.2 16
50 Hz 13.1 Hz 22.2 16 14.3 16 22.2 16 14.3 16
60 Hz 15.72 Hz 26.6 16 15.85 16 26.6 16 15.85 16
250 Hz 65.5 Hz 475 13 187 13 475 12 187 12
500 Hz 131 Hz 2423 10.5 1097 10.5 2423 9.5 1097 9.5

MCLK IN = 1 MHz

4.05 Hz 1.06 Hz 7.63 16 5.45 16 7.63 16 5.45 16
20 Hz 5.24 Hz 20.25 16 13.3 16 20.25 16 13.3 16
25 Hz 6.55 Hz 23.5 16 14.6 16 23.5 16 14.6 15.5
100 Hz 26.2 Hz 377 13 210 13 377 12 210 12
200 Hz 52.4 Hz 2226 10.5 1132 10.5 2226 9.5 1132 9.5

−3 dB
Frequency

±10 V Range ±5 V Range 0 V to 10 V Range 0 to 5 V Range

RMS Noise P-P (Bits) RMS Noise P-P (Bits) RMS Noise P-P (Bits) RMS Noise P-P (Bits)
(μV) Resolution (μV) Resolution (μV) Resolution (μV) Resolution

Rev. B | Page 16 of 52