Page 1
16-Bit, 100 kSPS, Single-Ended
V
Data Sheet
FEATURES
16-bit resolution with no missing codes
Throughput: 100 kSPS
INL: ±1 LSB typical, ±3 LSB maximum
Pseudo differential analog input range
0 V to V
Single-supply operation: 2.7 V to 5.5 V
Serial interface SPI/QSPI/MICROWIRE/DSP compatible
Power dissipation: 4 mW @ 5 V, 1.5 mW @ 2.7 V,
Standby current: 1 nA
8-lead packages:
Improved second source to ADS8320 and ADS8325
APPLICATIONS
Battery-powered equipment
Data acquisition
Instrumentation
Medical instruments
Process control
GENERAL DESCRIPTION
The AD7683 is a 16-bit, charge redistribution, successive
approximation, PulSAR® analog-to-digital converter (ADC)
that operates from a single power supply, VDD, between 2.7 V
and 5.5 V. It contains a low power, high speed, 16-bit sampling
ADC with no missing codes (B grade), an internal conversion
clock, and a serial, SPI-compatible interface port. The part also
contains a low noise, wide bandwidth, short aperture delay,
track-and-hold circuit. On the
with V
REF
up to VDD
REF
150 μW @ 2.7 V/10 kSPS
MSOP
3 mm × 3 mm QFN (LFCSP) (SOT-23 size)
CS
falling edge, it samples an
PulSAR ADC in MSOP/QFN
AD7683
APPLICATION DIAGRAM
0.5V TO VDD 2.7V TO 5.5
REF
0V TO V
REF
+IN
–IN
Table 1. MSOP, QFN (LFCSP)/SOT-23, 14-/16-/18-Bit
PulSAR ADC
Type
18-Bit True
Differential
16-Bit True
Differential
16-Bit
Pseudo
Differential
14-Bit
Pseudo
Differential
100
kSPS
AD7691 AD7690 AD7982
AD7684 AD7687 AD7688
AD7680
AD7683
AD7940 AD7942 AD7946 ADA4841-1
250
kSPS
AD7685
AD7694
analog input, +IN, between 0 V to REF with respect to a ground
sense, –IN. The reference voltage, REF, is applied externally and
can be set up to the supply voltage. Its power scales linearly with
throughput.
The AD7683 is housed in an 8-lead MSOP or an 8-lead QFN
(LFCSP) package, with an operating temperature specified from
−40°C to +85°C.
VDD
DCLOCK
AD7683
GND
Figure 1.
D
OUT
CS
400 kSPS
to
500 kSPS
AD7693
AD7686 AD7980 ADA4841-1
3-WIRE SPI
INTERFACE
≥1000
kSPS
AD7984
ADA4941-1
ADC
Driver
ADA4941-1
ADA4841-1
ADA4841-1
04301-001
Rev. B Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2004–2016 Analog Devices, Inc. All rights reserved.
Technical Support www.analog.com
Page 2
AD7683 Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
Application Diagram ........................................................................ 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
Timing Specifications .................................................................. 5
Absolute Maximum Ratings ............................................................ 6
Thermal Resistance ...................................................................... 6
ESD Caution .................................................................................. 6
Pin Configurations and Function Descriptions ........................... 7
Terminolog y ...................................................................................... 8
Typical Performance Characteristics ............................................. 9
Applications Information .............................................................. 12
Circuit Information .................................................................... 12
Converter Operation .................................................................. 12
Transfer Functions ..................................................................... 12
Typical Connection Diagram ................................................... 13
Analog Input ............................................................................... 13
Driver Amplifier Choice ........................................................... 13
Voltage Reference Input ............................................................ 14
Power Supply ............................................................................... 14
Digital Interface .......................................................................... 14
Layout .......................................................................................... 14
Evaluating the AD7683 Performance ...................................... 14
Outline Dimensions ....................................................................... 15
Ordering Guide .......................................................................... 16
REVISION HISTORY
2/16—Rev. A to Rev. B
Changes to Table 1 ............................................................................ 1
Added Figure 7 and Table 9; Renumbered Sequentially ............. 7
Changes to Table 10 ........................................................................ 13
Changes to Digital Interface Section ............................................ 14
Updated Outline Dimensions ....................................................... 16
Changes to Ordering Guide .......................................................... 16
2/08—Rev. 0 to Rev. A
Change to Title .................................................................................. 1
Moved Figure 3, Figure 4, and Figure 5 ......................................... 5
Changes to Figure 4 .......................................................................... 5
Moved Figure 17 and Figure 18 .................................................... 11
Changes to Figure 22 ...................................................................... 13
Updated Outline Dimensions ....................................................... 15
Changes to Ordering Guide .......................................................... 16
9/04—Initial Version: Revision 0
Rev. B | Page 2 of 16
Page 3
Data Sheet AD7683
VDD
VDD = 5 V
800 µA
VDD = 2.7 V, 10 kSPS throughput2
150 µW
SPECIFICATIONS
VDD = 2.7 V to 5.5 V; V
Table 2.
Parameter Conditions
RESOLUTION 16 Bits
ANALOG INPUT
Voltage Range +IN − (–IN) 0 V
Absolute Input Voltage +IN −0.1 VDD + 0.1 V
−IN −0.1 0.1 V
Analog Input CMRR fIN = 100 kHz 65 dB
Leakage Current at 25°C Acquisition phase 1 nA
Input Impedance See the Analog Input section
THROUGHPUT SPEED
Complete Cycle 10 µs
Throughput Rate 0 100 kSPS
DCLOCK Frequency 0 2.9 MHz
REFERENCE
Voltage Range 0.5 VDD + 0.3 V
Load Current 100 kSPS, V
DIGITAL INPUTS
Logic Levels
VIL −0.3 0.3 × VDD V
VIH 0.7 × VDD VDD + 0.3 V
IIL −1 +1 µA
IIH −1 +1 µA
Input Capacitance 5 pF
DIGITAL OUTPUTS
Data Format Serial, 16 bits straight binary
VOH I
VOL I
POWER SUPPLIES
VDD Specified performance 2.7 5.5 V
VDD Range1 2.0 5.5 V
Operating Current 100 kSPS throughput
= VDD; TA = –40°C to +85°C, unless otherwise noted.
REF
− V
= V
+IN
−IN
= −500 µA VDD − 0.3 V
SOURCE
= +500 µA 0.4 V
SINK
/2 = 2.5 V 50 µA
REF
AD7683 All Grades
REF
Unit Min Typ Max
V
VDD = 2.7 V 560 µA
Standby Current
Power Dissipation VDD = 5 V 4 6 mW
VDD = 2.7 V 1.5 mW
TEMPERATURE RANGE
Specified Performance T
1
See the Typical Performance Characteristics section for more information.
2
With all digital inputs forced to VDD or GND, as required.
3
During acquisition phase.
2, 3
VDD = 5 V, 25°C 1 50 nA
to T
MIN
−40 +85 °C
MAX
Rev. B | Page 3 of 16
Page 4
AD7683 Data Sheet
Gain Error1, T
to T
±2
±24 ±2
±15
LSB
Power Supply Sensitivity
±0.05
±0.05
LSB
Signal-to-Noise
fIN = 1 kHz
85
86 dB2
VDD = 5 V; V
Table 3.
Parameter Conditions
ACCURACY
No Missing Codes 15 16 Bits
Integral Linearity Error −6 ±3 +6 −3 ±1 +3 LSB
Transition Noise 0.5 0.5 LSB
Gain Error Temperature Drift ±0.3 ±0.3 ppm/°C
Offset Error1, T
Offset Temperature Drift ±0.3 ±0.3 ppm/°C
Power Supply Sensitivity
AC ACCURACY
Signal-to-Noise fIN = 1 kHz 90 88 91 dB2
Spurious-Free Dynamic Range fIN = 1 kHz −100 −108 dB
Total Harmonic Distortion fIN = 1 kHz −100 −106 dB
Signal-to-(Noise + Distortion) fIN = 1 kHz 90 88 91 dB
Effective Number of Bits fIN = 1 kHz 14.7 14.8 Bits
1
See the Terminology section. These specifications include full temperature range variation but do not include the error contribution from the external reference.
2
All specifications in dB are referred to a full-scale input, FS. Tested with an input signal at 0.5 dB below full scale, unless otherwise specified.
VDD = 2.7 V; V
= VDD; TA = –40°C to +85°C, unless otherwise noted.
REF
MIN
MAX
to T
MIN
±0.7 ±1.6 ±0.4 ±1.6 mV
MAX
VDD = 5 V ± 5%
= 2.5V; TA = –40°C to +85°C, unless otherwise noted.
REF
A Grade B Grade
Unit Min Typ Max Min Ty p Max
±0.05 ±0.05 LSB
Table 4.
A Grade B Grade
Parameter Conditions Min Typ Max Min Ty p Max Unit
ACCURACY
No Missing Codes 15 16 Bits
Integral Linearity Error −6 ±3 +6 −3 ±1 +3 LSB
Transition Noise 0.85 0.85 LSB
Gain Error1, T
MIN
to T
±2 ±30 ±2 ±15 LSB
MAX
Gain Error Temperature Drift ±0.3 ±0.3 ppm/°C
Offset Error1, T
MIN
to T
±0.7 ±3.5 ±0.7 ±3.5 mV
MAX
Offset Temperature Drift ±0.3 ±0.3 ppm/°C
VDD = 2.7 V ±5%
AC ACCURACY
Spurious-Free Dynamic Range fIN = 1 kHz −96 −100 dB
Total Harmonic Distortion fIN = 1 kHz −94 −98 dB
Signal-to-(Noise + Distortion) fIN = 1 kHz 85 86 dB
Effective Number of Bits fIN = 1 kHz 13.8 14 Bits
1
See the Terminology section. These specifications do include full temperature range variation but do not include the error contribution from the external reference.
2
All specifications in dB are referred to a full-scale input FS. Tested with an input signal at 0.5 dB below full scale, unless otherwise specified.
Rev. B | Page 4 of 16
Page 5
Data Sheet AD7683
T
TIMING SPECIFICATIONS
VDD = 2.7 V to 5.5 V; TA = −40°C to +85°C, unless otherwise noted.
Table 5.
Parameter Symbol Min Typ Max Unit
Throughput Rate t
CS Falling to DCLOCK Low
CS Falling to DCLOCK Rising
DCLOCK Falling to Data Remains Valid t
CS Rising Edge to D
High Impedance
OUT
DCLOCK Falling to Data Valid tEN 16 50 ns
Acquisition Time t
D
Fall Time tF 11 25 ns
OUT
D
Rise Time tR 11 25 ns
OUT
Timing and Circuit Diagrams
t
CYC
CS
t
SUCS
DCLOCK
D
OUT
145
t
CSD
HIGH-Z
NOTES
1. A MINIMUM OF 22 CLOCK CYCLES ARE REQUI RED FOR 16-BIT CONVERSIO N. SHOWN ARE 24 CLOCK CYCLES.
GOES LO W ON THE DCLO CK FALLING EDGE FO LLOWING THE LS B READING.
D
OUT
t
EN
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
0
(MSB) (LSB)
COMPLETE CYCLE
t
HDO
Figure 2. Serial Interface Timing
100 kHz
CYC
t
0 μs
CSD
t
20 ns
SUCS
5 16 ns
HDO
t
14 100 ns
DIS
400 ns
ACQ
t
ACQ
POWER DOW N
t
DIS
HIGH-Z
0
04301-002
O D
OUT
100pF
C
L
500µA I
500µA I
OL
1.4V
OH
04301-003
Figure 3. Load Circuit for Digital Interface Timing
0.8V
t
EN
2V
Figure 4. Voltage Reference Levels for Timing
2V
t
EN
2V
0.8V0.8V
04301-004
D
OUT
t
R
Figure 5. D
Rise and Fall Timing
OUT
t
F
90%
10%
04301-006
Rev. B | Page 5 of 16
Page 6
AD7683 Data Sheet
+IN1, –IN1
GND − 0.3 V to VDD + 0.3 V or
Digital Outputs to GND
−0.3 V to VDD + 0.3 V
ABSOLUTE MAXIMUM RATINGS
Table 6.
Parameter Rating
Analog Inputs
±130 mA
REF GND − 0.3 V to VDD + 0.3 V
Supply Voltages
VDD to GND −0.3 V to +6 V
Digital Inputs to GND −0.3 V to VDD + 0.3 V
Storage Temperature Range −65°C to +150°C
Junction Temperature 150°C
Lead Temperature Range JEDEC J-STD-20
Vapor Phase (60 sec) 215°C
Infrared (15 sec) 220°C
1
See the Analog Input section.
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
THERMAL RESISTANCE
Table 7. Thermal Resistance
Package Type θJA θJC Unit
8-Lead MSOP 200 44 °C/W
ESD CAUTION
Rev. B | Page 6 of 16
Page 7
Data Sheet AD7683
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
REF
1
AD7683
2
+IN
TOP VIEW
–IN
3
(Not to Scale)
4
GND
Figure 6. 8-Lead MSOP Pin Configuration
Table 8. 8-Lead MSOP Pin Function Descriptions
Pin No. Mnemonic Type1 Function
1 REF AI
Reference Input Voltage. The REF range is from 0.5 V to VDD. It is referred to the GND pin. Decouple the
REF pin closely to the GND pin with a ceramic capacitor of a few μF.
2 +IN AI
Analog Input. It is referred to Pin –IN. The voltage range, that is, the difference between +IN and –IN, is 0 V
.
to V
REF
3 –IN AI Analog Input Ground Sense. Connect this pin to either the analog ground plane or a remote sense ground.
4 GND P Power Supply Ground.
5
CS
DI
Chip Select Input. On its falling edge, it initiates the conversions. The part returns to shutdown mode as
soon as the conversion is completed. It also enables D
6 D
DO Serial Data Output. The conversion result is output on this pin. It is synchronized to DCLOCK.
OUT
7 DCLOCK DI Serial Data Clock Input.
8 VDD P Power Supply.
1
AI = analog input; DI = digital input; DO = digital output; and P = power.
VDD
8
7
DCLOCK
D
6
5
CS
OUT
04301-005
OUT
. When high, D
is high impedance.
OUT
1REF
2+IN
AD7683
TOP VIEW
3–IN
(Not to Scale)
4GND
NOTES
1. EXPOSED PAD. CONNECT THE EXPOSED PAD TO GND. THIS CONNECTION
IS NOT REQUIRED TO MEET SPECIFIED ELECTRICAL PERFORMANCE.
8VDD
7 DCLOCK
6D
OUT
5CS
04301-107
Figure 7. 8-Lead QFN (LFCSP) Pin Configuration
Table 9. 8-Lead QFN (LFCSP) Pin Function Descriptions
Pin No. Mnemonic Type1 Function
1 REF AI
Reference Input Voltage. The REF range is from 0.5 V to VDD. It is referred to the GND pin. Decouple the
REF pin closely to the GND pin with a ceramic capacitor of a few μF.
2 +IN AI
Analog Input. It is referred to Pin –IN. The voltage range, that is, the difference between +IN and –IN, is 0 V
.
to V
REF
3 –IN AI Analog Input Ground Sense. Connect this pin to either the analog ground plane or a remote sense ground.
4 GND P Power Supply Ground.
5
6 D
CS
DO Serial Data Output. The conversion result is output on this pin. It is synchronized to DCLOCK.
OUT
DI
Chip Select Input. On its falling edge, it initiates the conversions. The part returns to shutdown mode as
soon as the conversion is completed. It also enables D
. When high, D
OUT
is high impedance.
OUT
7 DCLOCK DI Serial Data Clock Input.
8 VDD P Power Supply.
EPAD
Exposed Pad. Connect the exposed pad to GND. This connection is not required to meet specified
electrical performance.
1
AI = analog input; DI = digital input; DO = digital output; and P = power.
Rev. B | Page 7 of 16
Page 8
AD7683 Data Sheet
[
]
( )
02.6/76.1/ −+=
dB
DNSENOB
TERMINOLOGY
Integral Nonlinearity Error (INL)
Linearity error refers to the deviation of each individual code
from a line drawn from negative full scale through positive
full scale. The point used as negative full scale occurs ½ LSB
before the first code transition. Positive full scale is defined as
a level 1½ LSB beyond the last code transition. The deviation
is measured from the middle of each code to the true straight
line (see Figure 22).
Differential Nonlinearity Error (DNL)
In an ideal ADC, code transitions are 1 LSB apart. DNL is the
maximum deviation from this ideal value. It is often specified in
terms of resolution for which no missing codes are guaranteed.
Offset Error
The first transition should occur at a level ½ LSB above analog
ground (38.1 µV for the 0 V to 5 V range). The offset error is
the deviation of the actual transition from that point.
Gain Error
The last transition (from 111...10 to 111...11) should occur for
an analog voltage 1½ LSB below the nominal full scale
(4.999886 V for the 0 V to 5 V range). The gain error is the
deviation of the actual level of the last transition from the ideal
level after the offset has been adjusted out.
Spurious-Free Dynamic Range (SFDR)
The difference, in decibels (dB), between the rms amplitude of
the input signal and the peak spurious signal.
Signal-to-(Noise + Distortion) Ratio (SINAD)
SINAD is the ratio of the rms value of the actual input signal to
the rms sum of all other spectral components below the Nyquist
frequency, including harmonics but excluding dc. The value for
SINAD is expressed in dB.
Effective Number of Bits (ENOB)
ENOB is a measurement of the resolution with a sine wave
input. It is related to SINAD (as represented by S/(N+D)) by
the following formula and is expressed in bits:
Total Harmonic Distortion (THD)
THD is the ratio of the rms sum of the first five harmonic
components to the rms value of a full-scale input signal and is
expressed in dB.
Signal-to-Noise Ratio (SNR)
SNR is the ratio of the rms value of the actual input signal to
the rms sum of all other spectral components below the Nyquist
frequency, excluding harmonics and dc. The value for SNR is
expressed in dB.
Aperture Delay
Aperture delay is a measure of the acquisition performance and
is the time between the falling edge of the
the input signal is held for a conversion.
Transient Response
Transient response is the time required for the ADC to
accurately acquire its input after a full-scale step function is
applied.
input and when
CS
Rev. B | Page 8 of 16
Page 9
Data Sheet AD7683
TYPICAL PERFORMANCE CHARACTERISTICS
3
2
POSITIVE INL = +0.43LSB
NEGATI VE INL = –0. 97LSB
3
2
POSITIVE DNL = +0.43LSB
NEGATIVE DNL = –0. 41LSB
1
0
INL (LSB)
–1
–2
–3
0 16384 32768 49152 65536
CODE
Figure 8. Integral Nonlinearity vs. Code
7000
6000
5000
4000
3000
COUNTS
2000
1000
001
0
79FD79FE79FF7A007A017A027A037A047A057A067A077A08
50
62564
25440
2755
CODE IN HEX
VDD = REF = 2.5V
35528
4604
130
00
Figure 9. Histogram of a DC Input at the Code Center
0
–20
–40
–60
–80
–100
–120
–140
AMPLITUDE (dB OF FULL SCALE)
–160
–180
0 1020304050
FREQUENCY (kHz)
16384 POINT FFT
VDD = REF = 5V
f
= 100kSPS
S
f
= 20.43kHz
IN
SNR = 92.7dB
THD = –105.7d B
SFDR = –106.4d B
Figure 10. FFT Plot
1
0
DNL (LSB)
–1
–2
04301-012
–3
0 16384 32768 49152 65536
CODE
04301-011
Figure 11. Differential Nonlinearity vs. Code
120000
100000
80000
60000
COUNTS
40000
20000
04301-009
006 00
0
7A0E 7A0F 7A10 7A 11 7A12 7A13 7A14 7A15 7A16
102287
15152
CODE IN HEX
VDD = REF = 5V
13619
8
04301-010
Figure 12. Histogram of a DC Input at the Code Center
0
–20
–40
–60
–80
–100
–120
–140
AMPLITUDE (dB OF FULL SCALE)
–160
04301-008
–180
0 1020304050
FREQUENCY (kHz)
16384 POINT F FT
VDD = REF = 2.5V
f
= 100kSPS
S
f
= 20.43kHz
IN
SNR = 88.7dB
THD = –102.6dB
SFDR = –104.6d B
04301-007
Figure 13. FFT Plot
Rev. B | Page 9 of 16
Page 10
AD7683 Data Sheet
–
100
17
80
95
90
SNR, SINAD (d B)
85
80
2.0 5.55.04.54.03.53.02.5
REFERENCE VOLTAGE (V)
SNR
SINAD
ENOB
Figure 14. SNR, SINAD, and ENOB vs. Reference Voltage
100
95
90
85
SINAD (dB)
80
75
= 2.5V, –1dB
V
REF
V
REF
V
= 5V, –10dB
= 5V, –1dB
REF
–85
16
–90
15
ENOB (Bits)
14
04301-013
13
–95
THD (dB)
–100
–105
–110
0200120 1608040
V
2.5V = –1dB
REF
5V = –1dB
V
REF
FREQUENCY (kHz)
04301-015
Figure 16. THD vs. Frequency
1200
f
= 100kSPS
S
1000
800
600
400
OPERATING CURRENT (µA)
200
70
0 20015010050
FREQUENCY (kHz)
Figure 15. SINAD vs. Frequency
04301-014
0
2.0 5.55.04.54.03.53.02.5
SUPPLY (V)
04301-017
Figure 17. Operating Current vs. Supply
Rev. B | Page 10 of 16
Page 11
Data Sheet AD7683
900
VDD = 5V,
800
700
600
500
400
300
OPERATING CURRENT (µA)
200
100
0
–55 –34 –15 5 25 45 65 85 105 125
f
= 100kSPS
S
TEMPERATURE (°C)
VDD = 2.7V,
f
= 100kSPS
S
04301-018
Figure 18. Operating Current vs. Temperature
1000
750
500
250
POWER-DOW N CURRENT (nA)
0
–55 –35 –15 5 25 45 65 85 105 125
TEMPERATURE (°C)
Figure 19. Power-Down Current vs. Temperature
04301-019
6
5
4
3
2
1
0
–1
–2
–3
OFFSET, GAIN ERROR (LSB)
–4
–5
–6
–55 –35 –15 5 25 45 65 85 105 125
TEMPERATURE (°C)
OFFSET ERROR
GAIN ERROR
Figure 20. Offset and Gain Error vs. Temperature
04301-016
Rev. B | Page 11 of 16
Page 12
AD7683 Data Sheet
SW+MSB
16,384C
+IN
LSB
COMP
CONTROL
LOGIC
SWITCHES CONTROL
BUSY
OUTPUT CODE
CNV
REF
GND
–IN
4C 2C C C32,768C
SW–MSB
16,384C
LSB
4C 2C C C32,768C
04301-020
000...000
000...001
000...010
111...101
111...110
111...111
ADC CODE (STRAI GHT BINARY)
ANALOG INP UT
+FS – 1.5 LS B
+
FS – 1 LSB
–FS + 1 LSB
–FS
–FS + 0.5 LS B
04301-021
APPLICATIONS INFORMATION
CIRCUIT INFORMATION
The AD7683 is a low power, single-supply, 16-bit ADC using a
successive approximation architecture.
The AD7683 is capable of converting 100,000 samples per
second (100 kSPS) and powers down between conversions.
When operating at 10 kSPS, for example, it consumes typically
150 µW with a 2.7 V supply, ideal for battery-powered
applications.
The AD7683 provides the user with an on-chip track-and-hold
and does not exhibit any pipeline delay or latency, making it
ideal for multiple, multiplexed channel applications.
The AD7683 is specified from 2.7 V to 5.5 V. It is housed in an
8-lead MSOP or a tiny, 8-lead QFN (LFCSP) package.
The AD7683 is an improved second source to the ADS8320 and
ADS8325. For even better performance, consider the AD7685.
CONVERTER OPERATION
The AD7683 is a successive approximation ADC based on a
charge redistribution DAC. Figure 21 shows the simplified
schematic of the ADC. The capacitive DAC consists of two
identical arrays of 16 binary-weighted capacitors that connect
to the two comparator inputs.
During the acquisition phase, terminals of the array tied to the
comparator’s input are connected to GND via SW+ and SW−.
All independent switches are connected to the analog inputs.
Thus, the capacitor arrays are used as sampling capacitors and
acquire the analog signal on the +IN and −IN inputs. When the
acquisition phase is complete and the
version phase is initiated. When the conversion phase begins,
SW+ and SW− are opened first. The two capacitor arrays are
then disconnected from the inputs and connected to the GND
input. Therefore, the differential voltage between the inputs,
+IN and −IN, captured at the end of the acquisition phase is
applied to the comparator inputs, causing the comparator to
become unbalanced. By switching each element of the capacitor
CS
input goes low, a con-
Figure 21. ADC Simplified Schematic
array between GND and REF, the comparator input varies by
binary-weighted voltage steps (V
The control logic toggles these switches, starting with the MSB,
to bring the comparator back into a balanced condition. After
the completion of this process, the part returns to the acquisition
phase and the control logic generates the ADC output code.
TRANSFER FUNCTIONS
The ideal transfer function for the AD7683 is shown in Figure 22
and Tabl e 10.
Table 10. Output Codes and Ideal Input Voltages
Description
FSR – 1 LSB 4.999924 V FFFF1
Midscale + 1 LSB 2.500076 V 8001
Midscale 2.5 V 8000
Midscale – 1 LSB 2.499924 V 7FFF
–FSR + 1 LSB 76.3 µV 0001
–FSR 0 V 00002
1
Rev. B | Page 12 of 16
This is also the code for an overranged analog input (V
V
– V
REF
GND
2
This is also the code for an underranged analog input (V
REF
Figure 22. ADC Ideal Transfer Function
Analog Input
V
= 5 V
REF
).
/2, V
REF
/4...V
/65,536).
REF
Digital Output Code
Hexadecimal
– V
above
+IN
–IN
– V
+IN
–IN
below V
GND
).
Page 13
Data Sheet AD7683
0V TO V
REF
(NOTE 3)
NOTES
1. SEE VOL TAGE REFERENCE INPUT SECT ION FO R REFERENCE SEL ECTION.
2. C
IS USUALLY A 10µF CERAMIC CAPACI TOR (X5R).
REF
3. SEE DRIVER AMPLIFIER CHOICE SECTION.
4. OPTI ONAL FILTER. SEE ANALOG INPUT SECTIO N.
(NOTE 1)
REF
33Ω
2.7nF
(NOTE 4)
C
2.2µF TO 10µF
REF
(NOTE 2)
Figure 23. Typical Application Diagram
TYPICAL CONNECTION DIAGRAM
Figure 23 shows an example of the recommended application
diagram for the AD7683.
ANALOG INPUT
Figure 24 shows an equivalent circuit of the input structure of
the AD7683. The two diodes, D1 and D2, provide ESD protection for the analog inputs, +IN and −IN. Care must be taken to
ensure that the analog input signal never exceeds the supply rails
by more than 0.3 V because this causes these diodes to become
forward-biased and start conducting current. However, these
diodes can handle a forward-biased current of 130 mA maximum.
For instance, these conditions can eventually occur when the
input buffer (U1) supplies are different from VDD. In such a
case, use an input buffer with a short-circuit current limitation
to protect the part.
VDD
+IN
OR –IN
GND
D1
C
PIN
D2
R
Figure 24. Equivalent Analog Input Circuit
This analog input structure allows the sampling of the differential signal between +IN and −IN. By using this dierential input,
small signals common to both inputs are rejected. For instance,
by using −IN to sense a remote signal ground, ground potential
differences between the sensor and the local ADC ground are
eliminated. During the acquisition phase, the impedance of the
analog input, +IN, can be modeled as a parallel combination of
Capacitor C
of R
and CIN. C
IN
and the network formed by the series connection
PIN
is primarily the pin capacitance. RIN is typically
PIN
600 Ω and is a lumped component consisting of some serial
resistors and the on resistance of the switches. C
30 pF and is mainly the ADC sampling capacitor. During the
conversion phase, when the switches are opened, the input
impedance is limited to C
. RIN and CIN make a 1-pole, low-
PIN
IN
C
IN
is typically
IN
04301-023
+IN
–IN
2.7V TO 5. 25V
3-WIRE INT ERFACE
04301-022
REF
AD7683
GND
VDD
DCLOCK
D
OUT
CS
100nF
pass filter that reduces undesirable aliasing effects and limits
the noise.
When the source impedance of the driving circuit is low, the
AD7683 can be driven directly. Large source impedances signi-
ficantly affect the ac performance, especially THD. The dc
performances are less sensitive to the input impedance.
DRIVER AMPLIFIER CHOICE
Although the AD7683 is easy to drive, the driver amplifier
needs to meet the following requirements:
The noise generated by the driver amplifier needs to be
kept as low as possible to preserve the SNR and transition
noise performance of the AD7683. Note that the AD7683
has a noise figure much lower than most other 16-bit
ADCs and, therefore, can be driven by a noisier op amp
while preserving the same or better system performance.
The noise coming from the driver is filtered by the AD7683
analog input circuit, 1-pole, low-pass filter made by R
and C
or by the external filter, if one is used.
IN
For ac applications, the driver needs to have a THD
performance suitable to that of the AD7683. Figure 16 shows
the THD vs. frequency that the driver should exceed.
For multichannel multiplexed applications, the driver
amplifier and the AD7683 analog input circuit must be
able to settle for a full-scale step of the capacitor array at a
16-bit level (0.0015%). In the amplifier data sheet, settling
at 0.1% to 0.01% is more commonly specified. This could
differ significantly from the settling time at a 16-bit level
and should be verified prior to driver selection.
Table 11. Recommended Driver Amplifiers
Amplifier Typical Application
ADA4841-1 Very low noise and low power
OP184 Low power, low noise, and low frequency
AD8605, AD8615 5 V single-supply, low power
AD8519 Low power and low frequency
AD8031 High frequency and low power
IN
Rev. B | Page 13 of 16
Page 14
AD7683 Data Sheet
VOLTAGE REFERENCE INPUT
The AD7683 voltage reference input, REF, has a dynamic input
impedance. Therefore, it should be driven by a low impedance
source with efficient decoupling between the REF and GND
pins, as explained in the Layout section.
When REF is driven by a very low impedance source (such as
an unbuffered reference voltage like the low temperature drift
ADR435 reference or a reference buffer using the AD8031 or
the AD8605), a 10 μF (X5R, 0805 size) ceramic chip capacitor is
appropriate for optimum performance.
If desired, smaller reference decoupling capacitors with values
as low as 2.2 μF can be used with a minimal impact on performance, especially DNL.
POWER SUPPLY
The AD7683 powers down automatically at the end of each
conversion phase and, therefore, the power scales linearly with
the sampling rate, as shown in Figure 25. This makes the part
ideal for low sampling rates (even of a few Hz) and low batterypowered applications.
1000
100
10
1
OPERATING CURRENT (µA)
0.1
0.01
10 100 1k 10k 100k
Figure 25. Operating Current vs. Sampling Rate
SAMPLING RATE (SPS)
VDD = 5V
VDD = 2.7V
04301-024
DIGITAL INTERFACE
The AD7683 is compatible with SPI®, QSPI™, digital hosts,
MICROWIRE™, and DSPs (for example, Blackfin® ADSP-BF531,
ADSP-BF532, ADSP-BF533, or the ADSP-2191M). The connection
diagram is shown in Figure 26 and the corresponding timing is
given in Figure 2.
A falling edge on
After the fifth DCLOCK falling edge, D
low. The data bits are then clocked, MSB first, by subsequent
CS
initiates a conversion and the data transfer.
is enabled and forced
OUT
DCLOCK falling edges. The data is valid on both DCLOCK
edges. Although the rising edge can be used to capture the data,
a digital host also using the DCLOCK falling edge allows a
faster reading rate, provided it has an acceptable hold time.
CONVERT
CS
AD7683
D
DCLOCK
OUT
Figure 26. Connection Diagram
DIGITAL HOST
DATA IN
CLK
04301-025
LAYOUT
Design the PCB that houses the AD7683 so that the analog and
digital sections are separated and confined to certain areas of
the board. The pin configuration of the AD7683, with all its
analog signals on the left side and all its digital signals on the
right side, eases this task.
Avoid running digital lines under the device because these
couple noise onto the die, unless a ground plane under the
AD7683 is used as a shield. Fast switching signals, such as
CS
or clocks, should never run near analog signal paths. Avoid
crossover of digital and analog signals.
Use at least one ground plane. It can be common or split between
the digital and analog sections. In such a case, it should be joined
underneath the AD7683.
The AD7683 voltage reference input (REF) has a dynamic input
impedance and should be decoupled with minimal parasitic
inductances. Accomplish this by placing the reference decoupling
ceramic capacitor close to, and ideally right up against, the REF
and GND pins and by connecting these pins with wide, low
impedance traces.
Finally, decouple the power supply, VDD, of the AD7683 with a
ceramic capacitor, typically 100 nF, placed close to the AD7683.
Connect it using short and large traces to provide low impedance
paths and reduce the effect of glitches on the power supply lines.
EVALUATING THE AD7683 PERFORMANCE
Other recommended layouts for the AD7683 are outlined in the
evaluation board for the AD7683 (EVAL-AD7683CBZ). The
evaluation board package includes a fully assembled and tested
evaluation board, documentation, and software for controlling
the board from a PC via the EVAL-CONTROL BRD3Z.
Rev. B | Page 14 of 16
Page 15
Data Sheet AD7683
COMPLI ANT TO JEDEC STANDARDS MO-187-AA
6°
0°
0.80
0.55
0.40
4
8
1
5
0.65 BSC
0.40
0.25
1.10 MAX
3.20
3.00
2.80
COPLANARITY
0.10
0.23
0.09
3.20
3.00
2.80
5.15
4.90
4.65
PIN 1
IDENTIFIER
15° MAX
0.95
0.85
0.75
0.15
0.05
10-07-2009-B
8
1
5
4
0.35
0.30
0.25
PIN 1 INDEX
ARE
A
SEA
TING
PLANE
0.80
0.75
0.70
0.20 REF
0.05 MAX
0.02 NOM
0.80 MAX
0.55 NOM
1.74
1.64
1.49
2.48
2.38
2.23
0.50
0.40
0.30
0.65 BSC
PIN 1
INDICATOR
(R 0.2)
02-05-2013-C
FOR PROPE R CONNECTIO N OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DE S CRIPTIO NS
SECTION OF THIS DATA SHEET.
T
O
P
VIEW
BOTTOM VIEW
0.20 MIN
EXPOSED
PA
D
3.10
3.00 SQ
2.90
OUTLINE DIMENSIONS
Figure 27. 8-Lead Mini Small Outline Package [MSOP]
Dimensions Shown in millimeters
(RM-8)
Figure 28. 8-Terminal Quad Flat No Lead Package (QFN) [LFCSP_WD]
3 mm × 3 mm Body, Very Very Thin, Dual Lead
(CP-8-3)
Dimensions Shown in millimeters
Rev. B | Page 15 of 16
Page 16
AD7683 Data Sheet
Integral
Package
Ordering
©2004–2016 Analog Devices, Inc. All rights reserved. Trademarks and
ORDERING GUIDE
Model1
Nonlinearity Temperature Range Package Description2
Option Branding
Quantity
AD7683ACPZRL7 ±6 LSB max –40°C to +85°C 8-Lead QFN [LFCSP_WD] CP-8-3 C4G Reel, 1,500
AD7683ARMZ ±6 LSB max –40°C to +85°C 8-Lead MSOP RM-8 C4G Tube, 50
AD7683ARMZRL7 ±6 LSB max –40°C to +85°C 8-Lead MSOP RM-8 C4G Reel, 1,000
AD7683BCPZRL7 ±3 LSB max –40°C to +85°C 8-Lead QFN [LFCSP_WD] CP-8-3 C38 Reel, 1,500
AD7683BRMZ ±3 LSB max –40°C to +85°C 8-Lead MSOP RM-8 C38 Tube, 50
AD7683BRMZRL7 ±3 LSB max –40°C to +85°C 8-Lead MSOP RM-8 C38 Reel, 1,000
EVA L-AD7683SDZ Evaluation Board
EVAL-CONTROL BRD3Z Controller Board
1
Z = RoHS Compliant Part.
2
The EVAL CONTROL BRD3Z board allows a PC to control and communicate with all Analog Devices evaluation boards ending in the CB designators.
registered trademarks are the property of their respective owners.
D04301-0-2/16(B)
Rev. B | Page 16 of 16
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