16-Bit, 100 kSPS, Single-Ended
V
Data Sheet
FEATURES
16-bit resolution with no missing codes
Throughput: 100 kSPS
INL: ±1 LSB typical, ±3 LSB maximum
Pseudo differential analog input range
0 V to V
Single-supply operation: 2.7 V to 5.5 V
Serial interface SPI/QSPI/MICROWIRE/DSP compatible
Power dissipation: 4 mW @ 5 V, 1.5 mW @ 2.7 V,
Standby current: 1 nA
8-lead packages:
Improved second source to ADS8320 and ADS8325
APPLICATIONS
Battery-powered equipment
Data acquisition
Instrumentation
Medical instruments
Process control
GENERAL DESCRIPTION
The AD7683 is a 16-bit, charge redistribution, successive
approximation, PulSAR® analog-to-digital converter (ADC)
that operates from a single power supply, VDD, between 2.7 V
and 5.5 V. It contains a low power, high speed, 16-bit sampling
ADC with no missing codes (B grade), an internal conversion
clock, and a serial, SPI-compatible interface port. The part also
contains a low noise, wide bandwidth, short aperture delay,
track-and-hold circuit. On the
with V
REF
up to VDD
REF
150 μW @ 2.7 V/10 kSPS
MSOP
3 mm × 3 mm QFN (LFCSP) (SOT-23 size)
CS
falling edge, it samples an
PulSAR ADC in MSOP/QFN
AD7683
APPLICATION DIAGRAM
0.5V TO VDD 2.7V TO 5.5
REF
0V TO V
REF
+IN
–IN
Table 1. MSOP, QFN (LFCSP)/SOT-23, 14-/16-/18-Bit
PulSAR ADC
Type
18-Bit True
Differential
16-Bit True
Differential
16-Bit
Pseudo
Differential
14-Bit
Pseudo
Differential
100
kSPS
AD7691 AD7690 AD7982
AD7684 AD7687 AD7688
AD7680
AD7683
AD7940 AD7942 AD7946 ADA4841-1
250
kSPS
AD7685
AD7694
analog input, +IN, between 0 V to REF with respect to a ground
sense, –IN. The reference voltage, REF, is applied externally and
can be set up to the supply voltage. Its power scales linearly with
throughput.
The AD7683 is housed in an 8-lead MSOP or an 8-lead QFN
(LFCSP) package, with an operating temperature specified from
−40°C to +85°C.
VDD
DCLOCK
AD7683
GND
Figure 1.
D
OUT
CS
400 kSPS
to
500 kSPS
AD7693
AD7686 AD7980 ADA4841-1
3-WIRE SPI
INTERFACE
≥1000
kSPS
AD7984
ADA4941-1
ADC
Driver
ADA4941-1
ADA4841-1
ADA4841-1
04301-001
Rev. B Document Feedback
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AD7683 Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
Application Diagram ........................................................................ 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
Timing Specifications .................................................................. 5
Absolute Maximum Ratings ............................................................ 6
Thermal Resistance ...................................................................... 6
ESD Caution .................................................................................. 6
Pin Configurations and Function Descriptions ........................... 7
Terminolog y ...................................................................................... 8
Typical Performance Characteristics ............................................. 9
Applications Information .............................................................. 12
Circuit Information .................................................................... 12
Converter Operation .................................................................. 12
Transfer Functions ..................................................................... 12
Typical Connection Diagram ................................................... 13
Analog Input ............................................................................... 13
Driver Amplifier Choice ........................................................... 13
Voltage Reference Input ............................................................ 14
Power Supply ............................................................................... 14
Digital Interface .......................................................................... 14
Layout .......................................................................................... 14
Evaluating the AD7683 Performance ...................................... 14
Outline Dimensions ....................................................................... 15
Ordering Guide .......................................................................... 16
REVISION HISTORY
2/16—Rev. A to Rev. B
Changes to Table 1 ............................................................................ 1
Added Figure 7 and Table 9; Renumbered Sequentially ............. 7
Changes to Table 10 ........................................................................ 13
Changes to Digital Interface Section ............................................ 14
Updated Outline Dimensions ....................................................... 16
Changes to Ordering Guide .......................................................... 16
2/08—Rev. 0 to Rev. A
Change to Title .................................................................................. 1
Moved Figure 3, Figure 4, and Figure 5 ......................................... 5
Changes to Figure 4 .......................................................................... 5
Moved Figure 17 and Figure 18 .................................................... 11
Changes to Figure 22 ...................................................................... 13
Updated Outline Dimensions ....................................................... 15
Changes to Ordering Guide .......................................................... 16
9/04—Initial Version: Revision 0
Rev. B | Page 2 of 16
Data Sheet AD7683
VDD
VDD = 5 V
800 µA
VDD = 2.7 V, 10 kSPS throughput2
150 µW
SPECIFICATIONS
VDD = 2.7 V to 5.5 V; V
Table 2.
Parameter Conditions
RESOLUTION 16 Bits
ANALOG INPUT
Voltage Range +IN − (–IN) 0 V
Absolute Input Voltage +IN −0.1 VDD + 0.1 V
−IN −0.1 0.1 V
Analog Input CMRR fIN = 100 kHz 65 dB
Leakage Current at 25°C Acquisition phase 1 nA
Input Impedance See the Analog Input section
THROUGHPUT SPEED
Complete Cycle 10 µs
Throughput Rate 0 100 kSPS
DCLOCK Frequency 0 2.9 MHz
REFERENCE
Voltage Range 0.5 VDD + 0.3 V
Load Current 100 kSPS, V
DIGITAL INPUTS
Logic Levels
VIL −0.3 0.3 × VDD V
VIH 0.7 × VDD VDD + 0.3 V
IIL −1 +1 µA
IIH −1 +1 µA
Input Capacitance 5 pF
DIGITAL OUTPUTS
Data Format Serial, 16 bits straight binary
VOH I
VOL I
POWER SUPPLIES
VDD Specified performance 2.7 5.5 V
VDD Range1 2.0 5.5 V
Operating Current 100 kSPS throughput
= VDD; TA = –40°C to +85°C, unless otherwise noted.
REF
− V
= V
+IN
−IN
= −500 µA VDD − 0.3 V
SOURCE
= +500 µA 0.4 V
SINK
/2 = 2.5 V 50 µA
REF
AD7683 All Grades
REF
Unit Min Typ Max
V
VDD = 2.7 V 560 µA
Standby Current
Power Dissipation VDD = 5 V 4 6 mW
VDD = 2.7 V 1.5 mW
TEMPERATURE RANGE
Specified Performance T
1
See the Typical Performance Characteristics section for more information.
2
With all digital inputs forced to VDD or GND, as required.
3
During acquisition phase.
2, 3
VDD = 5 V, 25°C 1 50 nA
to T
MIN
−40 +85 °C
MAX
Rev. B | Page 3 of 16
AD7683 Data Sheet
Gain Error1, T
to T
±2
±24 ±2
±15
LSB
Power Supply Sensitivity
±0.05
±0.05
LSB
Signal-to-Noise
fIN = 1 kHz
85
86 dB2
VDD = 5 V; V
Table 3.
Parameter Conditions
ACCURACY
No Missing Codes 15 16 Bits
Integral Linearity Error −6 ±3 +6 −3 ±1 +3 LSB
Transition Noise 0.5 0.5 LSB
Gain Error Temperature Drift ±0.3 ±0.3 ppm/°C
Offset Error1, T
Offset Temperature Drift ±0.3 ±0.3 ppm/°C
Power Supply Sensitivity
AC ACCURACY
Signal-to-Noise fIN = 1 kHz 90 88 91 dB2
Spurious-Free Dynamic Range fIN = 1 kHz −100 −108 dB
Total Harmonic Distortion fIN = 1 kHz −100 −106 dB
Signal-to-(Noise + Distortion) fIN = 1 kHz 90 88 91 dB
Effective Number of Bits fIN = 1 kHz 14.7 14.8 Bits
1
See the Terminology section. These specifications include full temperature range variation but do not include the error contribution from the external reference.
2
All specifications in dB are referred to a full-scale input, FS. Tested with an input signal at 0.5 dB below full scale, unless otherwise specified.
VDD = 2.7 V; V
= VDD; TA = –40°C to +85°C, unless otherwise noted.
REF
MIN
MAX
to T
MIN
±0.7 ±1.6 ±0.4 ±1.6 mV
MAX
VDD = 5 V ± 5%
= 2.5V; TA = –40°C to +85°C, unless otherwise noted.
REF
A Grade B Grade
Unit Min Typ Max Min Ty p Max
±0.05 ±0.05 LSB
Table 4.
A Grade B Grade
Parameter Conditions Min Typ Max Min Ty p Max Unit
ACCURACY
No Missing Codes 15 16 Bits
Integral Linearity Error −6 ±3 +6 −3 ±1 +3 LSB
Transition Noise 0.85 0.85 LSB
Gain Error1, T
MIN
to T
±2 ±30 ±2 ±15 LSB
MAX
Gain Error Temperature Drift ±0.3 ±0.3 ppm/°C
Offset Error1, T
MIN
to T
±0.7 ±3.5 ±0.7 ±3.5 mV
MAX
Offset Temperature Drift ±0.3 ±0.3 ppm/°C
VDD = 2.7 V ±5%
AC ACCURACY
Spurious-Free Dynamic Range fIN = 1 kHz −96 −100 dB
Total Harmonic Distortion fIN = 1 kHz −94 −98 dB
Signal-to-(Noise + Distortion) fIN = 1 kHz 85 86 dB
Effective Number of Bits fIN = 1 kHz 13.8 14 Bits
1
See the Terminology section. These specifications do include full temperature range variation but do not include the error contribution from the external reference.
2
All specifications in dB are referred to a full-scale input FS. Tested with an input signal at 0.5 dB below full scale, unless otherwise specified.
Rev. B | Page 4 of 16
Data Sheet AD7683
T
TIMING SPECIFICATIONS
VDD = 2.7 V to 5.5 V; TA = −40°C to +85°C, unless otherwise noted.
Table 5.
Parameter Symbol Min Typ Max Unit
Throughput Rate t
CS Falling to DCLOCK Low
CS Falling to DCLOCK Rising
DCLOCK Falling to Data Remains Valid t
CS Rising Edge to D
High Impedance
OUT
DCLOCK Falling to Data Valid tEN 16 50 ns
Acquisition Time t
D
Fall Time tF 11 25 ns
OUT
D
Rise Time tR 11 25 ns
OUT
Timing and Circuit Diagrams
t
CYC
CS
t
SUCS
DCLOCK
D
OUT
145
t
CSD
HIGH-Z
NOTES
1. A MINIMUM OF 22 CLOCK CYCLES ARE REQUI RED FOR 16-BIT CONVERSIO N. SHOWN ARE 24 CLOCK CYCLES.
GOES LO W ON THE DCLO CK FALLING EDGE FO LLOWING THE LS B READING.
D
OUT
t
EN
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
0
(MSB) (LSB)
COMPLETE CYCLE
t
HDO
Figure 2. Serial Interface Timing
100 kHz
CYC
t
0 μs
CSD
t
20 ns
SUCS
5 16 ns
HDO
t
14 100 ns
DIS
400 ns
ACQ
t
ACQ
POWER DOW N
t
DIS
HIGH-Z
0
04301-002
O D
OUT
100pF
C
L
500µA I
500µA I
OL
1.4V
OH
04301-003
Figure 3. Load Circuit for Digital Interface Timing
0.8V
t
EN
2V
Figure 4. Voltage Reference Levels for Timing
2V
t
EN
2V
0.8V0.8V
04301-004
D
OUT
t
R
Figure 5. D
Rise and Fall Timing
OUT
t
F
90%
10%
04301-006
Rev. B | Page 5 of 16