+3 V, Dual, Serial Input
a
FEATURES
Micropower: 100 mA/DAC
0.1 mA Typical Power Shutdown
Single-Supply +2.7 V to +5.5 V Operation
Compact 1.1 mm Height TSSOP-14 Package
AD7394/12-Bit Resolution
AD7395/10-Bit Resolution
Serial Interface with Schmitt Trigger Inputs
APPLICATIONS
Automotive Output Span Voltage
Portable Communications
Digitally Controlled Calibration
PC Peripherals
GENERAL DESCRIPTION
The AD7394/AD7395 family of dual, 12-/10-bit, voltage output
digital-to-analog converters is designed to operate from a single
+3 V supply. Built using a CBCMOS process, this monolithic
DAC offers the user low cost and ease of use in single-supply
+3 V systems. Operation is guaranteed over the supply voltage
range of +2.7 V to +5.5 V making this device ideal for battery
operated applications.
The full-scale output voltage is determined by the applied external reference input voltage, VREF. The rail-to-rail VREF input
to V
positive supply V
A doubled-buffered serial data interface offers high speed,
microcontroller compatible inputs using serial-data-in (SDI),
clock (CLK) and load strobe (LDA + LDB) pins. A chip-select
(CS) pin simplifies connection of multiple DAC packages by
enabling the clock input when active low. Additionally, an RS
input sets the output to zero scale or to 1/2 scale based on the
logic level applied to the MSB pin. The power shutdown pin,
SHDN, reduces power dissipation to nanoamp current levels.
All digital inputs contain Schmitt-triggered logic levels to minimize power dissipation and prevent false triggering on the clock
input.
Both parts are offered in the same pinout to allow users to select
the amount of resolution appropriate for their application without circuit card redesign.
outputs allows for a full-scale voltage set equal to the
OUT
or any value in between.
DD
12-/10-Bit DACs
AD7394/AD7395
FUNCTIONAL BLOCK DIAGRAM
VDDV
REF
AGND
OP
AMP A
OP
AMP B
SHDN
V
V
OUTA
OUTB
R
CS
CLK
SDI
(DATA)
LDA
LDB
EN
R
E
S
G
H
I
I
S
F
T
T
E
R
DGND MSB
E
D
G
A
I
C
S
T
A
E
R
D
PR
12
DAC A
AD7394/AD7395
R
D
E
D
G
A
I
C
S
T
B
E
R
PR
DAC B
RS
The AD7394/AD7395 is specified over the extended industrial
(–40°C to +85°C) temperature range. Packages available in-
clude plastic DIP and low profile 1.75 mm height SO-14 surface
mount packages. The AD7395ARU is available for ultracompact
applications in a thin 1.1 mm TSSOP-14 package. For automotive
applications the AD7395AR is specified for operation over the
(–40°C to +125°C) temperature range.
1
VDD = 3V
0.8
V
= 2.5V
REF
0.6
0.4
0.2
0
DNL – LSB
–0.2
–0.4
–0.6
TA = –558C, +258C, +858C
–0.8
SUPERIMPOSED
–1
0 1000500
1500 25002000 3000 40003500
CODE – Decimal
Figure 1. Differential Nonlinearity Error vs. Code
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
Fax: 781/326-8703 © Analog Devices, Inc., 1998
AD7394/AD7395–SPECIFICATIONS
AD7394 12-BIT RAIL-TO-RAIL VOLTAGE OUT DAC
ELECTRICAL CHARACTERISTICS
(@ V
= 2.5 V, –408C < TA < +858C, unless otherwise noted)
REF IN
Parameter Symbol Conditions 3 V 6 10% 5 V 6 10% Units
STATIC PERFORMANCE
Resolution
Relative Accuracy
Relative Accuracy
Differential Nonlinearity
Differential Nonlinearity
Zero-Scale Error V
Full-Scale Voltage Error V
Full-Scale Voltage Error V
Full-Scale Tempco
1
2
2
2
2
3
N 12 12 Bits
INL T
INL T
DNL T
= +25°C ±1.5 ±1.5 LSB max
A
= –40°C, +85°C ±2.0 ±2.0 LSB max
A
= +25°C, Monotonic ±0.9 ±0.9 LSB max
A
DNL Monotonic ±1 ±1 LSB max
ZSE
FSE
FSE
TCV
FS
Data = 000
T
= +25°C, +85°C, Data = FFFH±8 ±8 mV max
A
T
= –40°C, Data = FFF
A
H
H
4.0 4.0 mV max
±20 ±20 mV max
–30 –30 ppm/°C typ
REFERENCE INPUT
V
Range V
REF IN
Input Resistance R
Input Capacitance
3
REF
REF
C
REF
0/V
DD
0/V
DD
V min/max
2.5 2.5 MΩ typ
5 5 pF typ
ANALOG OUTPUT
Output Current (Source) I
Output Current (Sink) I
Capacitive Load
3
OUT
OUT
C
L
Data = 800
Data = 800
H
H
, ∆V
, ∆V
= 5 LSB 1 1 mA typ
OUT
= 5 LSB 3 3 mA typ
OUT
No Oscillation 100 100 pF typ
LOGIC INPUTS
Logic Input Low Voltage V
Logic Input High Voltage V
Input Leakage Current I
Input Capacitance
INTERFACE TIMING
3
3, 5
Clock Width High t
Clock Width Low t
Load Pulsewidth t
Data Setup t
Data Hold t
Clear Pulsewidth t
Load Setup t
Load Hold t
IL
IH
IL
C
IL
CH
CL
LDW
DS
DH
CLRW
LD1
LD2
0.5 0.8 V max
VDD–0.6 4.0 V min
10 10 µA max
10 10 pF max
50 30 ns min
50 30 ns min
30 20 ns min
10 10 ns min
30 15 ns min
15 15 ns min
30 15 ns min
40 20 ns min
AC CHARACTERISTICS
Output Slew Rate SR Data = 000H to FFFH to 000
Settling Time
DAC Glitch Q Code 7FF
6
t
S
To ± 0.1% of Full Scale 70 60 µs typ
to 800H to 7FF
H
H
H
0.05 0.05 V/µs typ
65 65 nV/s typ
Digital Feedthrough Q 15 15 nV/s typ
Feedthrough V
OUT/VREF
V
= 1.5 VDC +1 V p-p
REF
,
Data = 000H, f = 100 kHz –63 –63 dB typ
SUPPLY CHARACTERISTICS
Power Supply Range V
Shutdown Supply Current I
Positive Supply Current I
Power Dissipation P
DD RANGE
DD_SD
DD
DISS
DNL < ±1 LSB 2.7/5.5 2.7/5.5 V min/max
SHDN = 0, V
V
= 0 V, No Load 125/200 125/200 µA typ/max
IL
V
= 0 V, No Load 600 1000 µW max
IL
= 0 V, No Load 0.1/1.5 0.1/1.5 µA typ/max
IL
Power Supply Sensitivity PSS ∆VDD = ±5% 0.006 0.006 %/% max
NOTES
1
One LSB = V
2
The first two codes (000H, 001H) are excluded from the linearity error measurement.
3
These parameters are guaranteed by design and not subject to production testing.
4
Typicals represent average readings measured at +25° C.
5
All input control signals are specified with tR = tF = 2 ns (10% to 90% of +3 V) and timed from a voltage level of 1.6 V.
6
The settling time specification does not apply for negative going transitions within the last three LSBs of ground.
Specifications subject to change without notice.
/4096 V for the 12-bit AD7394.
REF
4
–2–
REV. 0
AD7395 10-BIT RAIL-TO-RAIL VOLTAGE OUT DAC
AD7394/AD7395
ELECTRICAL CHARACTERISTICS
(@ V
= 2.5 V, –408C < TA < +858C/+1258C, unless otherwise noted)
REF IN
Parameter Symbol Conditions 3 V 6 10% 5 V 6 10% Units
STATIC PERFORMANCE
Resolution
Relative Accuracy
Relative Accuracy
Differential Nonlinearity
Zero-Scale Error V
Full-Scale Voltage Error V
Full-Scale Voltage Error V
Full-Scale Tempco
1
2
2
2
3
N 10 10 Bits
INL T
INL T
= +25°C ±1.5 ±1.5 LSB max
A
= –40°C, +85°C, +125°C ±2.0 ±2.0 LSB max
A
DNL Monotonic ±1 ±1 LSB max
ZSE
FSE
FSE
TCV
FS
Data = 000
T
= +25°C, +85°C, +125°C
A
Data = FFF
T
= –40°C, Data = FFF
A
H
H
H
9.0 9.0 mV max
±42 ±42 mV max
±48 ±48 mV max
–35 –35 ppm/°C typ
REFERENCE INPUT
V
Range V
REF IN
Input Resistance R
Input Capacitance
3
REF
REF
C
REF
0/V
DD
0/V
DD
V min/max
2.5 2.5 MΩ typ
5 5 pF typ
ANALOG OUTPUT
Output Current (Source) I
Output Current (Sink) I
Capacitive Load
3
OUT
OUT
C
L
Data = 200
Data = 200
H
H
, ∆V
, ∆V
= 5 LSB 1 1 mA typ
OUT
= 5 LSB 3 3 mA typ
OUT
No Oscillation 100 100 pF typ
LOGIC INPUTS
Logic Input Low Voltage V
Logic Input High Voltage V
Input Leakage Current I
Input Capacitance
INTERFACE TIMING
3
3, 5
Clock Width High t
Clock Width Low t
Load Pulsewidth t
Data Setup t
Data Hold t
Clear Pulsewidth t
Load Setup t
Load Hold t
IL
IH
IL
C
IL
CH
CL
LDW
DS
DH
CLRW
LD1
LD2
0.5 0.8 V max
VDD–0.6 4.0 V min
10 10 µA max
10 10 pF max
50 30 ns min
50 30 ns min
30 20 ns min
10 10 ns min
30 15 ns min
15 15 ns min
30 15 ns min
40 20 ns min
AC CHARACTERISTICS
Output Slew Rate SR Data = 000H to 3FFH to 000
Settling Time
DAC Glitch Q Code 7FF
6
t
S
To ± 0.1% of Full Scale 70 60 µs typ
to 800H to 7FF
H
H
H
0.05 0.05 V/µs typ
65 65 nV/s typ
Digital Feedthrough Q 15 15 nV/s typ
Feedthrough V
OUT/VREF
V
= 1.5 VDC +1 V p-p
REF
,
Data = 000H, f = 100 kHz –63 –63 dB typ
SUPPLY CHARACTERISTICS
Power Supply Range V
Shutdown Supply Current I
Positive Supply Current I
Power Dissipation P
DD RANGE
DD_SD
DD
DISS
DNL < ±1 LSB 2.7/5.5 2.7/5.5 V min/max
SHDN = 0, V
V
= 0 V, No Load 125/200 125/200 µA typ/max
IL
V
= 0 V, No Load 600 1000 µW max
IL
= 0 V, No Load 0.1/1.5 0.1/1.5 µA typ/max
IL
Power Supply Sensitivity PSS ∆VDD = ±5% 0.006 0.006 %/% max
NOTES
1
One LSB = V
2
The first two codes (000H, 001H) are excluded from the linearity error measurement.
3
These parameters are guaranteed by design and not subject to production testing.
4
Typicals represent average readings measured at +25°C.
5
All input control signals are specified with tR = tF = 2 ns (10% to 90% of +3 V) and timed from a voltage level of 1.6 V.
6
The settling time specification does not apply for negative going transitions within the last three LSBs of ground.
Specifications subject to change without notice.
/4096 V for the 10-bit AD7395.
REF
4
–3–REV. 0
AD7394/AD7395
SDI
CLK
LDA,B
SDI
CLK
LDA,B
V
OUT
CS
RS
FS
ZS
SHDN
I
D0D1D2D3D4D5D6D7D8D9D10D11
t
61 LSB
CSH
t
LD2
t
CLRW
t
S
t
CSS
t
LD1
t
t
DH
DS
t
CL
t
CH
t
LDW
t
S
ERROR BAND
Figure 2. Timing Diagram
t
SDR
DD
Figure 3. Timing Diagram
Table I. Control Logic Truth Table
CS CLK RS MSB SHDN LDA/B Serial Shift Register Function DAC Register Function
H X H X H H No Effect Latched
L L H X H H No Effect Latched
L H H X H H No Effect Latched
L ↑+ H X H H Shift-Register-Data Advanced One Bit Latched
L ↑+ H X H L Shift-Register-Data Advanced One Bit Transparent
L H H X H L No Effect Transparent
↑+ L H X H H No Effect Latched
HX H X H ↓– No Effect Updated with Current Shift Register
Contents
H X H X H L No Effect Transparent
X X L H H X No Effect Loaded with 800
XX ↑+ H H H No Effect Latched with 800
H
H
X X L L H X No Effect Loaded with All Zeros
XX ↑+ L H H No Effect Latched All Zeros
X X X X L X No Effect No Affect
NOTES
1. ↑+ positive logic transition; ↓– negative logic transition; X Don’t Care
2. Do not clock in serial data while level sensitive inputs LDA or LDB are logic LOW.
–4–
REV. 0
AD7394/AD7395
Table II. AD7394 Serial Input Register Data Format, Data Is Loaded in MSB-First Format
MSB LSB
B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
AD7394 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Table III. AD7395 Serial Input Register Data Format, Data Is Loaded in MSB-First Format
MSB LSB
B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
AD7395 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
ABSOLUTE MAXIMUM RATINGS*
VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . .–0.3 V, +7 V
V
to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, V
REF
DD
Logic Inputs to GND . . . . . . . . . . . . . . . . . . . . . –0.3 V, +8 V
V
to GND . . . . . . . . . . . . . . . . . . . . . –0.3 V, VDD + 0.3 V
OUT
I
Short Circuit to GND . . . . . . . . . . . . . . . . . . . . . 50 mA
OUT
Package Power Dissipation . . . . . . . . . . . . . (T
Thermal Resistance θ
JA
max – T
J
)/θ
A
14-Lead Plastic DIP Package (N-14) . . . . . . . . . . 103°C/W
14-Lead SOIC Package (R-14) . . . . . . . . . . . . . . . 158°C/W
14-Lead Thin Shrink Surface Mount (RU-14) . . . 180°C/W
Maximum Junction Temperature (T
max) . . . . . . . . . . 150°C
J
Operating Temperature Range . . . . . . . . . . . –40°C to +85°C
AD7395AR and AD7395AN Only . . . . . . –40°C to +125°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Lead Temperature
␣ ␣ N-14 (Soldering, 10 sec) . . . . . . . . . . . . . . . . . . . . . .+300°C
␣ ␣ R-14 (Vapor Phase, 60 sec) . . . . . . . . . . . . . . . . . . . .+215°C
␣ ␣ RU-14 (Infrared, 15 sec) . . . . . . . . . . . . . . . . . . . . . .+224°C
JA
*Stresses above those listed under Absolute Maximum Ratings may cause
permanent damage to the device. This is a stress rating only; functional operation
of the device at these or any other conditions above those indicated in the
operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
ORDERING GUIDE
Res Temperature Package Package
Model (LSB) Range Description Options
AD7394AN 12 –40°C to +85°C 14-Lead P-DIP N-14
AD7394AR 12 –40°C to +85°C 14-Lead SOIC R-14
AD7395AN 10 –40°C to +125°C 14-Lead P-DIP N-14
AD7395AR 10 –40°C to +125°C 14-Lead SOIC R-14
AD7395ARU 10 –40°C to +85°C 14-Lead Thin Shrink Small Outline Package (TSSOP) RU-14
The AD7394/AD7395 contains 709 transistors. The die size measures 70 mil × 99 mil.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD7394/AD7395 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper
ESD precautions are recommended to avoid performance degradation or loss of functionality.
–5–REV. 0
WARNING!
ESD SENSITIVE DEVICE
AD7394/AD7395
PIN FUNCTION DESCRIPTIONS
Pin
No. Name Function
1 AGND Analog Ground.
2V
3V
OUTA
REF
4 DGND Digital Ground. Should be tied to analog GND.
5 CS Chip Select, active low input. Disables shift register loading when high. Does not effect LDA or LDB operation.
6 CLK Clock input, positive edge clocks data into shift register, MSB data bit first.
7 SDI Serial Data Input, input data loads directly into the shift register.
8 LDA Load DAC register strobe, level sensitive active low. Transfers shift register data to DAC A register. Asyn-
9 RS Resets DAC register to zero condition or half-scale, depending on MSB pin logic level. Asynchronous active
10 LDB Load DAC register strobe, level-sensitive active low. Transfers shift register data to DAC B register. Asyn-
11 MSB Digital Input: Logic High presets DAC registers to half-scale 800
12 SHDN Active low shutdown control input. Does not affect register contents as long as power is present on V
13 V
14 V
DD
OUTB
DAC A Voltage Output.
DAC Reference voltage input terminal. Establishes DAC full-scale output voltage. Pin can be tied to V
DD
pin.
chronous active low input. See Control Logic Truth Table for operation.
low input.
chronous active low input. See Control Logic Truth Table for operation.
(sets MSB bit to one) when the RS pin is
strobed; Logic Low clears all DAC registers to zero (000
H
H
) when the RS pin is strobed.
DD
. New
data can be loaded into the shift register and DAC register during shutdown. When device is powered up the
most recent data loaded into the DAC register will control the DAC output.
Positive power supply input. Specified range of operation +2.7 V to +5.5 V
DAC B Voltage Output.
PIN CONFIGURATIONS
14
AGND
V
OUTA
V
REF
DGND
CS
CLK
SDI
1
2
AD7394
3
AD7395
4
TOP VIEW
(Not to Scale)
5
6
7
V
OUTB
13
V
DD
12
SHDN
11
MSB
10
LDB
9
RS
8
LDA
–6–
REV. 0
Typical Performance Characteristics–
AD7394/AD7395
1.5
1
0.5
0
INL – LSB
–0.5
–1
–1.5
0 1000500
TA = –558C
TA = +258C, +858C
1500 25002000 3000 40003500
CODE – Decimal
VDD = 3V
= 2.5V
V
REF
Figure 4. AD7394 Integral Nonlinearity Error vs. Code
35
AD7395
30
25
20
15
FREQUENCY
10
5
0
26 3828 30 32 34 36
SS = 200,
= 2.7V
V
DD
= 2.5V
V
REF
T
= +858C TO –408C
A
TEMPCO – ppm/8C
40
Figure 7. Full-Scale Output Tempco
Histogram
25
SS = 200 UNITS
= +258C
T
A
V
= 2.7V
20
DD
V
= 2.5V
REF
15
10
FREQUENCY
5
0
23 22 21
TOTAL UNADJUSTED ERROR – LSB
AD7394
01
Figure 5. Total Unadjusted Error
Histogram
0.6
AD7394
0.5
– Volts
VDD = 5.0V
T
= +258C
A
CODE = 768
H
0.4
0.3
INL – LSB
0.2
0.1
0
1 1.5 2 2.5 3 3.5 4 4.5
0 0.5 5
V
REF
Figure 8. Integral Nonlinearity Error
vs. V
REF
50
SS = 200 UNITS
= +258C
T
A
V
= 2.7V
DD
40
V
= 2.5V
REF
30
20
FREQEUENCY
10
0
–5
TOTAL UNAJUSTED ERROR – LSB
51015
0
AD7395
Figure 6. Total Unadjusted Error
Histogram
30
25
20
15
10
5
FSE – LSB
0
25
FULL SCALE ERROR
210
215
0
0.5 5
TOTAL UNADJUSTED
FULL SCALE ERROR
1 1.5 2 2.5 3 3.5 4 4.5
V
– Volts
REF
Figure 9. Full-Scale Error vs. V
AD7394
TA = +258C
REF
10
8
6
4
2
OUTPUT NOISE DENSITY – mV/ Hz
0
1 10 100k
100 1k 10k
FREQUENCY – Hz
VDD = 5V
V
= 2.5V
REF
= +258C
T
A
Figure 10. AD7394 Output Noise
Density vs. Frequency
140
VDD = 3V
135
130
VIN 3V TO 0V
125
120
– mA
DD
I
115
110
105
100
0 0.5 3
1 1.5 2 2.5
VIN – Volts
AD7394
VIN 0V TO 3V
Figure 11. Supply Current vs. Logic
Input Voltage
–7–REV. 0
5
4.5
4
V
3.5
3
2.5
2
LOGIC THRESHOLD – V
1.5
1
FROM LOW TO HIGH
LOGIC
V
FROM HIGH TO LOW
LOGIC
23 7
456
VDD – Volts
AD7394
Figure 12. Logic Threshold vs. Supply Voltage
AD7394/AD7395
GAIN – dB
0
25
250
100 1k
VDD = 5V
CODE = FFF
H
10k 100k
230
235
240
245
210
215
220
225
FREQUENCY – Hz
1800
1600
A: IDD = 2.7V, CODE = 555
1400
B: IDD = 2.7V, CODE = 3FF
C: VDD = 5.5V, CODE = 155
1200
D: VDD = 5.5V, CODE = 3FF
1000
– mA
800
DD
I
600
400
200
0
1k 10k 10M
A
100k 1M
CLOCK FREQUENCY – Hz
AD7394
H
H
H
H
D
C
B
Figure 13. Supply Current vs. Clock
Frequency
10
V
= 2.5V
REF
9
CODE = 800
8
7
6
5
4
3
2
CURRENT SOURCING – mA
1
0
210 29
Figure 16. AD7394 I
rent vs.
∆
H
VDD = 5V
VDD = 3V
28 27 26 25 24 23 22 21
D V
– LSB
OUT
Source Cur-
V
OUT
OUT
80
70
60
50
40
PSRR – dB
VDD = 3.0V, 65%
30
20
10
0
1 10 10k
100 1k
FREQUENCY – Hz
TA = +258C
VDD = 5.0V, 65%
Figure 14. AD7394 Power Supply
Rejection vs. Frequency
1.262
1.257
1.252
– Volts
OUT
1.247
V
1.242
0
1.237
VDD = +5V
V
= 2.5V
REF
T
= +258C
A
CODE = 800
5mV/DIV
TIME – 2ms/DIV
TO 7FF
H
H
Figure 17. Midscale Transition
Performance
20
18
16
VDD = 5V
14
12
10
8
6
CURRENT SINKING – mA
4
2
0
23 4 567 89
01 10
D V
Figure 15. AD7394 I
vs.
∆
V
OUT
V
CODE = 800
VDD = 3V
– LSB
OUT
Sink Current
OUT
REF
= 2.5V
H
Figure 18. AD7395 Reference Multiplying Bandwidth
1.4
1.2
– mV
1
OUT
0.8
0.6
0.4
0.2
NOMINAL CHANGE IN V
0
0 100 600
CODE = 000
HOURS OF OPERATION – 1508C
H
200 300 400 500
Figure 19. Long-Term Drift Accelerated by Burn-In
AD7394
CODE = FFF
H
–8–
REV. 0
AD7394/AD7395
N-CH
V
DD
V
OUT
AGND
P-CH
OPERATION
The AD7394 and AD7395 are a set of pin compatible, dual,
12-bit/10-bit digital-to-analog converters. These single-supply
operation devices consume less than 200 microamps of current
while operating from power supplies in the +2.7 V to +5.5 V
range, making them ideal for battery operated applications.
They contain a voltage-switched, 12-bit/10-bit, laser trimmed
digital-to-analog converter, rail-to-rail output op amps, two
DAC registers and a serial input shift register. The external
reference input has constant input resistance independent of the
digital code setting of the DAC. In addition, the reference input
can be tied to the same supply voltage as V
maximum output voltage span of 0 to V
, resulting in a
DD
. The serial interface
DD
consists of a serial data input (SDI), clock (CLK) and chip
select pin (CS) and two load DAC Register pins (LDA and
LDB). A reset (RS) pin is available to reset the DAC register to
zero scale or midscale, depending on the digital level applied to
the MSB pin. This function is useful for power-on reset or
system failure recovery to a known state. Additional power
savings are accomplished by activating the SHDN pin resulting
in a 1.5 µA maximum consumption sleep mode.
D/A CONVERTER SECTION
The voltage switched R-2R DAC generates an output voltage
dependent on the external reference voltage connected to the
REF pin according to the following equation:
× D
V
V
OUT
REF
=
N
2
(1)
where D is the decimal data word loaded into the DAC register
and N is the number of bits of DAC resolution. In the case of
the 10-bit AD7395 using a 2.5 V reference, Equation 1 simplifies to:
AMPLIFIER SECTION
The internal DAC’s output is buffered by a low power con-
sumption precision amplifier. The op amp has a 60 µs typical
settling time to 0.1% of full scale. There are slight differences in
settling time for negative slewing signals versus positive. Also,
negative transition settling time to within the last 6 LSBs of zero
volts has an extended settling time. The rail-to-rail output stage
of this amplifier has been designed to provide precision performance while operating near either power supply. Figure 20
shows an equivalent output schematic of the rail-to-rail-amplifier with its N-channel pull-down FETs that will pull an output
load directly to GND. The output sourcing current is provided
by a P-channel pull-up device that can source current to GND
terminated loads.
Figure 20. Equivalent Analog Output Circuit
The rail-to-rail output stage provides more than ±1 mA of out-
put current. The N-channel output pull-down MOSFET shown
in Figure 20 has a 35 Ω ON resistance, which sets the sink cur-
rent capability near ground. In addition to resistive load driving
capability, the amplifier has also been carefully designed and
characterized for up to 100 pF capacitive load driving capability.
OUT
2.5 × D
=
1024
OUT
(2)
is
V
Using Equation 2 the nominal midscale voltage at V
1.25 V for D = 512; full-scale voltage is 2.497 V. The LSB step
size is = 2.5 × 1/1024 = 0.0024 V.
For the 12-bit AD7394 operating from a 5.0 V reference Equation 1 becomes:
OUT
5.0 × D
=
4096
(3)
V
Using Equation 3 the AD7394 provides a nominal midscale
voltage of 2.50 V for D = 2048, and a full-scale output of
4.998 V. The LSB step size is = 5.0 × 1/4096 = 0.0012 V.
REFERENCE INPUT
The reference input terminal has a constant input resistance
independent of digital code which results in reduced glitches on
the external reference voltage source. The high 2.5 MΩ input
resistance minimizes power dissipation within the AD7394/
AD7395 D/A converters. The V
ranging from ground to the positive supply voltage V
input accepts input voltages
REF
. One of
DD
the simplest applications, which saves an external reference
voltage source, is connection of the V
V
supply. This connection results in a rail-to-rail voltage
DD
terminal to the positive
REF
output span maximizing the programmed range. The reference
input will accept ac signals as long as they are kept within the
supply voltage range, 0 < V
< VDD. The reference bandwidth
REF
and integral nonlinearity error performance are plotted in the
Typical Performance Characteristics section (see Figures 8 and
18). The ratiometric reference feature makes the AD7394/AD7395
an ideal companion to ratiometric analog-to-digital converters
such as the AD7896.
–9–REV. 0
AD7394/AD7395
POWER SUPPLY
The very low power consumption of the AD7394/AD7395 is a
direct result of a circuit design optimizing the use of a CBCMOS
process. By using the low power characteristics of CMOS for
the logic, and the low noise, tight matching of the complementary bipolar transistors, excellent analog accuracy is achieved.
One advantage of the rail-to-rail output amplifiers used in the
AD7394/AD7395 is the wide range of usable supply voltage.
The part is fully specified and tested for operation from +2.7 V
to +5.5 V.
POWER SUPPLY BYPASSING AND GROUNDING
Local supply bypassing consisting of a 10 µF tantalum electro-
lytic in parallel with a 0.1 µF ceramic capacitor is recommended
in all applications (Figure 21).
+2.7V TO +5.5V
C
*
CS
LDA, B
CLK
SDI
RS
*OPTIONAL EXTERNAL
REFERENCE BYPASS
REF V
AD7394
OR
AD7395
DGND
DD
AGND
0.1mF
10mF
V
V
OUTA
OUTB
Figure 21. Recommended Supply Bypassing for the
AD7394/AD7395
INPUT LOGIC LEVELS
All digital inputs are protected with a Zener-type ESD protection structure (Figure 22) that allows logic input voltages to
exceed the V
supply voltage. This feature can be useful if the
DD
user is driving one or more of the digital inputs with a 5 V CMOS
logic input-voltage level while operating the AD7394/AD7395
on a +3 V power supply. If this mode of interface is used, make
sure that the V
of the 5 V CMOS meets the VIL input re-
OL
quirement of the AD7394/AD7395 operating at 3 V. See Figure
12 for a graph of digital logic input threshold versus operating
V
supply voltage.
DD
V
DD
LOGIC
IN
GND
Figure 22. Equivalent Digital Input ESD Protection
In order to minimize power dissipation from input logic levels
that are near the V
and VIL logic input voltage specifications,
IH
a Schmitt trigger design was used that minimizes the inputbuffer current consumption compared to traditional CMOS
input stages. Figure 11 is a plot of incremental input voltage
versus supply current showing that negligible current consumption takes place when logic levels are in their quiescent state.
The normal crossover current still occurs during logic transitions. A secondary advantage of this Schmitt trigger is the prevention of false triggers that would occur with slow moving
logic transitions when a standard CMOS logic interface or opto
isolators are used. The logic inputs SDI, CLK, CS, LDA, LDB,
RS, SHDN all contain the Schmitt trigger circuits.
CS
CLK
SDI
EN
SHIFT
REGISTER
DAC A REGISTER
DPR
Q
LDA LDB RS
DAC B REGISTER
DPR
MSB
Figure 23. Equivalent Digital Interface Logic
DIGITAL INTERFACE
The AD7394/AD7395 has a serial data input. A functional
block diagram of the digital section is shown in Figure 23, while
Table I contains the truth table for the logic control inputs.
Three pins control the serial data input register loading. Two
additional pins determine which DAC will receive the data
loaded into the input shift register. Data at the SDI is clocked
into the shift register on the rising edge of the CLK. Data is
entered in the MSB-first format. The active low chip select (CS)
pin enables loading of data into the shift register from the SDI
pin. Twelve clock pulses are required to load the 12-bit AD7390
DAC shift register. If additional bits are clocked into the shift
register, for example, when a microcontroller sends two 8-bit
bytes, the MSBs are ignored (Table IV). The lowest resolution
AD7395 is also loaded MSB-first with 10 bits of data. Again, if
additional bits are clocked into the shift register only the last 10
bits clocked in are used. When CS returns to logic high, shiftregister loading is disabled. The load pins LDA and LDB control the flow of data from the shift register to the DAC register.
After a new value is clocked into the serial-input register, it will
be transferred to the DAC register associated with its LDA or
LDB logic control line. Note, if the user wants to load both
DAC registers with the current contents of the shift register,
both control lines LDA and LDB should be strobed together.
The LDA and LDB pins are level-sensitive and should be returned to logic high prior to any new data being sent to the
input shift register to avoid changing the DAC register values.
See Truth Table for complete set of conditions.
RESET (RS) PIN
Forcing the asynchronous RS pin low will set the DAC register
to all zeros, or midscale, depending on the logic level applied to
the MSB pin. When the MSB pin is set to logic high, both DAC
registers will be reset to midscale (i.e., the DAC Register’s MSB
bit will be set to Logic 1 followed by all zeros). The reset function is useful for setting the DAC outputs to zero at power-up or
after a power supply interruption. Test systems and motor
controllers are two of many applications that benefit from
powering up to a known state. The external reset pulse can be
–10–
REV. 0
AD7394/AD7395
Table IV. Typical Microcontroller Interface Formats
MSB BYTE 1 LSB MSB BYTE 0 LSB
B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
X X X X D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
XXXXXXD9D8D7D6D5D4D3D2D1D0
D11–D0: 12-bit AD7394 DAC data; D9–D0: 10-bit AD7395 DAC data; X = Don’t Care; The MSB of byte 1 is the first bit that is loaded into the SDI input.
generated by the microprocessor’s power-on RESET signal, by
an output from the microprocessor, or by an external resistor
and capacitor. RESET has a Schmitt trigger input which results
in a clean reset function when using external resistor/capacitor
generated pulses. See the Control-Logic Truth Table I.
POWER SHUTDOWN (SHDN)
Maximum power savings can be achieved by using the power
shutdown control function. This hardware activated feature is
controlled by the active low input SHDN pin. This pin has a
Schmitt trigger input which helps to desensitize it to slowly
changing inputs. By placing a logic low on this pin the internal
consumption of the device is reduced to nano amp levels, guar-
anteed to 1.5 µA maximum over the operating temperature
range. When the AD7394/AD7395 has been programmed into
the power shutdown state, the present DAC register data is
maintained as long as V
remains greater than 2.7 V. Once a
DD
wake-up command SHDN = 1 is given, the DAC voltage outputs will return to their previous values. It typically takes
80 microseconds for the output voltage to fully stabilize. In the
shutdown state the DAC output amplifier exhibits an opencircuit with a nominal output resistance of 500 kΩ to ground. If
the power shutdown feature is not needed, then the user should
tie the SHDN pin to the V
voltage thereby disabling this
DD
function.
UNIPOLAR OUTPUT OPERATION
This is the basic mode of operation for the AD7394. As shown
in Figure 24, the AD7394 has been designed to drive loads as
low as 5 kΩ in parallel with 100 pF. The code table for this
operation is shown in Table V.
+2.7V TO +5.5V
R
75kV
75kV
0.1mF10mF
V
V
OUTA
OUTB
100pF
100pF
0.01mF
EXT
REF
mC
5
V
V
REF
DIGITAL
DGND AGND
DD
DAC A
DAC B
DIGITAL INTERFACE
CIRCUITRY OMITTED
FOR CLARITY.
Figure 24. AD7394 Unipolar Output Operation
Table V. Unipolar Code Table
Hexadecimal Decimal Output
Number Number Voltage (V)
in DAC Register in DAC Register [V
REF
= 2.5 V]
FFF 4095 2.4994
801 2049 1.2506
800 2048 1.2500
7FF 2047 1.2494
000 0 0
The circuit can be configured with an external reference plus
power supply, or powered from a single dedicated regulator or
reference depending on the application performance requirements.
BIPOLAR OUTPUT OPERATION
Although the AD7395 has been designed for single-supply operation, the output can easily be configured for bipolar operation. A typical circuit is shown in Figure 25. This circuit uses a
clean regulated +5 V supply for power, which also provides the
circuit’s reference voltage. Since the AD7395 output span swings
from ground to very near +5 V, it is necessary to choose an
external amplifier with a common-mode input voltage range that
extends to its positive supply rail. The micropower consumption
OP196 has been designed just for this purpose and results in
only 50 microamps of maximum current consumption. Connec-
tion of the equally valued 470 kΩ resistors results in a differen-
tial amplifier mode of operation with a voltage gain of two,
which produces a circuit output span of ten volts, that is, –5 V to
+5 V. As the DAC is programmed from zero code 000
scale 200
to full-scale 3FFH, the circuit output voltage VO is
H
set at –5 V, 0 V and +5 V (–1 LSB). The output voltage V
to mid-
H
is
O
coded in offset binary according to Equation 4.
OUT
=
512
V
D
–1
×5
(4)
where D is the decimal code loaded in the AD7395 DAC register. Note that the LSB step size is 10/1024 = 10 mV. This circuit has been optimized for micropower consumption including
the 470 kΩ gain setting resistors, which should have low tem-
perature coefficients to maintain accuracy and matching (preferably the same resistor material, such as metal film). If better
stability is required, the power supply could be substituted with
a precision reference voltage such as the low dropout REF195,
which can easily supply the circuit’s 262 microamps of current,
and still provide additional power for the load connected to
V
. The micropower REF195 is guaranteed to source 10 mA
OUT
–11–REV. 0
AD7394/AD7395
output drive current, but consumes only 50 microamps internally. If higher resolution is required, the AD7394 can be used
with the addition of two more bits of data inserted into the
software coding, which would result in a 2.5 mV LSB step size.
Table VI shows examples of nominal output voltages, V
, pro-
O
vided by the Bipolar Operation circuit application.
I
< 262mA
SY
+5V
REF V
C
200mA
DD
AD7395
GND
470kV 470kV
V
OUTA
ONLY ONE CHANNEL SHOWN.
DIGITAL INTERFACE CIRCUITRY
OMITTED FOR CLARITY.
OP196
25V
< 50mA
V
O
+5V
–5V
BIPOLAR
OUTPUT
SWING
Figure 25. Bipolar Output Operation
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
Table VI. Bipolar Code Table
Hexadecimal Number Decimal Number Analog Output
in DAC Register in DAC Register Voltage (V)
3FF 1023 4.9902
201 513 0.0097
200 512 0.0000
1FF 511 –0.0097
000 0 –5.0000
C3323–8–4/98
0.210 (5.33)
MAX
0.160 (4.06)
0.115 (2.93)
0.1574 (4.00)
0.1497 (3.80)
0.0098 (0.25)
0.0040 (0.10)
SEATING
Plastic DIP Package
(N-14)
0.795 (20.19)
0.725 (18.42)
14
17
PIN 1
0.022 (0.558)
0.014 (0.356)
0.100
(2.54)
BSC
8
0.070 (1.77)
0.045 (1.15)
SOIC Package
(R-14)
0.3444 (8.75)
0.3367 (8.55)
14 8
71
PLANE
PIN 1
0.0500
(1.27)
BSC
0.0688 (1.75)
0.0532 (1.35)
0.0192 (0.49)
0.0138 (0.35)
0.280 (7.11)
0.240 (6.10)
0.060 (1.52)
0.015 (0.38)
0.130
(3.30)
MIN
SEATING
PLANE
0.2440 (6.20)
0.2284 (5.80)
0.0099 (0.25)
0.0075 (0.19)
0.325 (8.25)
0.300 (7.62)
0.015 (0.381)
0.008 (0.204)
0.0196 (0.50)
0.0099 (0.25)
88
08
0.0500 (1.27)
0.0160 (0.41)
0.195 (4.95)
0.115 (2.93)
3 458
0.177 (4.50)
0.169 (4.30)
0.006 (0.15)
0.002 (0.05)
SEATING
PLANE
Thin Surface Mount TSSOP Package
(RU-14)
0.201 (5.10)
0.193 (4.90)
14 8
0.256 (6.50)
0.246 (6.25)
1
PIN 1
0.0256
(0.65)
BSC
7
0.0118 (0.30)
0.0075 (0.19)
0.0433
(1.10)
MAX
0.0079 (0.20)
0.0035 (0.090)
88
08
0.028 (0.70)
0.020 (0.50)
PRINTED IN U.S.A.
–12–
REV. 0
Loading...