2
D
11
781-461-3113
LC
MOS
Quad 8-Bit D/A Converter
AD7226
FEATURES
Four 8-Bit DACs with Output Amplifiers
Skinny 20-Lead DIP, SOIC, SSOP, and PLCC Packages
Microprocessor-Compatible
TTL/CMOS-Compatible
No User Trims
Extended Temperature Range Operation
Single Supply Operation Possible
APPLICATIONS
Process Control
Automatic Test Equipment
Automatic Calibration of Large System Parameters,
e.g., Gain/Offset
GENERAL DESCRIPTION
The AD7226 contains four 8-bit voltage-output digital-toanalog converters, with output buffer amplifiers and interface
logic on a single monolithic chip. No external trims are required
to achieve full specified performance for the part.
Separate on-chip latches are provided for each of the four D/A
converters. Data is transferred into one of these data latches
through a common 8-bit TTL/CMOS (5 V) compatible input
port. Control inputs A0 and A1 determine which DAC is
loaded when WR goes low. The control logic is speed-compatible with most 8-bit microprocessors.
Each D/A converter includes an output buffer amplifier capable
of driving up to 5 mA of output current. The amplifiers’ offsets
are laser-trimmed during manufacture, thereby eliminating any
requirement for offset nulling.
Specified performance is guaranteed for input reference voltages
from 2 V to 12.5 V with dual supplies. The part is also specified
for single supply operation at a reference of 10 V.
The AD7226 is fabricated in an all ion-implanted high speed
Linear Compatible CMOS (LC
2
MOS) process, which has been
specifically developed to allow high speed digital logic circuits
and precision analog circuits to be integrated on the same chip.
FUNCTIONAL BLOCK DIAGRAM
MSB
DATA
(8-BIT)
LSB
WR
V
REF
LATCH A
D
A
LATCH B
T
A
B
LATCH C
U
S
LATCH D
CONTROL
A1
A0
LOGIC
V
SS
DAC A
DAC B
DAC C
DAC D
AGND AGND
AD7226
V
DD
A
B
C
D
V
OUT
V
OUT
V
OUT
V
OUT
PRODUCT HIGHLIGHTS
1. DAC-to-DAC Matching
Since all four DACs are fabricated on the same chip at the
same time, precise matching and tracking between the DACs
is inherent.
2. Single-Supply Operation
The voltage mode configuration of the DACs allows the
AD7226 to be operated from a single power supply rail.
3. Microprocessor Compatibility
The AD7226 has a common 8-bit data bus with individual
DAC latches, providing a versatile control architecture for
simple interface to microprocessors. All latch enable signals
are level triggered.
4. Small Size
Combining four DACs and four op amps plus interface logic
into a 20-pin package allows a dramatic reduction in board
space requirements and offers increased reliability in systems
using multiple converters. Its pinout is aimed at optimizing
board layout with all the analog inputs and outputs at one
end of the package and all the digital inputs at the other.
A
B
C
D
REV.
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 www.analog.com
Fax: © 20 Analog Devices, Inc. All rights reserved.
AD7226* Product Page Quick Links
Comparable Parts
View a parametric search of comparable parts
Documentation
Application Notes
• AN-317: Circuit Applications of the AD7226 Quad CMOS
DAC
• AN-321: 3-Phase Sine Wave Generation Using the AD7226
Quad DAC
Data Sheet
• AD7226: Military Data Sheet
• AD7226: LC2MOS Quad 8-Bit D/A Converter Data Sheet
Reference Materials
Solutions Bulletins & Brochures
• Digital to Analog Converters ICs Solutions Bulletin
Last Content Update: 08/30/2016
Design Resources
• AD7226 Material Declaration
• PCN-PDN Information
• Quality And Reliability
• Symbols and Footprints
Discussions
View all AD7226 EngineerZone Discussions
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Technical Support
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number
* This page was dynamically generated by Analog Devices, Inc. and inserted into this data sheet. Note: Dynamic changes to
the content on this page does not constitute a change to the revision number of the product data sheet. This content may be
frequently modified.
(VDD = 11.4 V to 16.5 V, VSS = –5 V 10%, AGND = DGND = 0 V; V
D
AD7226–SPECIFICATIONS
unless otherwise noted. All Specifications T
MIN
to T
unless otherwise noted.)
MAX
DUAL SUPPLY
Parameter K, B Versions
STATIC PERFORMANCE
Resolution 8 Bits
Total Unadjusted Error ± 1LSB maxV
Relative Accuracy ± 0.5 LSB max
Differential Nonlinearity ± 1LSB max Guaranteed Monotonic
Full-Scale Error ± 0.5 LSB max
Full-Scale Temperature Coefficient ± 20 ppm/∞C typ V
Zero Code Error ± 20 mV max
Zero Code Error Temperature Coefficient ±50 mV/∞C typ
REFERENCE INPUT
Voltage Range 2 to (VDD – 4) V min to V max
Input Resistance 2 kW min
Input Capacitance
3
50 pF min Occurs when each DAC is loaded with all 0s.
200 pF max Occurs when each DAC is loaded with all 1s.
DIGITAL INPUTS
Input High Voltage, V
Input Low Voltage, V
INL
INH
2.4 V min
0.8 V max
Input Leakage Current ± 1 mA max V
Input Capacitance 8 pF max
Input Coding Binary
DYNAMIC PERFORMANCE
Voltage Output Slew Rate
Voltage Output Settling Time
4
4
2.5 V/ms min
4 ms max V
Digital Crosstalk 10 nV secs typ
Minimum Load Resistance 2 kW min V
POWER SUPPLIES
VDD Range 11.4/16.5 V min/V max For Specified Performance
I
DD
I
SS
SWITCHING CHARACTERISTICS
Address to Write Setup Time, t
Address to Write Hold Time, t
Data Valid to Write Setup Time, t
Data Valid to Write Hold Time, t
Write Pulsewidth, t
NOTES
1
Maximum possible reference voltage.
2
Temperature ranges are as follows:
3
Guaranteed by design. Not production tested.
4
Sample Tested at 25∞C to ensure compliance.
5
Switching Characteristics apply for single and dual supply operation.
Specifications subject to change without notice.
K Version: –40∞C to +85∞C
B Version: –40∞C to +85∞C
WR
AS
AH
DS
DH
13 mA max Outputs Unloaded; VIN = V
11 mA max Outputs Unloaded; VIN = V
4, 5
0ns min
0ns min
50 ns min
0ns min
50 ns min
2
Unit Conditions/Comments
= 15 V ± 5%, V
DD
= 14 V to 16.5 V, V
DD
= 0 V or V
IN
= 10 V; Settling Time to ± 1/2 LSB
REF
= 10 V
OUT
DD
= +2 V to (V
REF
= 10 V
REF
REF
– 4 V)1,
DD
= +10 V
or V
INL
or V
INL
INH
INH
REV.–2–
AD7226
D
(VDD = 15 V 5%, VSS = AGND = DGND = O V; V
SINGLE SUPPLY
All specifications T
MIN
to T
unless otherwise noted.)
MAX
Parameter K, B Versions
2
= 10 V1 unless otherwise noted.
REF
Unit Conditions/Comments
STATIC PERFORMANCE
Resolution 8 Bits
Total Unadjusted Error ± 2LSB max
Differential Nonlinearity ± 1LSB max Guaranteed Monotonic
REFERENCE INPUT
Input Resistance 2 kW min
Input Capacitance
3
50 pF min Occurs when each DAC is loaded with all 0s.
200 pF max Occurs when each DAC is loaded with all 1s.
DIGITAL INPUTS
Input High Voltage, V
Input Low Voltage, V
INH
INL
Input Leakage Current ± 1 mA max V
2.4 V min
0.8 V max
= 0 V or V
IN
DD
Input Capacitance 8 pF max
Input Coding Binary
DYNAMIC PERFORMANCE
Voltage Output Slew Rate
Voltage Output Settling Time
4
4
2V/ms min
4 ms max Settling Time to ± 1/2 LSB
Digital Crosstalk 10 nV secs typ
Minimum Load Resistance 2 kW min V
= +10 V
OUT
POWER SUPPLIES
VDD Range 14.25/15.75 V min/V max For Specified Performance
I
DD
NOTES
1
Maximum possible reference voltage.
2
Temperature ranges are as follows:
K Version: –40∞C to +85∞C
B Version: –40∞C to +85∞C
3
Guaranteed by design. Not production tested.
4
Sample Tested at 25∞C to ensure compliance.
Specifications subject to change without notice.
13 mA max Outputs Unloaded; VIN = V
ABSOLUTE MAXIMUM RATINGS
1
VDD to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, +17 V
to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, +17 V
V
DD
to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –7 V, V
V
SS
VSS to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –7 V, V
VDD to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, +24 V
AGND to DGND . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, V
Digital Input Voltage to DGND . . . . . . . –0.3 V, VDD + 0.3 V
to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, V
V
REF
V
to AGND2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . VSS, V
OUT
Power Dissipation (Any Package) to 75∞C . . . . . . . . . . 500 mW
Derates above 75∞C by . . . . . . . . . . . . . . . . . . . . . 2.0 mW/∞C
Operating Temperature
Commercial (K Version) . . . . . . . . . . . . . . . –40∞C to +85∞C
Industrial (B Version) . . . . . . . . . . . . . . . . . –40∞C to +85∞C
Storage Temperature . . . . . . . . . . . . . . . . . . . –65∞C to +150∞C
Lead Temperature (Soldering, 10 secs) . . . . . . . . . . . . . 300∞C
NOTES
1
Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only, functional operation of the
device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
2
Outputs may be shorted to AGND provided that the power dissipation of the
package is not exceeded. Typically short circuit current to AGND is 50 mA.
INL
or V
INH
DD
DD
DD
DD
DD
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although the
AD7226 features proprietary ESD protection circuitry, permanent damage may occur on devices
subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended
to avoid performance degradation or loss of functionality.
REV.
–3–
AD7226
D
PIN CONFIGURATIONS
DIP and SOIC/SSOP
DB7 (MSB)
V
REF
AGND
DGND
DB7 (MSB)
DB8
BV
V
1
OUT
V
A
2
OUT
V
3
SS
4
V
REF
5
AGND
DGND
DB6
DB5
DB4
AD7226
TOP VIEW
6
(Not to Scale)
7
8
9
10
20
V
19
V
18
A0
17
A1
16
15
WR
14
DB0(LSB)
DB1
13
12
DB2
11
DB3
OUT
OUT
DD
C
D
PLCC
B
C
OUT
V
DB3
V
OUT
DB2
D
V
OUT
DB1
18
V
17
A0
16
A1
15
WR
14
DB0(LSB)
DD
SSVOUT
V
3 2 1 20 19
4
5
6
(Not to Scale)
7
8
9 10 11 12 13
DB5
A
AD7226
TOP VIEW
DB4
TERMINOLOGY
TOTAL UNADJUSTED ERROR
This is a comprehensive specification that includes full-scale
error, relative accuracy and zero code error. Maximum output
voltage is V
256. The LSB size will vary over the V
code error will, relative to the LSB size, increase as V
– 1 LSB (ideal), where 1 LSB (ideal) is V
REF
range. Hence the zero
REF
REF
/
REF
decreases.
Accordingly, the total unadjusted error, which includes the zero
code error, will also vary in terms of LSB’s over the V
REF
range.
As a result, total unadjusted error is specified for a fixed reference voltage of 10 V.
RELATIVE ACCURACY
Relative Accuracy or endpoint nonlinearity, is a measure of the
maximum deviation from a straight line passing through the
endpoints of the DAC transfer function. It is measured after
allowing for zero and full-scale error and is normally expressed
in LSB’s or as a percentage of full-scale reading.
DIFFERENTIAL NONLINEARITY
Differential Nonlinearity is the difference between the measured
change and the ideal 1 LSB change between any two adjacent
codes. A specified differential nonlinearity of ± 1 LSB max over
the operating temperature range ensures monotonicity.
DIGITAL CROSSTALK
The glitch impulse transferred to the output of one converter
due to a change in the digital input code to another of the converters. It is specified in nV secs and is measured at V
REF
= 0 V.
FULL SCALE ERROR
Full-Scale Error is defined as:
Measured Value – Zero Code Error – Ideal Value
REV.–4–
AD7226
D
CIRCUIT INFORMATION D/A SECTION
The AD7226 contains four identical, 8-bit, voltage mode digital-toanalog converters. The output voltages from the converters have the
same polarity as the reference voltage allowing single supply operation. A novel DAC switch pair arrangement on the AD7226 allows a
reference voltage range from 2 V to 12.5 V.
Each DAC consists of a highly stable, thin-film, R-2R ladder
and eight high speed NMOS, single-pole, double-throw
switches. The simplified circuit diagram for one channel is
shown in Figure 1. Note that V
(Pin 4) and AGND (Pin 5)
REF
are common to all four DACs.
V
OUT
V
REF
AGND
RRR
2R 2R 2R 2R 2R
DB0 DB5 DB6 DB7
SHOWN FOR ALL 1s ON DAC
Figure 1. D/A Simplified Circuit Diagram
The input impedance at the V
pin of the AD7226 is the
REF
parallel combination of the four individual DAC reference input
impedances. It is code dependent and can vary from 2 kW to
infinity. The lowest input impedance (i.e., 2 KW) occurs when
all four DACs are loaded with the digital code 01010101.
Therefore, it is important that the reference presents a low
output impedance under changing load conditions. The nodal
capacitance at the reference terminals is also code dependent
and typically varies from 100 pF to 250 pF.
Each V
pin can be considered as a digitally programmable
OUT
voltage source with an output voltage of:
VDV
=
OUTX X REF
(1)
where DX is fractional representation of the digital input code
and can vary from 0 to 255/256.
The source impedance is the output resistance of the buffer
amplifier.
OP AMP SECTION
Each voltage-mode D/A converter output is buffered by a unity
gain, noninverting CMOS amplifier. This buffer amplifier is
capable of developing 10 V across a 2 kW load and can drive
capacitive loads of 3300 pF. The output stage of this amplifier
consists of a bipolar transistor from the V
load to the V
, the negative supply for the output amplifiers.
SS
line and a current
DD
This output stage is shown in Figure 2.
The NPN transistor supplies the required output current drive
(up to 5 mA). The current load consists of NMOS transistors
which normally act as a constant current sink of 400 mA to V
,
SS
giving each output a current sink capability of approximately
400 mA if required.
The AD7226 can be operated single or dual supply resulting
in different performance in some parameters from the output
amplifiers.
In single supply operation (V
= 0 V = AGND), with the out-
SS
put approaching AGND (i.e., digital code approaching all 0s)
V
DD
I/P
O/P
400A
V
SS
Figure 2. Amplifier Output Stage
the current load ceases to act as a current sink and begins to act
as a resistive load of approximately 2 kW to AGND. This occurs
as the NMOS transistors come out of saturation. This means
that, in single supply operation, the sink capability of the amplifiers is reduced when the output voltage is at or near AGND. A
typical plot of the variation of current sink capability with output voltage is shown in Figure 3.
500
VSS = –5V
400
300
(A)
V
= 0
200
100
0
0102
SS
SINK
I
Figure 3. Variation of I
468
V
OUT
(V)
SINK
VDD = +15V
with V
OUT
If the full sink capability is required with output voltages at or
near AGND (= 0 V), then V
can be brought below 0 V by 5 V
SS
and thereby maintain the 400 mA current sink as indicated in
Figure 3. Biasing V
below 0 V also gives additional headroom
SS
in the output amplifier which allows for better zero code error
performance on each output. Also improved is the slew rate and
negative-going settling time of the amplifiers (discussed later).
Each amplifier offset is laser trimmed during manufacture to
eliminate any requirement for offset nulling.
DIGITAL SECTION
The digital inputs of the AD7226 are both TTL and CMOS
(5 V) compatible from V
= 11.4 V to 16.5 V. All logic inputs
DD
are static protected MOS gates with typical input currents of
less than 1 nA. Internal input protection is achieved by an
on-chip distributed diode from DGND to each MOS gate. To
minimize power supply currents, it is recommended that the
digital input voltages be driven as close to the supply rails (V
DD
and DGND) as practically possible.
REV.
–5–
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