Waveform Generator
AD5932
Rev. A
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AD5932
DVDD CAP/2.5V DGND INTERRUPT ST
ANDBY AGND AVDD
VCC
2.5V
SYNC
MCLK
CTRL
FSYNC
SYNCOUT
MSBOUT
VOUT
COMP
SCLK SDATA
DATAAND CONTROL
FREQUENCY
CONTROLLER
INCREMENT
CONTROLLER
CONTROL
REGISTER
ON-BOARD
REFERENCE
FULL-SCALE
CONTROL
24-BIT
PIPELINED
DDS CORE
10-BIT
DAC
SERIAL INTERFACE
REGULATOR
DATA INCR
BUFFER
BUFFER
/
24
05416-001
Data Sheet
FEATURES
Programmable frequency profile
No external components necessary
Output frequency up to 25 MHz
Burst-and-listen capability
Preprogrammable frequency profile minimizes number of
DSP/microcontroller writes
Sinusoidal/triangular/square wave outputs
Automatic or single pin control of frequency stepping
Power-down mode: 20 µA
Power supply: 2.3 V to 5.5 V
Automotive temperature range: −40°C to +125°C
16-lead, Pb-free TSSOP
APPLICATIONS
Frequency scanning/radar
Network/impedance measurements
Incremental frequency stimulus
Sensory applications
Proximity and motion
Programmable Frequency Scan
GENERAL DESCRIPTION
The AD59321 is a waveform generator offering a programmable
frequency scan. Utilizing embedded digital processing that
allows enhanced frequency control, the device generates
synthesized analog or digital frequency-stepped waveforms.
Because frequency profiles are preprogrammed, continuous
write cycles are eliminated, thereby freeing up valuable
DSP/microcontroller resources. Waveforms start from a known
phase and are incremented phase-continuously, which allows
phase shifts to be easily determined. Consuming only 6.7 mA,
the AD5932 provides a convenient low power solution to
waveform generation.
The AD5932 outputs each frequency in the range of interest for
a defined length of time and then steps to the next frequency in
the scan range. The length of time the device outputs a particular
frequency is preprogrammed, and the device increments the
frequency automatically; or, alternatively, the frequency is
incremented externally via the CTRL pin. At the end of the
range, the AD5932 continues to output the last frequency until
the device is reset. The AD5932 also offers a digital output via
the MSBOUT pin.
(continued on Page 3)
FUNCTIONAL BLOCK DIAGRAM
1
Protected by U.S. patent number 6747583.
Information furnishe d by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Figure 1.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
AD5932* Product Page Quick Links
Comparable Parts
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Evaluation Kits
• AD5932 Evaluation Board
Last Content Update: 08/30/2016
Documentation
Application Notes
• AN-1044: Programming the AD5932 for Frequency Sweep
and Single Frequency Outputs
• AN-1248: SPI Interface
• AN-1389: Recommended Rework Procedure for the Lead
Frame Chip Scale Package (LFCSP)
• AN-237: Choosing DACs for Direct Digital Synthesis
• AN-280: Mixed Signal Circuit Technologies
• AN-342: Analog Signal-Handling for High Speed and
Accuracy
• AN-345: Grounding for Low-and-High-Frequency Circuits
• AN-419: A Discrete, Low Phase Noise, 125 MHz Crystal
Oscillator for the AD9850
• AN-423: Amplitude Modulation of the AD9850 Direct
Digital Synthesizer
• AN-543: High Quality, All-Digital RF Frequency
Modulation Generation with the ADSP-2181 and the
AD9850 DDS
• AN-557: An Experimenter's Project:
• AN-587: Synchronizing Multiple AD9850/AD9851 DDSBased Synthesizers
• AN-605: Synchronizing Multiple AD9852 DDS-Based
Synthesizers
• AN-621: Programming the AD9832/AD9835
• AN-632: Provisionary Data Rates Using the AD9951 DDS
as an Agile Reference Clock for the ADN2812 ContinuousRate CDR
• AN-769: Generating Multiple Clock Outputs from the
AD9540
• AN-772: A Design and Manufacturing Guide for the Lead
Frame Chip Scale Package (LFCSP)
• AN-823: Direct Digital Synthesizers in Clocking
Applications Time
• AN-837: DDS-Based Clock Jitter Performance vs. DAC
Reconstruction Filter Performance
• AN-843: Measuring a Loudspeaker Impedance Profile
Using the AD5933
• AN-847: Measuring a Grounded Impedance Profile Using
the AD5933
• AN-851: A WiMax Double Downconversion IF Sampling
Receiver Design
• AN-927: Determining if a Spur is Related to the DDS/DAC
or to Some Other Source (For Example, Switching
Supplies)
• AN-939: Super-Nyquist Operation of the AD9912 Yields a
High RF Output Signal
• AN-953: Direct Digital Synthesis (DDS) with a
Programmable Modulus
Data Sheet
• AD5932: Programmable Frequency Scan Waveform
Generator Data Sheet
Product Highlight
• Introducing Digital Up/Down Converters: VersaCOMM™
Reconfigurable Digital Converters
User Guides
• UG-796: Evaluation Board for Programmable Single-Scan
Waveform Generator
Software and Systems Requirements
• AD5932 Evaluation Software
Tools and Simulations
• ADIsimDDS (Direct Digital Synthesis) - BETA
Reference Materials
Technical Articles
• 400-MSample DDSs Run On Only +1.8 VDC
• ADI Buys Korean Mobile TV Chip Maker
• Basics of Designing a Digital Radio Receiver (Radio 101)
• Clock Requirements For Data Converters
• DDS Applications
• DDS Circuit Generates Precise PWM Waveforms
• DDS Design
• DDS Device Produces Sawtooth Waveform
• DDS Device Provides Amplitude Modulation
• DDS IC Initiates Synchronized Signals
• DDS IC Plus Frequency-To-Voltage Converter Make LowCost DAC
• DDS Simplifies Polar Modulation
• Digital Potentiometers Vary Amplitude In DDS Devices
• Digital Up/Down Converters: VersaCOMM™ White Paper
• Digital Waveform Generator Provides Flexible Frequency
Tuning for Sensor Measurement
• Improved DDS Devices Enable Advanced Comm Systems
• Integrated DDS Chip Takes Steps To 2.7 GHz
• Simple Circuit Controls Stepper Motors
• Speedy A/Ds Demand Stable Clocks
• Synchronized Synthesizers Aid Multichannel Systems
• The Year of the Waveform Generator
• Two DDS ICs Implement Amplitude-shift Keying
• Video Portables and Cameras Get HDMI Outputs
Design Resources
• AD5932 Material Declaration
• PCN-PDN Information
• Quality And Reliability
• Symbols and Footprints
Discussions
View all AD5932 EngineerZone Discussions
Sample and Buy
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Technical Support
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AD5932 Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Serial Interface ............................................................................ 15
Applications ....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 4
Specifications Test Circuit ........................................................... 5
Timing Specifications .................................................................. 6
Master Clock and Timing Diagrams ......................................... 6
Absolute Maximum Ratings ............................................................ 8
ESD Caution .................................................................................. 8
Pin Configuration and Function Descriptions ............................. 9
Typical Performance Characteristics ........................................... 10
Terminology .................................................................................... 14
Theory of Operation ...................................................................... 15
Frequency Profile........................................................................ 15
Powering up the AD5932 .......................................................... 15
Programming the AD5932 ........................................................ 16
Setting Up the Frequency Scan................................................. 17
Activating and Controlling the Scan ....................................... 18
Outputs from the AD5932 ........................................................ 19
Applications ..................................................................................... 20
Grounding and Layout .............................................................. 20
AD5932 to ADSP-21xx Interface ............................................. 20
AD5932 to 68HC11/68L11 Interface ....................................... 21
AD5932 to 80C51/80L51 Interface .......................................... 21
AD5932 to DSP56002 Interface ............................................... 21
Evaluation Board ............................................................................ 22
Schematics ................................................................................... 23
Outline Dimensions ....................................................................... 25
Ordering Guide .......................................................................... 25
REVISION HISTORY
2/12—Rev. 0 to Rev. A
Changes to Figure 21, Figure 22, Figure 23, Figure 24, and
Figure 25 .......................................................................................... 12
Changes to Figure 26, Figure 27, Figure 28, and Figure 29 ....... 13
4/06—Revision 0: Initial Version
Rev. A | Page 2 of 28
Data Sheet AD5932
GENERAL DESCRIPTION
(continued from Page 1)
To program the AD5932, the user enters the start frequency, the
increment step size, the number of increments to be made, and
the time interval that the part outputs each frequency. The frequency scan profile is initiated, started, and executed by toggling
the CTRL pin.
The AD5932 is written to via a 3-wire serial interface that operates
at clock rates up to 40 MHz. The device operates with a power
supply from 2.3 V to 5.5 V.
Note that the AVDD and DVDD are independent of each other
and can be operated from different voltages. The AD5932 also
has a standby function that allows sections of the device that are
not in use to be powered down.
The AD5932 is available in a 16-lead, Pb-free TSSOP.
Rev. A | Page 3 of 28
AD5932 Data Sheet
Update Rate
50
MSPS
Narrow Band (±200 kHz)
−74
−70
dBc
f
= 50 MHz, f
= f
/50
2.8 V DVDD = 4.5 V to 5.5 V
IAA 3.8 4 mA
SPECIFICATIONS
AVDD = DVDD = 2.3 V to 5.5 V; AGND = DGND = 0 V; TA = T
Table 1.
Y Grade1
Parameter Min Typ Max Unit Test Conditions/Comments
SIGNAL DAC SPECIFICATIONS
Resolution 10 Bits
VOUT Peak-to-Peak 0.58 V Internal 200 Ω resistor to GND
VOUT Offset 56 mV From 0 V to the trough of the waveform
V
0.32 V Voltage at midscale output
MIDSCALE
VOU T TC 200 ppm/°C
DC Accuracy
Integral Nonlinearity (INL) ±1.5 LSB
Differential Nonlinearity (DNL) ±0.75 LSB
DDS SPECIFICATIONS
Dynamic Specifications
Signal-to-Noise Ratio 53 60 dB f
Total Harmonic Distortion −60 −53 dBc f
Spurious-Free Dynamic Range (SFDR)
Wide Band (0 to Nyquist) −56 −52 dBc f
Clock Feedthrough −50 dBc Up to 16 MHz out
Wake-Up Time 1.7 ms From standby
OUTPUT BUFFER
VOUT Peak-to-Peak 0 DVDD V Typically, square wave on MSBOUT and SYNCOUT
Output Rise/Fall Time2 12 ns
VOLTAGE REFERENCE
Internal Reference 1.15 1.18 1.26 V
Reference TC2 90 ppm/°C
LOGIC INPUTS2
Input Current 0.1 ±2 µA
Input High Voltage, V
1.7 V DVDD = 2.3 V to 2.7 V
INH
2.0 V DVDD = 2.7 V to 3.6 V
MIN
to T
, unless otherwise noted.
MAX
= 50 MHz, f
MCLK
= 50 MHz, f
MCLK
= 50 MHz, f
MCLK
MCLK
OUT
OUT
OUT
OUT
= f
= f
= f
MCLK
MCLK
MCLK
MCLK
/4096
/4096
/50
Input Low Voltage, V
0.7 V DVDD = 2.7 V to 3.6 V
0.8 V DVDD = 4.5 V to 5.5 V
Input Capacitance, CIN 3 pF
LOGIC OUTPUTS2
Output High Voltage, VOH DVDD − 0.4 V V I
Output Low Voltage, VOL 0.4 V I
Floating-State O/P Capacitance 5 pF
POWER REQUIREMENTS f
AVDD/DVDD 2.3 5.5 V
IDD 2.4 2.7 mA
IAA + IDD 6.2 6.7 mA
0.6 V DVDD = 2.3 V to 2.7 V
INL
= 1 mA
SINK
= 1 mA
SINK
MCLK
Rev. A | Page 4 of 28
= 50 MHz, f
OUT
= f
MCLK
/7
Data Sheet AD5932
10-BIT
DAC
SIN
ROM
AVDD
REGULATOR
20pF
10nF
COMP
VOUT
AD5932
CAP/2.5V
12
100nF 10nF
05416-002
Y Grade1
Parameter Min Typ Max Unit Test Conditions/Comments
Low Power Sleep Mode Device is reset before putting into standby
20 85 µA All outputs powered down, MCLK = 0 V,
serial interface active
140 240 µA All outputs powered down, MCLK active,
serial interface active
1
Operating temperature range is as follows: Y version: −40°C to +125°C; typical specifications are at +25°C.
2
Guaranteed by design, not production tested.
SPECIFICATIONS TEST CIRCUIT
Figure 2. Test Circuit Used to Test the Specifications
Rev. A | Page 5 of 28
AD5932 Data Sheet
MCLK
t
3
t
2
t
1
05416-003
SCLK
FSYNC
SDATA
D15 D14 D2 D1 D0 D15 D14
t
7
t
9
t
6
t
8
t
10
t
5
t
4
05416-004
TIMING SPECIFICATIONS
All input signals are specified with tR = tF = 5 ns (10% to 90% of VDD) and are timed from a voltage level of (VIL + VIH)/2 (see Figure 3 to
Figure 6). DVDD = 2.3 V to 5.5 V; AGND = DGND = 0 V; all specifications T
Table 2.
Parameter1 Limit at T
MIN
, T
Unit Conditions/Comments
MAX
t1 20 ns min MCLK period
t2 8 ns min MCLK high duration
t3 8 ns min MCLK low duration
t4 25 ns min SCLK period
t5 10 ns min SCLK high time
t6 10 ns min SCLK low time
t7 5 ns min FSYNC to SCLK falling edge setup time
t8 10 ns min FSYNC to SCLK hold time
t9 5 ns min Data setup time
t10 3 ns min Data hold time
t11 2 × t1 ns min Minimum CTRL pulse width
t12 0 ns min CTRL rising edge to MCLK falling edge setup time
t13 10 × t1 ns typ CTRL rising edge to VOUT delay (initial pulse, includes initialization)
8 × t1 ns typ CTRL rising edge to VOUT delay (initial pulse, includes initialization)
t14 1 × t1 ns typ Frequency change to SYNC output, each frequency increment
t15 2 × t1 ns typ Frequency change to SYNC output, end of scan
t16 20 ns max MCLK falling edge to MSBOUT
1
Guaranteed by design, not production tested.
MIN
to T
, unless otherwise noted.
MAX
MASTER CLOCK AND TIMING DIAGRAMS
Figure 3. Master Clock
Figure 4. Serial Timing
Rev. A | Page 6 of 28
Data Sheet AD5932
MCLK
CTRL
VOUT
t
12
t
11
t
13
05416-005
CTRL
VOUT
SYNCOUT
(Each Freq uency
Increment)
SYNCOUT
(End of Scan)
t
13
t
15
t
14
05416-006
Figure 5. CTRL Timing
Figure 6. SYNCOUT Timing
Rev. A | Page 7 of 28
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