ANALOG DEVICES AD5762R Service Manual

Complete Dual, 16-Bit, High Accuracy,

Serial Input, Bipolar Voltage Output DAC

FEATURES

Complete dual, 16-bit digital-to-analog converter (DAC)
Programmable output range: ±10 V, ±10.2564 V, or ±10.5263 V
±1 LSB maximum INL error, ±1 LSB maximum DNL error
Low noise: 60 nV/√Hz
Settling time: 10 μs maximum
Integrated reference buffers
Internal reference: 10 ppm/°C maximum
On-chip die temperature sensor
Output control during power-up/brownout
Programmable short-circuit protection
Simultaneous updating via
Asynchronous
Digital offset and gain adjust
Logic output control pins
DSP-/microcontroller-compatible serial interface
Temperature range: −40°C to +85°C
iCMOS process technology

CLR

to zero code

APPLICATIONS

Industrial automation
Open-loop/closed-loop servo control
Process control
Data acquisition systems
Automatic test equipment
Automotive test and measurement
High accuracy instrumentation

LDAC

AD5762R

GENERAL DESCRIPTION

The AD5762R is a dual, 16-bit, serial input, bipolar voltage output
DAC that operates from supply voltages of ±11.4 V to ±16.5 V.
Nominal full-scale output range is ±10 V. The AD5762R provides
integrated output amplifiers, reference buffers, and proprietary
power-up/power-down control circuitry. The part also features
a digital I/O port, programmed via the serial interface, and an
analog temperature sensor. The part incorporates digital offset
and gain adjust registers per channel.

The AD5762R is a high performance converter that provides
guaranteed monotonicity, integral nonlinearity (INL) of ±1 LSB,
low noise, and 10 μs settling time. The AD5762R includes an
on-chip 5 V reference with a reference temperature coefficient
of 10 ppm/°C maximum. During power-up when the supply
voltages are changing, VOUTx is clamped to 0 V via a low
impedance path.

The AD5764R is based on the iCMOS® technology platform, which
is designed for analog systems designers within industrial/instru­mentation equipment OEMs who need high performance ICs at
higher voltage levels. iCMOS enables the development of analog
ICs capable of 30 V and operation at ±15 V supplies, while allowing
reductions in power consumption and package size, coupled with
increased ac and dc performance.

The AD5762R uses a serial interface that operates at clock rates
of up to 30 MHz and is compatible with DSP and microcontroller
interface standards. Double buffering allows the simultaneous
updating of all DACs. The input coding is programmable to either
twos complement or offset binary formats. The asynchronous
clear function clears all DAC registers to either bipolar zero or
zero scale, depending on the coding used. The AD5762R is ideal
for both closed-loop servo control and open-loop control appli­cations. The AD5762R is available in a 32-lead TQFP and offers
guaranteed specifications over the −40°C to +85°C industrial
temperature range (see

Figure 1 for the functional block diagram).

Rev. A

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

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Tel: [phone] www.analog.com
Fax: [phone] ©2008–2009 Analog Devices, Inc. All rights reserved.

AD5762R

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications ....................................................................................... 1 

General Description ......................................................................... 1

Revision History ............................................................................... 2

Functional Block Diagram .............................................................. 3

Specifications ..................................................................................... 4

AC Performance Characteristics ................................................ 6

Timing Characteristics ................................................................ 7

Absolute Maximum Ratings .......................................................... 10

Thermal Resistance .................................................................... 10

ESD Caution ................................................................................ 10

Pin Configuration and Function Descriptions ........................... 11

Typical Performance Characteristics ........................................... 13

Terminology .................................................................................... 19

Theory of Operation ...................................................................... 21

DAC Architecture ....................................................................... 21

Reference Buffers ........................................................................ 21

Serial Interface ............................................................................ 21

Simultaneous Updating via

Transfer Function ....................................................................... 23

Asynchronous Clear (

Registers ........................................................................................... 24

LDAC

........................................... 22

CLR

) ....................................................... 23

Function Register ....................................................................... 24

Data Register ............................................................................... 25

Coarse Gain Register ................................................................. 25

Fine Gain Register ...................................................................... 25

Offset Register ............................................................................ 26

Offset and Gain Adjustment Worked Example ......................... 26

Design Features ............................................................................... 27

Analog Output Control ............................................................. 27

Digital Offset and Gain Control ............................................... 27

Programmable Short-Circuit Protection ................................ 27

Digital I/O Port ........................................................................... 27

Die Temperature Sensor ............................................................ 27

Local Ground Offset Adjust ...................................................... 27

Applications Information .............................................................. 28

Typical Operating Circuit ......................................................... 28

Layout Guidelines ........................................................................... 30

Galvanically Isolated Interface ................................................. 30

Microprocessor Interfacing ....................................................... 30

Evaluation Board ........................................................................ 31

Outline Dimensions ....................................................................... 32

Ordering Guide .......................................................................... 32

REVISION HISTORY

8/09—Rev. 0 to Rev. A

Deleted Endnote 1, Table 1 .............................................................. 4

Deleted Endnote 1, Table 2 .............................................................. 6

Deleted Endnote 1, Table 3 .............................................................. 7

Changes to t

12/08—Revision 0: Initial Version

Parameter, Table 3 .................................................... 7

6

Rev. A | Page 2 of 32

AD5762R

FUNCTIONAL BLOCK DIAGRAM

DV

DGND

AVDDAVSSAVDDAV

PGND

CC

AD5762R

SS

REFOUT

5V

REFERENCE

REFAREFGND

REFERENCE

BUFFERS

VOLTAGE
MONITOR

AND

CONTROL

RSTINRSTOUT

ISCC

SDIN

SCLK

SYNC

SDO

BIN/2sCOMP

CLR

16

INPUT

INPUT
SHIFT

REGISTER

AND

CONTROL

LOGIC

D0

D1

REG A

GAIN REG A

OFFSET REG A

INPUT
REG B

GAIN REG B

OFFSET REG B

16

DAC

REG A

DAC

REG B

LDAC REFB

16

DAC A

DAC B

REFERENCE

BUFFERS

TEMP

SENSOR

TEMP

G1

G1

G2

G2

VOUTA

AGNDA

VOUTB

AGNDB

07248-001

Figure 1.

Rev. A | Page 3 of 32

AD5762R

SPECIFICATIONS

AVDD = 11.4 V to 16.5 V, AVSS = −11.4 V to −16.5 V, AGND = DGND = REFGND = PGND = 0 V; REFA = REFB = 5 V external;
DV

= 2.7 V to 5.25 V, R

CC

Table 1.

Parameter Min Typ Max Unit Test Conditions/Comments1
ACCURACY Outputs unloaded

Resolution 16 Bits
Relative Accuracy (INL) −1 +1 LSB
Differential Nonlinearity (DNL) −1 +1 LSB Guaranteed monotonic
Bipolar Zero Error −2 +2 mV

−3 +3 mV
Bipolar Zero Tempco2 −2 +2 ppm FSR/°C
Zero-Scale Error −2 +2 mV

−2.5 +2.5 mV
Zero-Scale Tempco2 −2 +2 ppm FSR/°C
Gain Error −0.02 +0.02 % FSR
Gain Tempco2 −2 +2 ppm FSR/°C
DC Crosstalk2 0.5 LSB

REFERENCE INPUT/OUTPUT

Reference Input2

Reference Input Voltage 5 V ±1% for specified performance
DC Input Impedance 1 100 MΩ
Input Current −10 ±0.03 +10 μA
Reference Range 1 7 V

Reference Output

Output Voltage 4.995 5 5.005 V 25°C, AVDD/AVSS = ±13.5 V
Reference Tempco2 −10 ±1.7 +10 ppm/°C

2

R

1 MΩ

LOAD

Power Supply Sensitivity2 300 μV/V
Output Noise2 18 μV p-p 0.1 Hz to 10 Hz
Noise Spectral Density2 75 nV/√Hz 10 kHz
Output Voltage Drift vs. Time2 ±40 ppm/500 hr
±50 ppm/1000 hr
Thermal Hysteresis2 70 ppm First temperature cycle
30 ppm Subsequent temperature cycles

OUTPUT CHARACTERISTICS2

Output Voltage Range3 −10.5263 +10.5263 V AVDD/AVSS = ±11.4 V, REFA = REFB = 5 V

−14.7368 +14.7368 V AVDD/AVSS = ±16.5 V, REFA = REFB = 7 V
Output Voltage Drift vs. Time ±13

±15

Short-Circuit Current 10 mA R
Load Current −1 +1 mA For specified performance
Capacitive Load Stability

R

= ∞ 200 pF

LOAD

R

= 10 kΩ 1000 pF

LOAD

DC Output Impedance 0.3 Ω

= 10 kΩ, CL = 200 pF. All specifications T

LOAD

MIN

to T

ppm FSR/
500 hr

ppm FSR/
1000 hr

, unless otherwise noted.

MAX

25°C; error at other temperatures obtained
using bipolar zero tempco

25°C; error at other temperatures obtained
using zero-scale tempco

= 6 kΩ, see Figure 31

ISCC

Rev. A | Page 4 of 32

AD5762R

Parameter Min Typ Max Unit Test Conditions/Comments
DIGITAL INPUTS

2

DV

= 2.7 V to 5.25 V

CC

1

Input High Voltage, VIH 2.4 V
Input Low Voltage, VIL 0.8 V
Input Current −1.2 +1.2 μA Per pin
Pin Capacitance 10 pF Per pin

DIGITAL OUTPUTS (D0, D1, SDO)

2

Output Low Voltage 0.4 V DVCC = 5 V ± 5%, sinking 200 μA
Output High Voltage DVCC − 1 V DVCC = 5 V ± 5%, sourcing 200 μA
Output Low Voltage 0.4 V DVCC = 2.7 V to 3.6 V, sinking 200 μA
Output High Voltage DVCC − 0.5 V DVCC = 2.7 V to 3.6 V, sourcing 200 μA
High Impedance Leakage Current −1 +1 μA SDO only
High Impedance Output Capacitance 5 pF SDO only

DIE TEMPERATURE SENSOR2

Output Voltage at 25°C 1.47 V Die temperature
Output Voltage Scale Factor 5 mV/°C
Output Voltage Range 1.175 1.9 V −40°C to +105°C
Output Load Current 200 μA Current source only
Power-On Time 80 ms

POWER REQUIREMENTS

AVDD +11.4 +16.5 V
AVSS −16.5 −11.4
DVCC 2.7 5.25 V
Power Supply Sensitivity

∆V

/∆ΑVDD −85 dB

OUT

2

AIDD 4.25 mA/channel Outputs unloaded

AISS 3.9 mA/channel Outputs unloaded
DICC 1.2 mA VIH = DVCC, VIL = DGND, 750 μA typ
Power Dissipation 180 mW ±12 V operation output unloaded

1

Temperature range: −40°C to +85°C; typical at +25°C. Device functionality is guaranteed to +105°C with degraded performance.

2

Guaranteed by design and characterization; not production tested.

3

Output amplifier headroom requirement is 1.4 V minimum.

Rev. A | Page 5 of 32

AD5762R

AC PERFORMANCE CHARACTERISTICS

AVDD = 11.4 V to 16.5 V, AVSS = −11.4 V to −16.5 V, AGND = DGND = REFGND = PGND = 0 V; REFA, REFB= 5 V external;
DV

= 2.7 V to 5.25 V, R

CC

Table 2.

Parameter Min Typ Max Unit Test Conditions/Comments
DYNAMIC PERFORMANCE

Output Voltage Settling Time 8 10 μs Full-scale step to ±1 LSB

2 μs 512 LSB step settling

Slew Rate 5 V/μs
Digital-to-Analog Glitch Energy 8 nV-sec
Glitch Impulse Peak Amplitude 25 mV
Channel-to-Channel Isolation 80 dB
DAC-to-DAC Crosstalk 8 nV-sec
Digital Crosstalk 2 nV-sec
Digital Feedthrough 2 nV-sec

Output Noise (0.1 Hz to 10 Hz) 0.1 LSB p-p
Output Noise (0.1 Hz to 100 kHz) 45 μV rms
1/f Corner Frequency 1 kHz
Output Noise Spectral Density 60 nV/√Hz Measured at 10 kHz
Complete System Output Noise Spectral Density

1

Guaranteed by design and characterization; not production tested.

2

Includes noise contributions from integrated reference buffers,16-bit DAC, and output amplifier.

= 10 kΩ, CL = 200 pF. All specifications T

LOAD

1

2

80 nV/√Hz Measured at 10 kHz

MIN

to T

, unless otherwise noted.

MAX

Effect of input bus activity on
DAC outputs

Rev. A | Page 6 of 32

AD5762R

TIMING CHARACTERISTICS

AVDD = 11.4 V to 16.5 V, AVSS = −11.4 V to −16.5 V, AGND = DGND = REFGND = PGND = 0 V; REFA = REFB = 5 V external;
DV

= 2.7 V to 5.25 V, R

CC

= 10 kΩ, CL = 200 pF. All specifications T

LOAD

MIN

to T

, unless otherwise noted.

MAX

Table 3.

1, 2, 3

Parameter

Limit at T

, T

Unit Description

MIN

MAX

t1 33 ns min SCLK cycle time
t2 13 ns min SCLK high time
t3 13 ns min SCLK low time
t4 13 ns min

4

t

5

13 ns min

t6 90 ns min

falling edge to SCLK falling edge setup time

SYNC

th

SCLK falling edge to SYNC rising edge

24
Minimum SYNC

high time
t7 2 ns min Data setup time
t8 5 ns min Data hold time
t9 1.7 μs min
480 ns min
t10 10 ns min
t11 500 ns max

rising edge to LDAC falling edge (all DACs updated)

SYNC

rising edge to LDAC falling edge (single DAC updated)

SYNC

pulse width low

LDAC

falling edge to DAC output response time

LDAC
t12 10 μs max DAC output settling time
t13 10 ns min
t14 2 μs max

5, 6

t

25 ns max SCLK rising edge to SDO valid

15

t16 13 ns min
t17 2 μs max
t18 170 ns min

1

Guaranteed by design and characterization; not production tested.

2

All input signals are specified with tR = tF = 5 ns (10% to 90% of DVCC) and timed from a voltage level of 1.2 V.

3

See Figure 2, Figure 3, and Figure 4.

4

Standalone mode only.

5

Measured with the load circuit of Figure 5.

6

Daisy-chain mode only.

pulse width low

CLR

pulse activation time

CLR

rising edge to SCLK falling edge

SYNC

rising edge to DAC output response time (LDAC = 0)

SYNC

falling edge to SYNC rising edge

LDAC

Rev. A | Page 7 of 32

AD5762R

Timing Diagrams

t

1

SCLK

SYNC

SDIN

LDAC

VOUTA/

VOUTB

LDAC = 0

VOUTA/

VOUTB

CLR

VOUTA/

VOUTB

12 24

t

6

t

4

t

7

DB23

t

t

3

t

8

t

13

14

t

2

t

10

Figure 2. Serial Interface Timing Diagram

t

5

DB0

t

t

9

t

18

t

17

10

t

t

11

t

12

12

07248-002

t

1

SCLK

SYNC

SDIN

SDO

LDAC

t

6

t

4

t

7

DB23 DB0 DB23 DB0

t

3

t

8

Figure 3. Daisy-Chain Timing Diagram

24 48

t

2

INPUT WORD FOR DAC N – 1INPUT WO RD FOR DAC N

t

15

DB23

INPUT WORD FOR DAC NUNDEFINED

DB0

t

5

t

16

t

9

t

10

07248-003

Rev. A | Page 8 of 32

AD5762R

SYNC

SCLK

24 48

SDIN

SDO

DB23 DB0 DB23 DB0

INPUT WORD SPECIFIES

REGIS TER TO BE READ

UNDEFINED

DB23

NOP CONDITI ON

SELECTED REGISTER DATA

CLOCKED OUT

DB0

07248-004

Figure 4. Readback Timing Diagram

200µA I

TO OUTPUT

PIN

C

L

50pF

200µA I

Figure 5. Load Circuit for SDO Timing Diagram

OL

OH

VOH (MIN) OR
V

(MAX)

OL

07248-005

Rev. A | Page 9 of 32

AD5762R

ABSOLUTE MAXIMUM RATINGS

TA = 25°C unless, otherwise noted. Transient currents of up to
100 mA do not cause SCR latch-up.

Table 4.

Parameter Rating

AVDD to AGND, DGND −0.3 V to +17 V
AVSS to AGND, DGND +0.3 V to −17 V
DVCC to DGND −0.3 V to +7 V
Digital Inputs to DGND

Digital Outputs to DGND −0.3 V to DVCC + 0.3 V
REFx to AGND, PGND −0.3 V to AVDD + 0.3 V
REFOUT to AGND AVSS to AVDD
TEMP AVSS to AVDD
VOUTx to AGND AVSS to AVDD
AGND to DGND −0.3 V to +0.3 V
Operating Temperature Range

Industrial −40°C to +85°C
Storage Temperature Range −65°C to +150°C
Junction Temperature (TJ max) 150°C
Lead Temperature (Soldering) JEDEC Industry Standard

J-STD-020

−0.3 V to (DV
whichever is less

+ 0.3 V) or +7 V,

CC

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

THERMAL RESISTANCE

θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.

Table 5. Thermal Resistance

Package Type θJA θ

32-Lead TQFP 65 12 °C/W

Unit

JC

ESD CAUTION

Rev. A | Page 10 of 32