ANALOG DEVICES AD5724R, AD5734R, AD5754R Service Manual

Complete, Quad, 12-/14-/16-Bit, Serial Input,

FEATURES

Complete, quad, 12-/14-/16-bit DACs Operates from single/dual supplies Software programmable output range

+5 V, +10 V, +10.8 V, ±5 V, ±10 V, ±10.8 V INL error: ±16 LSB maximum, DNL error: ±1 LSB maximum Total unadjusted error (TUE): 0.1% FSR maximum Settling time: 10 μs typical Integrated reference: ±5 ppm/°C maximum Integrated reference buffers Output control during power-up/brownout Simultaneous updating via Asynchronous DSP/microcontroller-compatible serial interface 24-lead TSSOP Operating temperature range: −40°C to +85°C iCMOS process technology

to zero scale/midscale

CLR

APPLICATIONS

Industrial automation Closed-loop servo control, process control Automotive test and measurement Programmable logic controllers

LDAC

1

Unipolar/Bipolar Voltage Output DACs

AD5724R/AD5734R/AD5754R

GENERAL DESCRIPTION

The AD5724R/AD5734R/AD5754R are quad, 12-/14-/16-bit serial input, voltage output, digital-to-analog converters (DACs). They operate from single supply voltages of +4.5 V up to +16.5 V or dual supply voltages from ±4.5 V up to ±16.5 V. Nominal full-scale output range is software selectable from +5 V, +10 V, +10.8 V, ±5 V, ±10 V, or ±10.8 V. Integrated output amplifiers, reference buffers, and proprietary power-up/power-down control circuitry are also provided.

The parts offer guaranteed monotonicity, integral nonlinearity (INL) of ±16 LSB maximum, low noise, 10 µs typical settling time, and an on-chip +2.5 V reference.

The AD5724R/AD5734R/AD5754R use a serial interface that operates at clock rates up to 30 MHz and are compatible with DSP and microcontroller interface standards. Double buffering allows the simultaneous updating of all DACs. The input coding is user-selectable twos complement or offset binary for a bipolar output (depending on the state of Pin BIN/ binary for a unipolar output. The asynchronous clear function clears all DAC registers to a user-selectable zero-scale or midscale output. The parts are available in a 24-lead TSSOP and offer guaranteed specifications over the −40°C to +85°C industrial temperature range.

2sCOMP

) and straight

1

iCMOS®, Reg. U.S. Patent and Trademark Office.

Rev. B

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

Table 1. Pin Compatible Devices

Part Number Description

AD5724/AD5734/AD5754

AD5722/AD5732/AD5752

AD5722R/AD5732R/AD5752R

AD5724R/AD5734R/AD5754R without internal reference.

Complete, dual, 12-/14-/16-bit, serial input, unipolar/bipolar, voltage output DACs.

AD5722/AD5732/AD5752 with internal reference.

AD5724R/AD5734R/AD5754R

REVISION HISTORY

5/10—Rev. A to Rev. B

Changes to Table 5 ............................................................................ 9

Changes to Table 6 .......................................................................... 10

3/09—Rev. 0 to Rev. A

Added AD5724R Model ............................................... Throughout

Added 12-Bit Resolution .............................................. Throughout

Changes to Resolution and Integral Nonlinearity (INL)

Parameters (Table 2) ......................................................................... 4

Changes to Endnote 2 (Table 2) ...................................................... 5

Added Endnote 4 (Table 4) ............................................................. 6

Added Figure 8 and Figure 11 ....................................................... 11

Added Figure 39 .............................................................................. 16

Added Ideal Output Voltage to Input Code

Relationship—AD5724R Section ................................................. 25

Added Table 21 ............................................................................... 27

Changes to Ordering Guide .......................................................... 32

1/09—Revision 0: Initial Version

Rev. B | Page 2 of 32

AD5724R/AD5734R/AD5754R

FUNCTIONAL BLOCK DIAGRAM

AV

SS

AD5724R/AD5734R/AD5754R

DV

CC

DD

2.5V

REFERENCE

REFIN/REFOUT

REFERENCE

BUFFERS

SDIN SCLK SYNC

SDO

CLR

BIN/2sCOMP

INPUTSHIFT

REGISTER

AND

CONTROL

LOGIC

AD5724R: n = 12-BI T AD5734R: n = 14-BI T AD5754R: n = 16-BI T

n

GND

INPUT

REGISTER A

INPUT

REGISTER B

INPUT

REGISTER C

INPUT

REGISTER D

DAC

REGISTER A

DAC

REGISTER B

DAC

REGISTER C

DAC

REGISTER D

LDAC

n

DAC A

n

DAC B

n

DAC C

n

DAC D

DAC_GND (2) SIG_GND (2)

V

A

OUT

B

V

OUT

C

V

OUT

D

V

OUT

06465-001

Figure 1.

Rev. B | Page 3 of 32

AD5724R/AD5734R/AD5754R

SPECIFICATIONS

AVDD = 4.5 V1 to 16.5 V, AVSS = −4.5 V1 to −16.5 V or AVSS = 0 V, GND = 0 V, REFIN= +2.5 V external, DVCC = 2.7 V to 5.5 V, R

= 2 kΩ, C

LOAD

Table 2.

Parameter Min Typ Max Unit Test Conditions/Comments

ACCURACY Outputs unloaded

Resolution

AD5754R 16 Bits AD5734R 14 Bits AD5724R 12 Bits

Total Unadjusted Error (TUE) −0.1 +0.1 % FSR

Integral Nonlinearity (INL)2

AD5754R −16 +16 LSB AD5734R −4 +4 LSB

AD5724R −1 +1 LSB Differential Nonlinearity (DNL) −1 +1 LSB All models, guaranteed monotonic Bipolar Zero Error −6 +6 mV TA = 25°C, error at other temperatures obtained using

Bipolar Zero TC3 ±4 ppm FSR/°C Zero-Scale Error −6 +6 mV TA = 25°C, error at other temperatures obtained using

Zero-Scale TC Offset Error −6 +6 mV TA = 25°C, error at other temperatures obtained using

Offset Error TC Gain Error −0.025 +0.025 % FSR ±10 V range, TA = 25°C, error at other temperatures

Gain Error

Gain TC DC Crosstalk

REFERENCE INPUT/OUTPUT

Reference Input

Reference Input Voltage 2.5 V ±1% for specified performance DC Input Impedance 1 5 MΩ Input Current −2 ±0.5 +2 μA Reference Range 2 3 V

Reference Output

Output Voltage 2.497 2.501 V TA = 25°C Reference TC

2.2 10 ppm/°C TA = −40°C to +85°C Output Noise (0.1 Hz to 10 Hz)3 Noise Spectral Density

OUTPUT CHARACTERISTICS

Output Voltage Range −10.8 +10.8 V AVDD/AVSS = ±11.7 V min, REFIN = +2.5 V

−12 +12 V AVDD/AVSS = ±12.9 V min, REFIN = +3 V Headroom 0.5 0.9 V Output Voltage TC ±4 ppm FSR/°C Output Voltage Drift vs. Time ±12 ppm FSR/500 hr ±15 ppm FSR/1000 hr Short-Circuit Current 20 mA Load 2 kΩ For specified performance Capacitive Load Stability 4000 pF DC Output Impedance 0.5 Ω

= 200 pF, all specifications T

LOAD

MIN

to T

, unless otherwise noted.

MAX

bipolar zero TC

zero-scale TC

3

±4 ppm FSR/°C

offset error TC

3

±4 ppm FSR/°C

obtained using gain TC

3

−0.065 0 +10 V and +5 V ranges, T

temperatures obtained using gain TC

3

0 +0.08 ±5 V range, T

= 25°C, error at other temperatures

A

obtained using gain TC

3

3, 4

1.8 5 ppm/°C TA = 0°C to 85°C

±4 ppm FSR/°C 120 μV

5 μV p-p

3

75 nV/√Hz @ 10 kHz

Rev. B | Page 4 of 32

= 25°C, error at other

A

AD5724R/AD5734R/AD5754R

Parameter Min Typ Max Unit Test Conditions/Comments

DIGITAL INPUTS

Input High Voltage, VIH 2 V Input Low Voltage, VIL 0.8 V Input Current ±1 μA Per pin Pin Capacitance 5 pF Per pin

DIGITAL OUTPUTS (SDO)

Output Low Voltage, VOL 0.4 V DVCC = 5 V ± 10%, sinking 200 μA Output High Voltage, VOH DVCC − 1 V DV Output Low Voltage, VOL 0.4 V DVCC = 2.7 V to 3.6 V, sinking 200 μA Output High Voltage, VOH DVCC − 0.5 V DVCC = 2.7 V to 3.6 V, sourcing 200 μA High Impedance Leakage Current ±1 μA High Impedance Output

Capacitance

POWER REQUIREMENTS

AVDD 4.5 16.5 V AVSS −4.5 −16.5 V DVCC 2.7 5.5 V Power Supply Sensitivity

∆V

AIDD 2.5 mA/channel Outputs unloaded

1.75 mA/channel AVSS = 0 V, outputs unloaded AISS 2.2 mA/channel Outputs unloaded DICC 0.5 3 μA VIH = DVCC, VIL = GND, 0.5 μA typical Power Dissipation 310 mW ±16.5 V operation, outputs unloaded 115 mW +16.5 V operation, outputs unloaded Power-Down Currents All DAC channels and internal reference

AIDD 40 μA AISS 40 μA DICC 300 nA

1

For specified performance, headroom requirement is 0.9 V.

2

INL is the relative accuracy. It is measured from Code 512, Code 128, Code 32 for the AD5754R, AD5734R, AD5724R respectively.

3

Guaranteed by characterization; not production tested.

4

The on-chip reference is production trimmed and tested at 25°C and 85°C. It is characterized from −40°C to +85°C.

3

DVCC = 2.7 V to 5.5 V, JEDEC compliant

= 5 V ± 10%, sourcing 200 μA

CC

5 pF

3

/∆ΑVDD −65 dB 200 mV sine wave superimposed on AVSS/AVDD @

OUT

50 Hz/60 Hz

powered-down

Rev. B | Page 5 of 32

AD5724R/AD5734R/AD5754R

AC PERFORMANCE CHARACTERISTICS

AVDD = 4.5 V1 to 16.5 V, AVSS = −4.5 V1 to −16.5 V or 0 V, GND = 0 V, REFIN= 2.5 V external, DVCC = 2.7 V to 5.5 V, R C

= 200 pF, all specifications T

LOAD

MIN

to T

, unless otherwise noted.

MAX

Table 3.

Parameter2 Min Typ Max Unit Test Conditions/Comments

DYNAMIC PERFORMANCE

Output Voltage Settling Time 10 12 μs 20 V step to ±0.03 % FSR

7.5 8.5 μs 10 V step to ±0.03 % FSR 5 μs 512 LSB step settling (16-bit resolution)

Slew Rate 3.5 V/μs Digital-to-Analog Glitch Energy 13 nV-sec Glitch Impulse Peak Amplitude 35 mV Digital Crosstalk 10 nV-sec DAC-to-DAC Crosstalk 10 nV-sec Digital Feedthrough 0.6 nV-sec Output Noise

0.1 Hz to 10 Hz Bandwidth 15 μV p-p 0x8000 DAC code 100 kHz Bandwidth 80 μV rms

Output Noise Spectral Density 320 nV/√Hz Measured at 10 kHz, 0x8000 DAC code

1

For specified performance, headroom requirement is 0.9 V.

2

Guaranteed by design and characterization; not production tested.

LOAD

= 2 kΩ,

TIMING CHARACTERISTICS

AVDD = 4.5 V to 16.5 V, AVSS = −4.5 V to −16.5 V or 0 V, GND = 0 V, REFIN = 2.5 V external, DVCC = 2.7 V to 5.5 V, R C

= 200 pF, all specifications are T

LOAD

Table 4.

1, 2, 3

Parameter

4

t

33 ns min SCLK cycle time

1

Limit at T

t2 13 ns min SCLK high time t3 13 ns min SCLK low time t4 13 ns min

t5 13 ns min t6 100 ns min t7 5 ns min Data setup time

t8 0 ns min Data hold time t9 20 ns min

t10 20 ns min t11 20 ns min t12 10 μs typ DAC output settling time t13 20 ns min t14 2.5 μs max

5

t

15

5

t

40 ns max SCLK rising edge to SDO valid (C

16

13 ns min

t17 200 ns min

1

Guaranteed by characterization; not production tested.

2

All input signals are specified with tR = tF = 5 ns (10% to 90% of DVCC) and timed from a voltage level of 1.2 V.

3

See Figure 2, Figure 3, and Figure 4.

4

To accommodate t16, in readback and daisy-chain modes the SCLK cycle time must be increased to 90 ns.

5

Daisy-chain and readback mode.

6

C

= capacitive load on SDO output.

L SDO

MIN

, T

MIN

MAX

to T

, unless otherwise noted.

MAX

Unit Description

falling edge to SCLK falling edge setup time

SYNC SCLK falling edge to SYNC Minimum SYNC

falling edge to SYNC falling edge

LDAC

rising edge to LDAC falling edge

SYNC

pulse width low

LDAC

pulse width low

CLR

pulse activation time

CLR

rising edge to SCLK falling edge

SYNC

Minimum SYNC

rising edge

high time (write mode)

6

= 15 pF)

L SDO

high time (readback/daisy-chain mode)

LOAD

= 2 kΩ,

Rev. B | Page 6 of 32

AD5724R/AD5734R/AD5754R

TIMING DIAGRAMS

t

1

SCLK

SYNC

SDIN

LDAC

V

OUT

V

OUT

CLR

V

OUT

t

6

t

4

t

7

DB23

t

9

x

t

3

t

8

t

13

t

14

4221

t

2

t

5

DB0

t

10

11

t

12

t

12

06465-002

Figure 2. Serial Interface Timing Diagram

t

1

SCLK

SYNC

SDIN

SDO

LDAC

t

17

t

4

t

7

t

3

t

8

t

2

INPUTWORDFORDACN-1INPUTWORD FOR DACN

t

16

DB23

INPUT WORD F OR DAC NUNDEFINED

8442

DB0

t

5

t

15

0BD32BD0BD32BD

t

10

t

11

06465-003

Figure 3. Daisy-Chain Timing Diagram

Rev. B | Page 7 of 32

AD5724R/AD5734R/AD5754R

SCLK

SYNC

1

t

1

17

4242

SDIN

SDO

REGISTER TO BE READ

UNDEFINED

Figure 4. Readback Timing Diagram

NOP CONDITIONINPUT WORD SPECIFIES

SELECTED REGISTER DATA

CLOCKED OUT

0BD32BD0BD32BD

06465-004

Rev. B | Page 8 of 32

AD5724R/AD5734R/AD5754R

ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted. Transient currents of up to 100 mA do not cause SCR latch-up.

Table 5.

Parameter Rating

AVDD to GND −0.3 V to +17 V AVSS to GND +0.3 V to −17 V DVCC to GND −0.3 V to +7 V Digital Inputs to GND

Digital Outputs to GND

REFIN/REFOUT to GND −0.3 V to +5 V V

x to GND AVSS to AVDD

OUT

DAC_GND to GND −0.3 V to +0.3 V SIG_GND to GND −0.3 V to +0.3 V Operating Temperature Range, TA

Industrial −40°C to +85°C Storage Temperature Range −65°C to +150°C Junction Temperature, TJ max 150°C 24-Lead TSSOP Package

θJA Thermal Impedance 42°C/W

θJC Thermal Impedance 9°C/W Power Dissipation (TJ max – TA)/θJA Lead Temperature JEDEC industry standard

Soldering J-STD-020 ESD (Human Body Model) 3.5 kV

−0.3 V to DV (whichever is less)

+ 0.3 V or 7 V

CC

+ 0.3 V or 7 V

CC

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

ESD CAUTION

Rev. B | Page 9 of 32

AD5724R/AD5734R/AD5754R

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

AV

1

AV

SS

2

NC

AD5724R/

3

A

V

OUT

V

OUT

BIN/2sCOMP

SYNC SCLK

SDIN

LDAC

NOTES

1. NC = NO CONNECT

2. IT IS RE COMMENDED THAT THE EXPOSED PAD BE THERMALLY CONNECTED TO A COPPER PLANE FOR ENHANCED THERMA L PERFORMANCE.

NC

CLR

NC

4

B

5 6 7 8

9 10 11 12

AD5734R/

AD5754R

TOP VIEW

(Not to Scale)

Figure 5. Pin Configuration

Table 6. Pin Function Descriptions

Pin No. Mnemonic Description

1 AVSS

Negative Analog Supply Pin. Voltage range is from –4.5 V to –16.5 V. This pin can be connected to 0 V if

output ranges are unipolar. 2, 6, 12, 13 NC No Connect. Do not connect to these pins. 3 V 4 V 5

A Analog Output Voltage of DAC A. The output amplifier is capable of directly driving a 2 kΩ, 4000 pF load.

OUT

B Analog Output Voltage of DAC B. The output amplifier is capable of directly driving a 2 kΩ, 4000 pF load.

OUT

BIN/2sCOMP

This pin determines the DAC coding for a bipolar output range. This pin should be hardwired to either DV

or GND. When hardwired to DV

, input coding is offset binary. When hardwired to GND, input coding is twos

CC

complement. (For unipolar output ranges, coding is always straight binary.) 7

Active Low Input. This is the frame synchronization signal for the serial interface. While SYNC is low, data is

SYNC

transferred on the falling edge of SCLK. Data is latched on the rising edge of SYNC. 8 SCLK

Serial Clock Input. Data is clocked into the shift register on the falling edge of SCLK. This operates at clock

speeds up to 30 MHz. 9 SDIN Serial Data Input. Data must be valid on the falling edge of SCLK. 10

LDAC

Load DAC, Logic Input. This is used to update the DAC registers and, consequently, the analog output. When

tied permanently low, the addressed DAC register is updated on the rising edge of SYNC

during the write cycle, the DAC input register is updated, but the output update is held off until the falling

11

CLR

edge of LDAC

The LDAC

Active Low Input. Asserting this pin sets the DAC registers to zero-scale code or midscale code (user selectable).

. In this mode, all analog outputs can be updated simultaneously on the falling edge of LDAC.

pin should not be left unconnected.

14 DVCC Digital Supply Pin. Voltage range is from 2.7 V to 5.5 V. 15 GND Ground Reference Pin. 16 SDO

Serial Data Output. Used to clock data from the serial register in daisy-chain or readback mode. Data is

clocked out on the rising edge of SCLK and is valid on the falling edge of SCLK. 17 REFIN/REFOUT

External Reference Voltage Input and Internal Reference Voltage Output. Reference input range is 2 V to 3 V.

REFIN = 2.5 V for specified performance. REFOUT = 2.5 V ± 2 mV @ 25°C. 18, 19 DAC_GND Ground reference pins for the four digital-to-analog converters. 20, 21 SIG_GND Ground reference pins for the four output amplifiers. 22 V 23 V

D Analog Output Voltage of DAC D. The output amplifier is capable of directly driving a 2 kΩ, 4000 pF load.

OUT

C Analog Output Voltage of DAC C. The output amplifier is capable of directly driving a 2 kΩ, 4000 pF load.

OUT

24 AVDD Positive Analog Supply Pin. Voltage range is from 4.5 V to 16.5 V. 25 (EPAD)

Exposed Paddle (EPAD)

The exposed paddle should be connected to the potential of the AV

electrically unconnected. It is recommended that the paddle be thermally connected to a copper plane for

enhanced thermal performance.

24

DD

23

V

C

OUT

22

D

V

OUT

21

SIG_GND SIG_GND

20 19

DAC_GND

18

DAC_GND

17

REFIN/REFOUT

16

SDO

15

GND DV

14

CC

NC

13

06465-005

CC

. If LDAC is held high

pin or, alternatively, it can be left

SS

Rev. B | Page 10 of 32

ANALOG DEVICES AD5724R, AD5734R, AD5754R Service Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

FEATURES

APPLICATIONS

GENERAL DESCRIPTION

TABLE OF CONTENTS

REVISION HISTORY

FUNCTIONAL BLOCK DIAGRAM

SPECIFICATIONS

AC PERFORMANCE CHARACTERISTICS

TIMING CHARACTERISTICS

TIMING DIAGRAMS

ABSOLUTE MAXIMUM RATINGS

ESD CAUTION

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS