Analog Devices AD10465 Datasheet

Dual Channel, 14-Bit, 65 MSPS A/D Converter

a

with Analog Input Signal Conditioning

FEATURES
Dual, 65 MSPS Minimum Sample Rate

Channel-to-Channel Matching, ⴞ0.5% Gain Error
Channel-to-Channel Isolation, >90 dB
DC-Coupled Signal Conditioning Included

Selectable Bipolar Input Voltage Range

(ⴞ0.5 V, ⴞ1.0 V, ⴞ2.0 V)
Gain Flatness up to 25 MHz: < 0.2 dB
80 dB Spurious-Free Dynamic Range
Two’s Complement Output Format

3.3 V or 5 V CMOS-Compatible Output Levels

1.75 W per Channel
Industrial and Military Grade

APPLICATIONS
Phased Array Receivers
Communications Receivers
FLIR Processing
Secure Communications
GPS Antijamming Receivers
Multichannel, Multimode Receivers

PRODUCT DESCRIPTION

The AD10465 is a full channel ADC solution with on-module
signal conditioning for improved dynamic performance and fully
matched channel-to-channel performance. The module includes
two wide dynamic range AD6644 ADCs. Each AD6644 has a dc­coupled amplifier front end including an AD8037 low distortion,
high bandwidth amplifier, providing a high input impedance
and gain, and driving the AD8138 single-to-differential ampli­fier. The AD6644s have on-chip track-and-hold circuitry and

AD10465

utilize an innovative multipass architecture to achieve 14-bit,
65 MSPS performance. The AD10465 uses innovative high­density circuit design and laser-trimmed thin-film resistor networks
to achieve exceptional matching and performance, while still
maintaining excellent isolation and providing for significant
board area savings.

The AD10465 operates with ±5.0 V for the analog signal condi­tioning with a separate 5.0 V supply for the analog-to-digital
conversion and 3.3 V digital supply for the output stage. Each
channel is completely independent, allowing operation with
independent encode and analog inputs. The AD10465 also
offers the user a choice of analog input signal ranges to fur­ther minimize additional external signal conditioning, while
still remaining general-purpose.

The AD10465 is packaged in a 68-lead Ceramic Gull Wing
package, footprint-compatible with the earlier generation AD10242
(12-bit, 40 MSPS) and AD10265 (12-bit, 65 MSPS). Manufac­turing is done on Analog Devices, Inc. Mil-38534 Qualified
Manufacturers Line (QML) and components are available up to
Class-H (–40°C to +85°C). The AD6644 internal components
are manufactured on Analog Devices, Inc. high-speed comple­mentary bipolar process (XFCB).

PRODUCT HIGHLIGHTS

1. Guaranteed sample rate of 65 MSPS.

2. Input amplitude options, user configurable.

3. Input signal conditioning included; both channels matched
for gain.

4. Fully tested/characterized performance.

5. Footprint compatible family; 68-lead LCC.

FUNCTIONAL BLOCK DIAGRAM

DRAOUT

D0A (LSB)

D1A

D2A

D3A

D4A

D5A

D6A

D7A

D8A

D9A

D10A

AINA3 AINA2 AINA1

TIMING

ENC

ENC

VREF
DROUT

11

OUTPUT BUFFERING

14

3

D11A D12A

REF

D13A (MSB)

A

AD10465

D0B (LSB) D1B D3BD2B D4B D5B D6B D7B D8B

REV. 0

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.

AINB2 AINB1

AINB3

REF

B

DRBOUT

TIMING

VREF
DROUT

OUTPUT BUFFERING

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] World Wide Web Site: http://www.analog.com
Fax: [phone] © Analog Devices, Inc., 2001

14

9

5

ENC

ENC

D13B

D12B

D11B

D10B

D9B

AD10465–SPECIFICATIONS

(AVCC = +5 V; AVEE = –5 V; DVCC = 3.3 V applies to each ADC unless otherwise noted.)

Test Mil AD10465AZ/BZ/QML-H

Parameter Temp Level Subgroup Min Typ Max Unit

RESOLUTION 14 Bits

DC ACCURACY

No Missing Codes Full VI 1, 2, 3 Guaranteed
Offset Error 25°C I 1 –2.2 ± 0.02 +2.2 % FS

Full VI 2, 3 –2.2 ±1.0 +2.2 % FS

Offset Error Channel Match Full V –1 ±1.0 +1 %
Gain Error

1

25°C I 1 –3 –1.0 +1 % FS
Full VI 2, 3 –5 ±2.0 +5 % FS

Gain Error Channel Match 25°C I 1 –1.5 ± 0.5 +1.5 %

Max I 2 –3 ±1.0 +3 %
Min I 3 –5 +5 %

ANALOG INPUT (A

)

IN

Input Voltage Range

AIN1 Full V ±0.5 V

2 Full V ±1.0 V

A

IN

3 Full V ±2V

A

IN

Input Resistance

AIN1 Full IV 12 99 100 101 Ω

2 Full IV 12 198 200 202 Ω

A

IN

A

3 Full IV 12 396 400 404 Ω

IN

Input Capacitance
Analog Input Bandwidth

ENCODE INPUT (ENC, ENC)

Differential Input Voltage

2

3

4

17

25°C IV 12 0 4.0 7.0 pF
Full V 100 MHz

Full IV 0.4 V p-p

Differential Input Resistance 25°CV 10 kΩ
Differential Input Capacitance 25°C V 2.5 pF

SWITCHING PERFORMANCE

Maximum Conversion Rate
Minimum Conversion Rate
Aperture Delay (t

)25°C V 1.5 ns

A

5

5

Full VI 4, 5, 6 65 MSPS
Full V 12 20 MSPS

Aperture Delay Matching 25°C IV 12 250 500 ps
Aperture Uncertainty (Jitter) 25°C V 0.3 ps rms
ENCODE Pulsewidth High 25°C IV 12 6.2 7.7 9.2 ns
ENCODE Pulsewidth Low 25°C IV 12 6.2 7.7 9.2 ns
Output Delay (t
Encode, Rising to Data Ready, Rising Delay (T

6

SNR

) Full V 6.8 ns

OD

) Full 11.5 ns

E_DR

Analog Input @ 4.98 MHz 25°C V 70 dBFS
Analog Input @ 9.9 MHz 25°C I 4 69 70 dBFS

Full II 5, 6 68 70 dBFS

Analog Input @ 19.5 MHz 25°C I 4 68 70 dBFS

Full II 5, 6 67 70 dBFS

Analog Input @ 32.1 MHz 25°C I 4 67 69 dBFS

Full II 5, 6 67 69 dBFS

7

SINAD

Analog Input @ 4.98 MHz 25°CV 70 dB
Analog Input @ 9.9 MHz 25°C I 4 67.5 69 dB

Full II 5, 6 67.5 69 dB

Analog Input @ 19.5 MHz 25°CI 4 65 68 dB

Full II 5, 6 65 68 dB

Analog Input @ 32.1 MHz 25°CI 4 60 63 dB

Full II 5, 6 58 61 dB

–2–

REV. 0

AD10465

Test Mil AD10465AZ/BZ/QML-H

Parameter Temp Level Subgroup Min Typ Max Unit

SPURIOUS-FREE DYNAMIC RANGE

Analog Input @ 4.98 MHz 25°C V 85 dBFS
Analog Input @ 9.9 MHz 25°C I 4 73 82 dBFS

Analog Input @ 19.5 MHz 25°C I 4 72 78 dBFS

Analog Input @ 32.1 MHz 25°C I 4 62 68 dBFS

TWO-TONE IMD REJECTION

fIN = 10 MHz and 11 MHz 25°C I 4 78 87 dBFS

and f2 are –7 dB II 5, 6 78

f

1

f

= 31 MHz and 32 MHz 25°C I 4 68 70 dBFS

IN

f1 and f2 Are –7 dB Full II 5, 6 60

CHANNEL-TO-CHANNEL ISOLATION
TRANSIENT RESPONSE 25°C V 15.3 ns

OVERVOLTAGE RECOVERY TIME

VIN = 2.0 × f
VIN = 4.0 × f

DIGITAL OUTPUTS

S

S

12

Logic Compatibility CMOS

= 3.3 V

DV

CC

Logic “1” Voltage Full I 1, 2, 3 2.5 DV
Logic “0” Voltage Full I 1, 2, 3 0.2 0.5 V

= 5 V

DV

CC

Logic “1” Voltage Full V DV
Logic “0” Voltage Full V 0.35 V
Output Coding Two’s Complement

POWER SUPPLY

AV

Supply Voltage

CC

) Current Full I 270 308 mA

I (AV

CC

Supply Voltage

AV

EE

I (AV

) Current Full V 38 49 mA

EE

Supply Voltage

DV

CC

I (DV
I

) Current Full V 30 46 mA

CC

(Total) Supply Current per Channel Full I 1, 2, 3 338 403 mA

CC

13

13

13

Power Dissipation (Total) Full I 1, 2, 3 3.5 3.9 W
Power Supply Rejection Ratio (PSRR) Full V 0.02 % FSR/% V
Passband Ripple to 10 MHz V 0.1 dB
Passband Ripple to 25 MHz V 0.2 dB

NOTES

1

Gain tests are performed on AIN1 input voltage range.

2

Input Capacitance spec. combines AD8037 die capacitance and ceramic package capacitance.

3

Full power bandwidth is the frequency at which the spectral power of the fundamental frequency (as determined by FFT analysis) is reduced by 3 dB.

4

All ac specifications tested by driving ENCODE and ENCODE differentially.

5

Minimum and maximum conversion rates allow for variation in Encode Duty Cycle of 50% ± 5%.

6

Analog input signal power at –1 dBFS; signal-to-noise ratio (SNR) is the ratio of signal level to total noise (first five harmonics removed). Encode = 65 MSPS. SNR
is reported in dBFS, related back to converter full power.

7

Analog input signal power at –1 dBFS; signal-to-noise and distortion (SINAD) is the ratio of signal level to total noise + harmonics. Encode = 65 MSPS.

8

Analog input signal power swept from –1 dBFS to –60 dBFS; SFDR is ratio of converter full scale to worst spur.

9

Both input tones at –7 dBFS; two-tone intermodulation distortion (IMD) rejection is the ratio of either tone to the worst third order intermod product.

10

Channel-to-channel isolation tested with A channel grounded and a full-scale signal applied to B channel.

11

Input driven to 2× and 4× AIN1 range for > four clock cycles. Output recovers inband in specified time with Encode = 65 MSPS.

12

Digital output logic levels: DVCC = 3.3 V, C

13

Supply voltage recommended operating range. AVCC may be varied from 4.85 V to 5.25 V. However, rated ac (harmonics) performance is valid only over the range
AVCC = 5.0 V to 5.25 V.

All specifications guaranteed within 100 ms of initial power-up regardless of sequencing.
Specifications subject to change without notice.

8

Full II 5, 6 70 82 dBFS

Full II 5, 6 70 78 dBFS

Full II 5, 6 60 66 dBFS

9

10

11

25°CIV 12 90 dB

Full IV 12 40 100 ns
Full IV 12 150 200 ns

– 0.2 V

CC

– 0.3 V

CC

Full VI 4.85 5.0 5.25 V

Full VI –5.25 –5.0 –4.75 V

Full VI 3.135 3.3 3.465 V

S

= 10 pF. Capacitive loads > 10 pF will degrade performance.

LOAD

REV. 0

–3–

AD10465

ABSOLUTE MAXIMUM RATINGS

1

Parameter Min Max Units

ELECTRICAL

VCC Voltage 0 7 V

Voltage –7 0 V

V

EE

Analog Input Voltage V

EEVCC

V
Analog Input Current –10 +10 mA
Digital Input Voltage (ENCODE) 0 VCCV
ENCODE, ENCODE Differential Voltage 4 V
Digital Output Current –10 +10 mA

ENVIRONMENTAL

2

Operating Temperature (Case) –40 +85 °C
Maximum Junction Temperature 174 °C
Lead Temperature (Soldering, 10 sec) 300 °C
Storage Temperature Range (Ambient) –65 +150 °C

NOTES

1

Absolute maximum ratings are limiting values applied individually, and beyond

which the serviceability of the circuit may be impaired. Functional operability is
not necessarily implied. Exposure to absolute maximum rating conditions for an
extended period of time may affect device reliability.

2

Typical thermal impedance for “ES” package: θJC = 2.2°C/W; θJA = 24.3°C/W.

ORDERING GUIDE

Model Temperature Range Package Description

AD10465AZ –25°C to +85°C (Case) 68-Lead Ceramic Leaded Chip Carrier
AD10465BZ –40°C to +85°C (Case) 68-Lead Ceramic Leaded Chip Carrier
5962-9961601HXA –40°C to +85°C (Case) 68-Lead Ceramic Leaded Chip Carrier
AD10465/PCB 25°C Evaluation Board with AD10465AZ

TEST LEVEL

I. 100% Production Tested.
II. 100% Production Tested at 25°C, and sample tested at

specified temperatures. AC testing done on sample basis.

III. Sample Tested only.

IV. Parameter is guaranteed by design and characterization

testing.

V. Parameter is a typical value only.
VI. 100% production tested at temperature at 25°C, sample

tested at temperature extremes.

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD10465 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.

WARNING!

ESD SENSITIVE DEVICE

–4–

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AD10465

PIN FUNCTION DESCRIPTIONS

Pin No. Name Function

1 SHIELD Internal Ground Shield between channels.
2, 4, 5, 9–11 AGNDA A Channel Analog Ground. A and B grounds should be connected as close to the device

as possible.
3 REF_A A Channel Internal Voltage Reference.
6A
7A
8A
12 DRAOUT Data Ready A Output.
13 AV
14 AV
26, 27 DGNDA A Channel Digital Ground.
15–25, 31–33 D0A–D13A Digital Outputs for ADC A. D0 (LSB).
28 ENCODEA ENCODE is complement of ENCODE.
29 ENCODEA Data conversion initiated on rising edge of ENCODE input.
30 DV
43, 44 DGNDB B Channel Digital Ground.
34–42, 45–49 D0B-D13B Digital Outputs for ADC B. D0 (LSB).
53–54, 57–61, 65, 68 AGNDB B Channel Analog Ground. A and B grounds should be connected as close to the device

50 DV
51 ENCODEB Data conversion initiated on rising edge of ENCODE input.
52 ENCODEB ENCODE is complement of ENCODE.
55 DRBOUT Data Ready B Output.
56 REF_B B Channel Internal Voltage Reference.
62 A
63 A
64 A
66 AV
67 AV

A1 Analog Input for A side ADC (nominally ±0.5 V).

IN

A2 Analog Input for A side ADC (nominally ±1.0 V).

IN

A3 Analog Input for A side ADC (nominally ±2.0 V).

IN

EE

CC

CC

Analog Negative Supply Voltage (nominally –5.0 V or –5.2 V).

Analog Positive Supply Voltage (nominally 5.0 V).

Digital Positive Supply Voltage (nominally 5.0 V/3.3 V).

as possible.

CC

B1 Analog Input for B side ADC (nominally ±0.5 V).

IN

B2 Analog Input for B side ADC (nominally ±1.0 V).

IN

B3 Analog Input for B side ADC (nominally ±2.0 V).

IN

CC

EE

Digital Positive Supply Voltage (nominally 5.0 V/3.3 V).

Analog Positive Supply Voltage (nominally –5.0 V).

Analog Negative Supply Voltage (nominally –5.0 V or –5.2 V). .

REV. 0

AGNDA

AGNDA

DRAOUT

AV

AV

D0A(LSBA)

D1A
D2A

D3A

D4A

D5A

D6A
D7A
D8A

D9A

D10A

DGNDA

PIN CONFIGURATION

68-Lead Ceramic Leaded Chip Carrier

A

A3

A1

A2

IN

IN

IN

A

A

A

AGNDA

AGNDA

REF

AGNDA

9618765 686766656463624321

10

11

12

13

EE

14

CC

15

16

17

18

19

20

21

22

23

24

25

26

27 4328 29 30 31 32 33 34 35 36 37 38 39 40 41 42

CC

DGNDA

ENCODEA

DV

ENCODEA

AGNDA

AD10465

TOP VIEW

(Not to Scale)

D11A

D0B(LSBB)

D13A(MSBA)

D12A

EE

CC

AV

AV

AGNDB

SHIELD

PIN 1
IDENTIFIER

D4B

D3B

D1B

D2B

–5–

B3

B1

B2

IN

IN

IN

A

A

A

AGNDB

D7B

D8B

D6B

D5B

AGNDB

AGNDB

60

59

AGNDB

58

AGNDB

57

AGNDB

56

REF

B

55

DRBOUT

54

AGNDB

53

AGNDB

52

ENCODEB

ENCODEB

51

50

DV

CC

D13B(MSBB)

49

48

D12B

47

D11B

46

D10B

45

D9B

44

DGNDB

DGNDB

AD10465–Typical Performance Characteristics

dB

–100

–110

–120

–130

dB

–100

–110

–120

–130

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

0

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

0

ENCODE = 65MSPS
A

= 5MHz (–1dBFS)

IN

SNR = 71.02
SFDR = 92.11dBc

3

2

2.5

5.0 7.5 10.0 12.5 15.0 17.5 20.0 22.5 25.0 27.5 30.0 32.5

FREQUENCY – MHz

4

5

TPC 1. Single Tone @ 5 MHz

ENCODE = 65MSPS
A

= 20MHz (–1dBFS)

IN

SNR = 70.71
SFDR = 79.73dBc

3

2

6

4

2.5

5.0 7.5 10.0 12.5 15.0 17.5 20.0 22.5 25.0 27.5 30.0 32.5

FREQUENCY – MHz

0

5

ENCODE = 65MSPS
A

= 10MHz (–1dBFS)

IN

SNR = 70.79
SFDR = 86.06dBc

2

4

3

–10

–20

–30

–40

–50

–60

dB

–70

–80

6

–90

–100

–110

–120

–130

6

2.5

5.0 7.5 10.0 12.5 15.0 17.5 20.0 22.5 25.0 27.5 30.0 32.5

0

FREQUENCY – MHz

TPC 4. Single Tone @ 10 MHz

0

ENCODE = 65MSPS

–10

A

= 25MHz (–1dBFS)

IN

–20

SNR = 70.36
SFDR = 74.58dBc

–30

–40

–50

–60

dB

–70

–80

5

–90

–100

–110

–120

–130

2.5

5.0 7.5 10.0 12.5 15.0 17.5 20.0 22.5 25.0 27.5 30.0 32.5

0

3

2

5

FREQUENCY – MHz

6

4

dB

–100

–110

–120

–130

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

0

TPC 2. Single Tone @ 20 MHz

ENCODE = 65MSPS
A

= 32MHz (–1dBFS)

IN

SNR = 70.22
SFDR = 66.40dBc

2

6

4

2.5

5.0 7.5 10.0 12.5 15.0 17.5 20.0 22.5 25.0 27.5 30.0 32.5

FREQUENCY – MHz

TPC 3. Single Tone @ 32 MHz

TPC 5. Single Tone @ 25 MHz

100

90

80

70

60

3

5

–dBc

50

40

30

20

10

0

4.989

SFDR

SINAD

9.989 19.000 32.000

INPUT FREQUENCY – MHz

TPC 6. SFDR and SINAD vs. Frequency

–6–

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