ANALOG DEVICES AD10200 Service Manual

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Dual Channel, 12-Bit 105 MSPS IF Sampling

A/D Converter with Analog Input

a

FEATURES
Dual, 105 MSPS Minimum Sample Rate
Channel-Channel Isolation, >80 dB
AC-Coupled Signal Conditioning Included
Gain Flatness up to Nyquist: < 0.2 dB
Input VSWR 1.1:1 to Nyquist
80 dB Spurious-Free Dynamic Range
Two’s Complement Output Format

3.3 V or 5 V CMOS-Compatible Output Levels

0.850 W per Channel
Industrial and Military Grade

APPLICATIONS
Radar IF Receivers
Phased Array Receivers
Communications Receivers
Secure Communications
GPS Antijamming Receivers
Multichannel, Multimode Receivers

PRODUCT DESCRIPTION

The AD10200 is a full channel ADC solution with on-module
signal conditioning for improved dynamic performance and
fully matched channel-to-channel performance. The module

Signal Conditioning

AD10200

includes two wide-dynamic range ADCs. Each ADC has a
transformer coupled front-end optimized for Direct-IF sampling.
The AD10200 has on-chip track-and-hold circuitry, and utilizes
an innovative architecture to achieve 12-bit, 105 MSPS perfor­mance. The AD10200 uses innovative high-density circuit
design to achieve exceptional matching and performance while
still maintaining excellent isolation, and providing for significant
board area savings.

The AD10200 operates with 5.0 V supply for the analog-to­digital conversion. Each channel is completely independent
allowing operation with independent encode and analog inputs.
The AD10200 is packaged in a 68-lead ceramic chip carrier
package. Manufacturing is done on Analog Devices, Inc. MIL­38534 Qualified Manufacturers Line (QML) and components
are available up to Class-H (–55°C to +125°C).

PRODUCT HIGHLIGHTS

1. Guaranteed sample rate of 105 MSPS.

2. Input signal conditioning with full power bandwidth to
250 MHz.

3. Fully tested/characterized performance at 121 MHz A

4. Optimized for IF sampling.

.

IN

FUNCTIONAL BLOCK DIAGRAM

AINA2

7

34

D00A
(LSB)

D01A

D02A

D03A

D04A

D05A

D06A

D07A

D08A

D09A

D10A

D11A

(MSB)

33

32

31

30

29

28

25

24

23

22

OUTPUT RESISTORS

21

18 17

12 12

TIMING

ENCODEAENCODEA

T1A

50⍀

T/H T/H

ADC

REF

3

REF_A_OUT

REV. A

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.

AINB2

63

50

D00B
(LSB)

49

T1B

50⍀

AD10200

ADC

12 12

OUTPUT RESISTORS

REF

56

REF_B_OUT

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] © Analog Devices, Inc., 2001

TIMING

53 54

ENCODEBENCODEB

48

47

46

45

42

41

40

39

38

37

D01B

D02B

D03B

D04B

D05B

D06B

D07B

D08B

D09B

D10B

D11B
(MSB)

1

(V

AD10200–SPECIFICATIONS

= 3.3 V, VCC = 5.0 V; ENCODE = 105 MSPS, unless otherwise noted)

DD

Test MIL

Parameter Temp Level Subgroup Min Typ Max Unit

RESOLUTION 12 Bits

DC ACCURACY

Differential Nonlinearity Full IV 12 –0.99 ±0.5 +0.99 LSB
Integral Nonlinearity Full IV 12 –3 ± 0.75 +3 LSB
No Missing Codes Full I 1, 2, 3 Guaranteed
Gain Error

2

Full I 1, 2, 3 –9 ± 1+9% FS

Output Offset Full I 1, 2, 3 –12 +12 LSB

ANALOG INPUT

Input Voltage Range 25°C V 2.048 V p-p
Input Impedance 25°CV 50 Ω
Input VSWR

3

Full IV 12 1.1:1 1.25:1 Ratio
Analog Input Bandwidth, High Full IV 12 200 250 MHz
Analog Input Bandwidth, Low Full IV 12 1 MHz

ANALOG REFERENCE

Output Voltage Full I 1, 2, 3 2.4 2.5 2.6 V
Load Current 25°CV 5 mA
Tempco Full V 50 ppm/°C

SWITCHING PERFORMANCE

Maximum Conversion Rate Full I 4, 5, 6 105 MSPS
Minimum Conversion Rate Full IV 12 10 MSPS
Duty Cycle Full IV 12 45 50 55 %
Aperture Delay (t
Aperture Uncertainty (Jitter) 25°C V 0.25 ps rms
Output Valid Time (t
Output Propagation Delay (
Output Rise Time (t

)25°C V 1.0 ns

A

4

)

V

)25°C V 12 3.5 ns

R

PD

4

)

Full IV 12 3.0 5.3 ns

Full IV 12 4.5 5.5 8.0 ns

Output Fall Time (tF)25°C V 12 3.3 ns

DIGITAL INPUTS

Encode Input Common Mode Full IV 12 1.2 1.6 2.0 V
Differential Input (Enc, Enc) Full IV 12 0.4 5.0 V
Logic “1” Voltage Full IV 12 2.0 V
Logic “0” Voltage Full IV 12 0.8 V
Input Resistance Full IV 12 358kΩ
Input Capacitance 25°C V 4.5 pF

DIGITAL OUTPUTS

Logic “1” Voltage
Logic “0” Voltage

4

4

Full VI 1, 2, 3 3.1 3.3 V

Full VI 1, 2, 3 0 0.2 V
Output Coding Two’s Complement

POWER SUPPLY

Power Dissipation

5

6

Full I 1, 2, 3 1800 2200 mW
Power Supply Rejection Ratio Full IV 12 ± 0.5 ± 5 mV/V
I (DV

) Current Full I 1, 2, 3 25 40 mA

DD

I (AVCC) Current Full I 1, 2, 3 340 410 mA

DYNAMIC PERFORMANCE

Signal-to-Noise Ratio (SNR)

7

(Without Harmonics)

= 10 MHz 25°C V 67 dBFS

f

IN

Full V 66 dBFS

f

= 41 MHz 25°C I 4 64 66.5 dBFS

IN

Full II 5, 6 62 65 dBFS

= 71 MHz 25°C I 4 62.5 66.4 dBFS

f

IN

Full II 5, 6 61.5 64 dBFS

= 121 MHz 25°C I 4 61 65 dBFS

f

IN

Full II 5, 6 61 64 dBFS

–2–

REV. A

AD10200

Test MIL

Parameter Temp Level Subgroup Min Typ Max Unit

DYNAMIC PERFORMANCE
(Continued)

Signal-to-Noise Ratio (SINAD)
(With Harmonics)

f

= 10 MHz 25°C V 66 dBFS

IN

= 41 MHz 25°C I 4 63 65.5 dBFS

f

IN

f

= 71 MHz 25°C I 4 61 63.5 dBFS

IN

= 121 MHz 25°C I 4 56 58.5 dBFS

f

IN

Spurious Free Dynamic Range

fIN = 10 MHz 25°C V 81 dBFS

= 41 MHz 25°C I 4 73 81 dBFS

f

IN

f

= 71 MHz 25°C I 4 67 74 dBFS

IN

= 121 MHz 25°C I 4 61 65 dBFS

f

IN

Two-Tone Intermodulation
Distortion

f

f

f

10

(IMD)

= 10 MHz; fIN = 12 MHz 25°C V 86 dBc

IN

= 71 MHz; fIN = 72 MHz 25°C V 70 dBc

IN

= 121 MHz; fIN = 122 MHz 25°C I 4 55.5 62 dBc

IN

Channel-to-Channel Isolation

fIN = 121 MHz Full IV 12 80 85 dB

NOTES

1

All ac specifications tested by driving ENCODE and ENCODE differentially.

2

Gain Error measured at 2.5 MHz.

3

Input VSWR guaranteed 10 MHz to 200 MHz.

4

tV and tPD are measured from the transition points of the ENCODE input to the 50%/50% levels of the digital outputs swing. The digital output load during test is
not to exceed an ac load of 10 pF or a dc current of ± 40 mA.

5

Supply voltages should remain stable within ± 5% for normal operation.

6

Power dissipation measured with encode at rated speed and 0 dBm analog input.

7

Analog Input signal power at –1 dBFS; signal-to-noise ratio (SNR) is the ratio of signal level to total noise (first 5 harmonic removed). Encode = 105 MSPS. SNR
is reported in dBFS, related back to converter full scale.

8

Analog Input signal power at –1 dBFS; signal-to-noise and distortion (SINAD) is the ratio of signal level to total noise + harmonics. Encode = 105 MSPS. SINAD
is reported in dBFS, related back to converter full scale.

9

Analog Input signal equal –1 dBFS; SFDR is ratio of converter full scale to worst spur.

10

Both input tones at –7 dBFS; two tone intermodulation distortion (IMD) rejection is the ratio of either tone to the worst third order intermod product. f1 = x MHz
± 100 kHz, f2 = x MHz ± 100 kHz.

11

Channel-to-Channel isolation tested with A Channel/50 Ω terminated (AINA2) grounded and a full-scale signal applied to B Channel (AINB2).

Specifications subject to change without notice.

8

Full V 63 dBFS

Full II 5, 6 60.5 63 dBFS

Full II 5, 6 57 60 dBFS

9

Full II 5, 6 53 55 dBFS

Full V 70 dBFS

Full II 5, 6 67.5 dBFS

Full II 5, 6 60 dBFS

Full II 5, 6 55.5 58 dBFS

Full V 81 dBc

Full V 65 dBc

11

Full II 5, 6 53 57 dBc

REV. A

–3–

AD10200

ABSOLUTE MAXIMUM RATINGS

1, 2

VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 V

V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 V

CC

Analog Inputs . . . . . . . . . . . . . . . . . . . . . . . . 5 V

Digital Inputs . . . . . . . . . . . . . . . . . . . –0.5 V to V

p-p(18 dBm)

+ 0.5 V

DD

Digital Output Current . . . . . . . . . . . . . . . . . . . . . . . . 20 mA

Operating Temperature . . . . . . . . . . . . . . . . –55°C to +125°C

Storage Temperature . . . . . . . . . . . . . . . . . . –65°C to +150°C

Maximum Junction Temperature . . . . . . . . . . . . . . . . . 175°C

Maximum Case Temperature . . . . . . . . . . . . . . . . . . . . 150°C

NOTES

1

Stresses above those listed under Absolute Maximum Ratings may cause perma-

nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions outside of those indicated in the operation
sections of this specification is not implied. Exposure to absolute maximum ratings
for extended periods may affect device reliability.

2

Typical thermal impedances for “Z” package:

θJC = 2.22°C/W; θJA = 24.3°C/W.

EXPLANATION OF TEST LEVELS
Test Level

I. 100% production tested.
II. 100% production tested at 25°C and sample tested at

specific temperatures.
III. Sample tested only.
IV. Parameter is guaranteed by design and characterization

testing.
V. Parameter is a typical value only.
VI. 100% production tested at 25°C; guaranteed by design and

characterization testing for industrial temperature range.

Table I. Output Coding (VREF = 2.5 V) (Two’s Complement)

Code AIN (V) Digital Output

+2047 +1.024 0111 1111 1111

•• •

•• •
0 0 0000 0000 0000
–1 –0.00049 1111 1111 1111

•• •

•• •
–2048 –1.024 1000 0000 0000

ORDERING GUIDE

Model Temperature Range Package Description Package Option

AD10200BZ –40°C to +85°C (Case) 68-Lead Ceramic Leaded Chip Carrier Z-68B
5962-9961002HXA –40°C to +85°C (Case) 68-Lead Ceramic Leaded Chip Carrier Z-68B
5962-9961001HXA –55°C to +125°C (Case) 68-Lead Ceramic Leaded Chip Carrier Z-68B
AD10200/PCB Evaluation Board with AD10200BZ

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although

WARNING!

the AD10200 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.

ESD SENSITIVE DEVICE

–4–

REV. A

PIN CONFIGURATION

AD10200

CC

AV

D10B

DNC

AGNDB

D9B

D8B

B2

IN

A

D7B

NC

D6B

AGNDB

60

59

58

57

56

55

54

53

52

51

50

49

48

47

46

45

44

DGNDB

AGNDB

AGNDB

DNC

DNC

REF_B_OUT

AGNDB

ENCODEB

ENCODEB

AGNDB

DV

CC

D0B (LSB)

D1B

D2B

D3B

D4B

D5B

DGNDB

AGNDA

AGNDA

DNC

AGNDA

AV

DNC

AGNDA

ENCODEA

ENCODEA

AGNDA

DV

(MSB) D11A

D10A

D9A

D8A

D7A

DGNDA

A2

IN

NC

DNC

AGNDA

A

AGNDA

9618 7 6 5 68 67 66 65 64 63 624321

10

11

12

13

14

CC

15

16

17

18

19

20

CC

21

22

23

24

25

26

27 4328 29 30 31 32 33 34 35 36 37 38 39 40 41 42

D6A

D5A

D4A

DGNDA

NC = NO CONNECT

D3A

VREF_A_OUT

AGNDA

DNC

AD10200

TOP VIEW

(Not to Scale)

D2A

D1A

(LSB) D0A

SHIELD

PIN 1
IDENTIFIER

AGNDA

DNC

AGNDB

AGNDB

(MSB) D11B

PIN FUNCTION DESCRIPTIONS

Pin No. Mnemonic Function

1 SHIELD Internal Ground Shield between Channels
2, 5, 9–11, 13, 16, 19, 35 AGNDA A Channel Analog Ground. A and B grounds should be connected as close to

the device as possible.
3 VREF_A_OUT A Channel Internal Voltage Reference
6, 62 NC No Connection
7A

A2 Analog Input for A Side ADC

IN

4, 8, 12, 15, 57, 58, 64, 67 DNC Do Not Connect
14, 66 AV

CC

Analog Positive Supply Voltage (Nominally 5.0 V)
17 ENCODEA Complement of Encode
18 ENCODEA Data conversion initiated on the rising edge of ENCODE input.
20 DV

CC

Digital Positive Supply Voltage (Nominally 3.3 V)
21–25, 28–34 D11A–D7A, Digital Outputs for ADC A. D0 (LSB)

D6A–D0A
26, 27 DGNDA A Channel Digital Ground
36, 52, 55, 59–61, 65, 68 AGNDB B Channel Analog Ground. A and B grounds should be connected as close to

the device as possible.

37–42, 45–50 D11B–D6B, Digital Outputs for ADC B. D0 (LSB)

D5B–D0B
43, 44 DGNDB B Channel Digital Ground
51 DV

CC

Digital Positive Supply Voltage (Nominally 3.3 V)

53 ENCODEB Data conversion initiated on rising edge of ENCODE input.
54 ENCODEB Complement of Encode
56 VREF_B_OUT B Channel Internal Voltage Reference
63 AINB2 Analog Input for B Side ADC

REV. A

–5–

AD10200

DEFINITION OF SPECIFICATIONS
Analog Bandwidth

The analog input frequency at which the spectral power of the
fundamental frequency (as determined by the FFT analysis) is
reduced by 3 dB.

Aperture Delay

The delay between the 50% point on the rising edge of the
ENCODE command and the instant at which the analog input
is sampled.

Aperture Uncertainty (Jitter)

The sample-to-sample variation in aperture delay.

Differential Nonlinearity

The deviation of any code from an ideal 1 LSB step.

Encode Pulsewidth/Duty Cycle

Pulsewidth high is the minimum amount of time that the
ENCODE pulse should be left in Logic “1” state to achieve
rated performance; pulsewidth low is the minimum time
ENCODE pulse should be left in low state. At a given clock
rate, these specs define an acceptable Encode duty cycle.

Harmonic Distortion

The ratio of the rms signal amplitude to the rms value of the
worst harmonic component.

Integral Nonlinearity

The deviation of the transfer function from a reference line
measured in fractions of 1 LSB using a “best straight line”
determined by a least square curve fit.

Minimum Conversion Rate

The encode rate at which the SNR of the lowest analog signal
frequency drops by no more that 3 dB below the guaranteed limit.

Maximum Conversion Rate

The encode rate at which parametric testing is performed.

Output Propagation Delay

The delay between the 50% point of the rising edge of ENCODE
command and the time when all output data bits are within
valid logic levels.

Overvoltage Recovery Time

The amount of time required for the converter to recover to

0.02% accuracy after an analog input signal of the specified
percentage of full scale is reduced to midscale.

Power Supply Rejection Ratio

The ratio of a change in output offset voltage to a change in
power supply voltage.

Signal-to-Noise-and-Distortion (SINAD)

The ratio of the rms signal amplitude (set a 1 dB below full scale)
to the rms value of the sum of all other spectral components,
excluding the first five harmonics and dc. [May be reported in
dBc (i.e., degrades as signal levels is lowered) or in dBFS (always
related back to converter full scale)].

Signal-to-Noise Ratio (without Harmonics)

The ratio of the rms signal amplitude (set a I dB below full
scale) to the rms value of the sum of all other spectral compo­nents, excluding the first five harmonics and dc. [May be
reported in dBc (i.e., degrades as signal levels is lowered) or in
dBFS (always related back to converter full scale).]

Spurious-Free Dynamic Range

The ratio of the rms signal amplitude to the rms value of the
peak spurious spectral component. The peak spurious compo­nent may or may not be a harmonic. [May be reported in dBc
(i.e., degrades as signal levels is lowered) or in dBFS (always
related back to converter full scale).]

Transient Response

The time required for the converter to achieve 0.02% accu­racy when a one-half full-scale step function is applied to the
analog input.

Two-Tone Intermodulation Distortion Rejection

The ratio of the rms value of either input tone to the rms value of
the worst third order intermodulation product; reported in dBc.

Voltage Standing-Wave Ratio (VSWR)

The ratio of the amplitude of the elective field at a voltage maxi­mum to that at an adjacent voltage minimum.

–6–

REV. A

AD10200Typical Performance Characteristics–

0

ⴚ10

ⴚ20

ⴚ30

ⴚ40

ⴚ50

ⴚ60

dB

ⴚ70

ⴚ80

ⴚ90

ⴚ100

ⴚ110

ⴚ120

ⴚ130

0

0

ENCODE = 105 MSPS

ⴚ10

A
SNR = 66.04dBFS

ⴚ20

SFDR = 79.71dBc

ⴚ30

ⴚ40

ⴚ50

ⴚ60

dB

ⴚ70

ⴚ80

ⴚ90

ⴚ100

ⴚ110

ⴚ120

ⴚ130

0

ENCODE = 105 MSPS

= 10MHz (–1dBFS)

A

IN

SNR = 66.84dBFS
SFDR = 82.28dBc

5 101520253035404550

FREQUENCY – MHz

TPC 1. Single Tone @ 10 MHz

= 71MHz (–1dBFS)

IN

5 101520253035404550

FREQUENCY – MHz

0

ENCODE = 105 MSPS

ⴚ10

A

IN

SNR = 66.06dBFS

ⴚ20

SFDR = 80.59dBc

ⴚ30

ⴚ40

ⴚ50

ⴚ60

dB

ⴚ70

ⴚ80

ⴚ90

ⴚ100

ⴚ110

ⴚ120

ⴚ130

0

0

ⴚ10

ⴚ20

ⴚ30

ⴚ40

ⴚ50

ⴚ60

dB

ⴚ70

ⴚ80

ⴚ90

ⴚ100

ⴚ110

ⴚ120

ⴚ130

0

= 41MHz (–1dBFS)

5 101520253035404550

FREQUENCY – MHz

TPC 4. Single Tone @ 41 MHz

ENCODE = 105 MSPS
A

= 121MHz (–1dBFS)

IN

SNR = 64.92dBFS
SFDR = 64.73dBc

5 101520253035404550

FREQUENCY – MHz

ⴚ10

ⴚ20

ⴚ30

ⴚ40

ⴚ50

ⴚ60

dB

ⴚ70

ⴚ80

ⴚ90

ⴚ100

ⴚ110

ⴚ120

ⴚ130

TPC 2. Single Tone @ 71 MHz

0

0

5 101520253035404550

FREQUENCY – MHz

ENCODE = 105 MSPS

= 121MHz (–6dBFS)

A

IN

SNR = 66.9dBFS
SFDR = 65.57dBc

TPC 3. Single Tone @ 121 MHz

ⴚ10

ⴚ20

ⴚ30

ⴚ40

ⴚ50

ⴚ60

dB

ⴚ70

ⴚ80

ⴚ90

ⴚ100

ⴚ110

ⴚ120

ⴚ130

TPC 5. Single Tone @ 121 MHz

0

0

5 101520253035404550

FREQUENCY – MHz

ENCODE = 105 MSPS

= 201MHz (–10dBFS)

A

IN

SNR = 66.84dBFS
SFDR = 64.57dBc

TPC 6. Single Tone @ 201 MHz

REV. A

–7–

AD10200

0

ENCODE = 105 MSPS

ⴚ10

A

= 37MHz & 38MHz (–10dBFS)

IN

ⴚ20

SFDR = 79.84dBc

ⴚ30

ⴚ40

ⴚ50

ⴚ60

dBc

ⴚ70

ⴚ80

ⴚ90

ⴚ100

ⴚ110

ⴚ120

ⴚ130

0

5 1015202530 35404550

FREQUENCY – MHz

TPC 7. Two-Tone @ 37 MHz/38 MHz

ⴚ10

ⴚ20

ⴚ30

ⴚ40

ⴚ50

ⴚ60

dBc

ⴚ70

ⴚ80

ⴚ90

ⴚ100

ⴚ110

ⴚ120

ⴚ130

0

0

5 101520253035404550

ENCODE = 105 MSPS
A

= 120MHz & 121MHz (–7dBFS)

IN

SFDR = 63.8dBc

FREQUENCY – MHz

TPC 8. Two-Tone @ 120 MHz/121 MHz

0

ENCODE = 105 MSPS

ⴚ10

A

= 71MHz & 72MHz (–7dBFS)

IN

SFDR = 74.8dBc

ⴚ20

ⴚ30

ⴚ40

ⴚ50

ⴚ60

dBc

ⴚ70

ⴚ80

ⴚ90

ⴚ100

ⴚ110

ⴚ120

ⴚ130

0

5 101520253035404550

FREQUENCY – MHz

TPC 10. Two-Tone @ 71 MHz/72 MHz

3.0

ENCODE = 105 MSPS
DNL MAX = 0.486 Codes

2.5

DNL MIN = 0.431 Codes

2.0

1.5

1.0

LSB

0.5

0.0

ⴚ0.5

ⴚ1.0

0

512 1024 1536 2048 2560 3072 3584 4096

TPC 11. Differential Nonlinearity

3

ENCODE = 105 MSPS
INL MAX = 0.874 Codes
INL MIN = 0.895 Codes

2

1

0

LSB

ⴚ1

ⴚ2

ⴚ3

512 1024 1536 2048 2560 3072 3584 4096

0

TPC 9. Integral Nonlinearity

–8–

0

ⴚ

1

2

ⴚ

3

ⴚ

4

ⴚ

ⴚ

5

dBFS

ⴚ6

ⴚ7

ⴚ8

ⴚ9

ⴚ10

3.0

32.7 62.4 92.1 121.8 151.5 181.2 210.9 240.6
MHz

TPC 12. Gain Flatness

ENCODE = 105 MSPS
3dB = 261MHz

270.3 300.0

REV. A

10MHz = 50.22 + j.173

V

CC

Q1
NPN

V

REF

OUTPUT

V

CC

50MHz = 48.79 – j4.2
100MHz = 46.95 – j5.9
150MHz = 48.55 – j4.66

TPC 13. Input Impedance S11

AD10200

11

10MHz = 1.0149
50MHz = 1.085

10

100MHz = 1.130
150MHz = 1.092

9

8

7

6

5

4

3

2

1

3.0 32.7 62.4 92.1 121.8 151.5 181.2 210.9 240.6
MHz

TPC 14. Voltage Standing Wave Ratio (VSWR)

270.3 300.0

SAMPLE N–1

AIN

ENCODE

ENCODE

D11⬇D0

SAMPLE N

SAMPLE N+1

DATA N⬇11 DATA N⬇ 10 N⬇9 DATA N⬇1 DATA N DATA N + 1

Figure 1. Timing Diagram

V

CC

17k⍀

ENCODE ENCODE

100⍀

8k⍀

17k⍀

100⍀

8k⍀

Figure 2. Equivalent Encode Input Circuit

SAMPLE N+10 SAMPLE N+11

SAMPLE N+9

1/f

S

t

PD

N⬇2

t

V

Figure 4. Equivalent Voltage Reference Output Circuit

V

CC

V

CC

A

IN

100⍀

DIGITAL
OUTPUT

REV. A

Figure 3. Equivalent Digital Output Circuit

Figure 5. Equivalent Analog Input Circuit

–9–

50⍀

5k⍀

7k⍀

5k⍀

7k⍀

AD10200

APPLICATION NOTES

Theory of Operation

The AD10200 is a high-dynamic range dual 12-bit, 105 MHz
subrange pipeline converter that uses switched capacitor
architecture. The analog input section uses A

A2/AINB2 at

IN

2.048 V p-p with an input impedance of 50 Ω. The analog input
includes an ac-coupled wide-band 1:1 transformer, which provides
high-dynamic range and SNR while maintaining VSWR and
gain flatness. The ADC includes a high-bandwidth linear track/
hold that gives excellent spurious performance up to and beyond
the Nyquist rate. The high-bandwidth track/hold has a low jitter
of 0.25 ps rms, leading to excellent SNR and SFDR performance.
AC-coupled differential PECL/ECL encode inputs are recom­mended for optimum performance.

USING THE AD10200
ENCODE Input

Any high speed A/D converter is extremely sensitive to the quality
of the sampling clock provided by the user. A track/hold circuit
is essentially a mixer, and any noise, distortion, or timing jitter
on the clock will be combined with the desired signal at the A/D
output. For that reason, considerable care has been taken in the
design of the ENCODE input of the AD10200, and the user is
advised to give commensurate thought to the clock source. The
ENCODE input are fully TTL/CMOS compatible. For opti­mum performance, the AD10200 must be clocked differentially.

Note that the ENCODE inputs cannot be driven directly from
PECL level signals (V

is 3.5 V max). PECL level signals can

IHD

easily be accommodated by ac coupling as shown in Figure 6.
Good performance is obtained using an MC10EL16 in the
circuit to drive the encode inputs.

PECL
GATE

510⍀

GND

510⍀

0.1␮F

0.1␮F

AD10200

ENCODE

ENCODE

Figure 6. AC Coupling to ENCODE Inputs

ENCODE Voltage Level Definition

The voltage level definitions for driving ENCODE and ENCODE
in differential mode are shown in Figure 7.

ENCODE Inputs

Differential Signal Amplitude (VID) 500 mV min,

750 mV nom
High Differential Input Voltage (V
Low Differential Input Voltage (V
Common-Mode Input (V

ENCODE

ENCODE

ENCODE

) 1.25 V min, 1.6 V nom

ICN

V

IHD

V

ICM

V

ILD

V

IHS

) 5.0 V max

IHD

) 0 V min

ILD

V

ID

Often, the cleanest clock source is a crystal oscillator producing
a pure sine wave. In this configuration, or with any roughly
symmetrical clock input, the input can be ac-coupled and biased
to a reference voltage that also provides the ENCODE. This
ensures that the reference voltage is centered on the encode signal.

Digital Outputs

The digital outputs are TTL/CMOS-compatible and a separate
output power supply pin supports interfacing with 3.3 V logic.

Analog Input

The analog input is a single ended ac-coupled high performance
1:1 transformer with an input impedance of 50 Ω to 105 MHz.
The nominal full scale input is 2.048 V p-p.

Special care was taken in the design of the analog input section
of the AD10200 to prevent damage and corruption of data when
the input is overdriven.

Voltage Reference

A stable and accurate 2.5 V voltage reference is designed into
the AD10200 (VREFOUT). An external voltage reference is
not required.

Timing

The AD10200 provides latched data outputs, with 10 pipeline
delays. Data outputs are available one propagation delay (t

PD

)
after the rising edge of the encode command (see Figure 1). The
length of the output data lines and loads placed on them should
be minimized to reduce transients within the AD10200; these
transients can detract from the converter's dynamic performance.

The minimum guaranteed conversion rate of the AD10200 is
10 MSPS. At internal clock rates below 10 MSPS, dynamic
performance may degrade. Therefore, input clock rates below
10 MHz should be avoided.

GROUNDING AND DECOUPLING
Analog and Digital Grounding

Proper grounding is essential in any high speed, high resolution
system. Multilayer printed circuit boards (PCBs) are recom­mended to provide optimal grounding and power schemes. The
use of ground and power planes offers distinct advantages:

1. The minimization of the loop area encompassed by a signal

and its return path.

2. The minimization of the impedance associated with ground

and power paths.

3. The inherent distributed capacitor formed by the power

plane, PCB insulation and ground plane.

These characteristics result in both a reduction of electromagnetic
interference (EMI) and an overall improvement in performance.

It is important to design a layout that prevents noise from cou­pling to the input signal. Digital signals should not be run in
parallel with input signal traces and should be routed away from
the input circuitry. The PCB should have a ground plane covering
all unused portions of the component side of the board to pro­vide a low impedance path and manage the power and ground
currents. The ground plane should be removed from the area
near the input pins to reduce stray capacitance.

0.1␮F
V

ILS

Figure 7. Differential Input Levels

–10–

REV. A

AD10200

LAYOUT INFORMATION

The schematic of the evaluation board (Figure 8) represents
a typical implementation of the AD10200. The pinout of the
AD10200 is very straightforward and facilitates ease of use and
the implementation of high frequency/high resolution design
practices. It is recommended that high quality ceramic chip
capacitors be used to decouple each supply pin to ground directly
at the device. All capacitors can be standard high quality ceramic
chip capacitors.

Care should be taken when placing the digital output runs.
Because the digital outputs have such a high-slew rate, the
capacitive loading on the digital outputs should be minimized.
Circuit traces for the digital outputs should be kept short and
connect directly to the receiving gate. Internal circuitry buffers
the outputs of the ADC through a resistor network to eliminate
the need to externally isolate the device from the receiving gate.

EVALUATION BOARD

The AD10200 evaluation board (Figure 9) is designed to
provide optimal performance for evaluation of the AD10200
analog-to-digital converter. The board encompasses everything
needed to ensure the highest level of performance for evaluating
the AD10200. The board requires an analog input signal, encode
clock and power supply inputs. The clock is buffered on-board
to provide clocks for the latches. The digital outputs and out
clocks are available at the standard 40-pin connectors J1 and J2.

Power to the analog supply pins is connected via banana jacks.
The analog supply powers the associated components and the
analog section of the AD10200. The digital outputs of the
AD10200 are powered via banana jacks with 3.3 V. Contact the
factory if additional layout or applications assistance is required.

REV. A

Figure 8. Evaluation Board Mechanical Layout

–11–

AD10200

40393837363534333231302928272625242322

J1

H40DM

123456789

B9A

B8A

B10A

(MSB) B11A

ⴙ

C15

10␮F

ⴙ3.3VDA

B11A (MSB)

B9A

R18

R16

100⍀

B10A

R17

100⍀

DGNDA

DGNDA

242322212019181716151413121110

O15

O14

I15

D11A

I14

D10A

GND

GND

DGNDA

O13

I13

D9A

OE2

U16

LE2

2526272829303132333435363738394041424344454647

B7A

100⍀

R40

B6A

DGNDA

B8A

100⍀

O12

I12

D8A

10111213141516

B5A

B4A

50⍀

R71

BUFLATA

B6A

DUT_3.3VDA

R45

100⍀

B7A

R44

100⍀

O11

O10

VCC

VCC

I11

I10

D6A

D7A

DUT_3.3VDA

B3A

B2A

B1A

(LSB) B0A

B5A

R46

R14

100⍀

B4A

R15

100⍀

DGNDA

O9O8O7

GND

GNDI9I8I7I6

D4A

D5A

DGNDA

21

DGNDA

17

181920

F3A

F2A

F1A

F0A

DGNDA

B3A

B1A (LSB)

R24

100⍀

100⍀

B2A

B0A

R13

R23

100⍀

100⍀

DGNDA

987654321

O6

O5

O4

GND

GNDI5I4

D1A

D2A

D3A

DGNDA

(LSB) D0A

F3A

R22

DNS

R21

DUT_3.3VDA

O3

VCC

VCCI3I2

DUT_3.3VDA

0⍀

R52

R51

F2A

DNS

O2

0⍀

F1A

R20

DNS

DGNDA

O1

GND

GNDI1I0

DGNDA

0⍀

R47

R19

R48

F0A

O0

DNS

0⍀

DGNDA

OE1

LE1

48

40393837363534333231302928272625242322

J2

H40DM

123456789

B9B

B8B

B10B

(MSB) B11B

ⴙ

C14

10␮F

ⴙ3.3VDB

B11B (MSB)

R18

R16

100⍀

B10B

R17

100⍀

DGNDB

DGNDB

242322212019181716151413121110

O15

O14

OE2

GND

LE2

I15

I14

GND

2526272829303132333435363738394041424344454647

D10A

D11A

DGNDB

74LCX16374

R7

50⍀

LATCHA

DGNDA

U17

B9B

O13

I13

D9A

B7B

DGNDB

100⍀

B8B

R40

O12

I12

D8A

10111213141516

B6B

B5B

B4B

R72

BUFLATB

DUT_3.3VDB

R45

B7B

R44

100⍀

100⍀

O11

VCC

VCC

I11

D7A

DUT_3.3VDB

B3B

B2B

50⍀

B6B

B5B

R46

100⍀

100⍀

R15

DGNDB

O9O8O7

O10

GND

I10

GNDI9I8I7I6

D5A

D6A

DGNDB

B1B

(LSB) B0B

R14

B4B

100⍀

D4A

21

17

181920

F3B

F2B

F1B

F0B

DGNDB

B3B

B1B (LSB)

R24

100⍀

100⍀

B2B

R13

100⍀

DGNDB

987654321

O6

O5

GND

GNDI5I4

D1A

D2A

D3A

DGNDB

DGNDB

B0B

R23

100⍀

O4

(LSB) D0A

F3B

R22

DNS

F2B

R21

DUT_3.3VDB

O3

O2

VCC

VCCI3I2

DUT_3.3VDB

0⍀

R53

R54

DNS

DGNDB

GND

GNDI1I0

DGNDB

0⍀

R20

R49

F1B

O1

DNS

R19

0⍀

R50

F0B

O0

DNS

0⍀

DGNDB

OE1

LE1

48

74LCX16374

R8

50⍀

LATCHB

DGNDB

E50

C36

DNS

AGNDB

AGNDB AGNDB

6059585756555453525150494847464544

AGNDB

J6

SMA

DNS

AGNDA

J7

SMA

E49

AGNDB

(NC)
AGNDA

ⴙ5VAB_

(NC)
AGNDB

LID

AGNDA

C37

DNS

AGNDA

AGNDA

AGNDA

(NC)
AGNDA

AGNDA

AGNDA

C33

0.1␮F

J4

SMA

J3

DNS

SMA

AGNDB

AGNDB

AGNDB

61

IN

A

B1

62

IN

B2

A

63

SDIN_B

64

AGNDB

65

ⴙ5VAB

66

SCLK_B

67

AGNDB

68

SHIELD

1

AGNDA

2

REF_A

3

SDIN_A

4

AGNDA

5

IN

A1

A

6

IN

A2

A

7

VFU_A

5

AGNDA

9

AGNDA

AGNDA

SDOUT_A

1011121314151617181920212223242526

AGNDA

AGNDA

VFU_B

AGNDA

NC

AGNDA

NC

REF_B

SDOUT_B

ⴙ5VAA

SCLK_A

NC

ⴙ5VAA_

C35

0.1␮F

AGNDB

ENCBB

ENCBB

AGNDB

AGNDA

AGNDA

C34

0.1␮F

AGNDB

ENCB

AGNDB

ENCB

AGNDB

U1

AD10200

ENCAB

ENCA

ENCA

ENCAB

AGNDA

DUT_3.3VDB

C18

0.1␮F

D0B

D1B

D1B

ⴙ3.3VDB

D0B (LSB)

AGNDA

ⴙ3.3VDA

D11A (MSBA)

D11A

AGNDA

C10

DUT_3.3VDA

U17

D2B

D2B

D10A

D10A

0.1␮F

D9A

D9A

U1

DGNDB

D3B

D3B

D4B

D5B

D4B

D5B

D8A

D7A

D8A

D7A

DGNDA

DGNDB

DGNDB

DGNDA

DGNDA

DGNDB

43

D6B

42

D7B

41

D8B

40

D9B

39

D10B

38

D11B (MSBB)

37

AGNDB

36

AGNDA

35

D0A (LSBA)

34

D1A

33

D2A

32

D3A

31

D4A

30

D5A

29

D6A

28

DGNDA

27

NC = NO CONNECT

D6B
D7B

D8B

D9B

D0A

D1A
D2A

D3A
D4A

D5A

D6A

D10B

D11B

DGNDB

AGNDB

AGNDA

DGNDA

L1

ⴙ3.3VDA

ⴙ5AA_

L3

47⍀

E6

ⴙ5AA

DUT_3.3VDA

47⍀

ⴞ20%

@100MHz

U1

C12

0.1␮F

ⴙ

C29

10␮F

E25

U1

C20

ⴞ20%

@100MHz

ⴙ

C3

10␮F

0.1␮F

AGNDA

AGNDA

DGNDA

ⴙ3.3VDB

ⴙ5AB

DUT_3.3VDB

L2

47⍀

U8

E26

ⴙ5AB_

L4

E5

ⴞ20%

@100MHz

C16

0.1␮F

ⴙ

C30

10␮F

U1

47⍀

C4

C21

0.1␮F

ⴞ20%

@100MHz

ⴙ

10␮F

AGNDB

AGNDB

DGNDB

Figure 9a. Evaluation Board

–12–

REV. A

AD10200

ENCODE

SMA

AGNDA

J10

ENCODE

SMA

AGNDB

U14

3

C2

0.1␮F

C23

0.1␮F

E3
E4

E33

E34

2

DGNDA

3

2

DGNDB

DGNDA

R58

33k⍀

U15

DGNDB

R39

33k⍀

AGNDB
AGNDA

DGNDB

DGNDA

+5VAA_

C1

R1

50⍀

AGNDA

R60

50⍀

AGNDB

0.1␮F

J12

SMA

R41

50⍀

AGNDA

+5VAB_

C22

0.1␮F

J11

SMA

R61

50⍀

AGNDB

BANANA JACKS FOR GNDS AND PWRS

DGNDB

DGNDA

J5

ERR

ADP3330

IN

SD

6

ERR

ADP3330

IN

SD

6

NR
OUT

SD

C6

0.1␮F

1
2
3
4

NR
OUT

SD

C25

0.1␮F

1
2
3
4

5

4

1
2
3
4

5

4

1
2
3
4

1

AGNDA

NC
D
DB
VBB

MC10EL16

U3

NC

VCC
D
DB
VBB

VEE

MC10EL16

1

AGNDB

U11

NC
D
DB
VBB

MC10EL16

U9

VCC

NC
D
DB

VEE

VBB

MC10EL16

U2

33k⍀

QB

33k⍀

QB

R56

Q

R38

Q

VCC

QB

VEE

VCC

QB

VEE

0.47␮F

Q

8
7
6
5

DGNDA

0.47␮F

Q

8
7
6
5

DGNDB

C13

8
7
6
5

AGNDA

DGNDA

+3.3VA

C27

8
7
6
5

AGNDB

DGNDA

+3.3VDB

DGNDA

DGNDB

AGNDA

+3.3VA

R3
100⍀

R4

100⍀

1

DGNDA

AGNDB

+3.3VB

2

R3
100⍀

R66

100⍀

DGNDB

E42

E41
E43

E44
E48

E47

E67

E68

E70

E69

E72

E71

E73

E74

E76

E75

E81

E82

AGNDA

E29 E30

E35

E36

E37

E38

E39

E40

E80

E79

E83

E84

AGNDB

R43

100⍀

R64

100⍀

R42
100⍀

AGNDA

1
2
3
4

MC100EPT23

R63
100⍀

AGNDB

1
2
3
4

MC100EPT23

C7

0.1␮F
ENCAB
ENCAB

C8

0.1␮F

DGNDA

U4

D0

VCC

D0B

Q0

D1B

Q1

D1

VEE

NC = NO CONNECT

C24

0.1␮F
ENCBB
ENCB

C28

0.1␮F

DGNDB

U10

D0

VCC

D0B

Q0

D1B

Q1

D1

VEE

NC = NO CONNECT

E65E66

E46E45

C5

0.1␮F

8

+3.3VA

7
6
5

DGNDA

C26

0.1␮F

8

+3.3VB

7
6
5

DGNDB

LATCHA

E23

E19

BUFLATA

LATCHB

E24

E22

BUFLATB

REV. A

STAND OFFS ON THE BOARD

Figure 9b. Evaluation Board

–13–

SO4

SO1
SO2 SO5
SO3 SO6

AD10200

BILL OF MATERIALS LIST FOR AD10200 EVAL BOARD

Qty. Component Name Ref Des Value Description M/S P/Ns

2 74LCX16373MTD U16, U17 74LCX16374MTD (Fairchild)
1 AD10200BZ U1 AD10200BZ
2 ADP3330 U14, U15 SM 3.3 V Regulator ADP3330ART-3.3-RL7 (Analog)
4 BRES0805 R38, R39, R56, R58 33 kΩ SM 0805 Resistor ERJ6GEYJ333V (Panasonic)
4 BRES0805 R1, R41, R60, 50 Ω SM 0805 Resistor ERJ6GEYJ510V (Panasonic)

R61

8 BRES0805 R3, R4, R42, R43, 100 Ω SM 0805 Resistor ERJ6GEYJ101V (Panasonic)

R63, R64, R65, R66

23 CAP2 C1, C2, C5, C6, 0.1 µF SM 0805 Capacitor GRM40X7R104K025BL

C7, C8, C9, C10, (MENA)
C12, C16, C17, C18,
C20, C21, C22, C23,
C24, C25, C26, C28,
C33, C34, C35

4 CAP2 C13, C27, C38, C39 0.47 µF SM 1206 Capacitor VJ1206U474MFXMB

(VITRAMON)
2 N49DM J1, J2 2×20×100 Male Connector TSW-120-08G-D (Samtec)
4 IND2 L1, L2, L3, L4 47 Ω Inductor 2743019447 (Fair Ride)
4 MC10EL16 U2, U3 U9, U11 MC1016EP16D (Motorola)
10 BJACK BJ1 – BJ10 POWER JACK 108-0740-001 (Johnson Comp.)
2 MC100ELT23 U4, U10 SY100ELT23L (Micrel-Synergy)
6 POLCAP2 C3, C4, C14, C15, 10 µF SM 1812 Polar Capacitor T491C106M016A57280

C29, C30 (KEMET)

8 RES2 R47, R48, R49, 0 Ω SM 0805 Resistor ERJ-6GEY0R00V (Panasonic)

R50, R51, R52,

R53, R54
4 RES4 R7, R8, R71, R72 50 Ω SM 0805 Resistor ERJ-6GEYJ510V (Panasonic)
24 RES2 R9, R10, R11, R12,

R13, R14, R15, R16,

R17, R18, R23, R24,

R25, R26, R27, R28,

R29, R30, R35, R36,

R40, R44, R45, R46
1 SMA J4 A
1 SMA J7 A
2 SMA J11, J12 ENCODE 142-0701-201 (Johnson Comp.)
2 SMA J5, J10 ENCODE 142-0701-201 (Johnson Comp.)
4 Stand-Off S01–S04 Stand-Off 313-2477-016 (Johnson Comp.)
4 Screws Screws (Stand-Off) MPMS 0040005PH (Building

1 PCB AD10200 Eval Board GS03363 Rev. A

A2 142-0701-201 (Johnson Comp.)

IN

B2 142-0701-201 (Johnson Comp.)

IN

Fasteners)

–14–

REV. A

AD10200

GND TIE

GND TIE

Figure 10a. Bottom View

C4

GND TIES

R61

C23

R60

C22

U11

C27

R38

R63

U15

C35

C24

C36

C21

C33

C20

C37

C7

C34

U14

C13 R56

C1
R1

C2

R41

C3

U10

R39

R66

R50
R49
R54

U9

R53

R65

R64

C25

C28

E40

C18

GND TIE

R51

R52

R48

R47

GND TIE

C10

E48

C8

R42

R43

U3

R4

U2

R7

R3

U4

C6

R58

GND TIES

C14

C30

R72

R8

C17

U17

GND TIE

U16

C9

GND TIE

C15

R71

C29

REV. A

Figure 10b. Bottom Assembly

–15–

AD10200

Figure 10c. Ground 1

AGNDA

DGNDBAGNDB

DGNDA

Figure 10d. Ground 2

–16–

REV. A

AD10200

GND TIE

GND TIE

C4

GND TIES

R61

C23

R60

C22

C27

R38

R63

U15

C35

C24

C36

C21

C33

C20

C37

C7

C34

U14

C13 R56

C1
R1

C2

R41

C3

U10

R39

R66

R50

U11

U2

R49
R54

U9

R53

R65

R64

C25

C28

E40

C18

GND TIE

R51

R52

R48

R47

GND TIE

C10

E48

C8

R42

R43

U3

R4

R7

R3

U4

C6

R58

GND TIES

Figure 10e. Bottom Silk

C14

C30

R72

R8

C17

U17

GND TIE

U16

C9

GND TIE

C15

R71

C29

REV. A

Figure 10f. Top View

–17–

AD10200

E11

GND TIE

E11

GND TIE

E5

+5VAB

BJ1
EXTRA

E27

E63

E39

GND TIE

E47

E8

E64

BJ2
EXTRA

E28

E3

AGNDB

L4

ENCB

J10 J11

AINB1

J6

J3

AINA1

L3

E6

REF_B

AINB2

J7

E49

REF_A

J4

AINA2

ENCA

J5

E4

E50

ENCBBAR

U1

ENCABAR

E37

E30

E35

E80

E46

E83

PIN 1

J12

E65

E41

E43

E68

E74

E71

E69

E75

E9 E10

GND TIES

E38

E29

E1E2

E36

E79

E45

E84

E81E82

E66

E42

E44

E67

GND TIES

E73

E72

E70

E76

E33

E26

3.3VDB

R30

R29

R28

R27

R26

R12

R9

R25

R36

R35

R34

ANALOG

DEVICES
COPYRIGHT

2/10 00

AD10200 EVALUATION BOARD

GS03363 (A)

BEL

R18

R17

R16

R40

R44

R45

R46

R15

R14

R13

3.3VDA

E25

J2

R33

R32

R31

E12

GND TIE

E7

J1

C16

DGNDB

L2

U6

C39

E58

E59

E62

E55

E60

R11

R10

E61

BUFLATB

E22

C26

E24

LATCHB

E77

GND TIE

E78

R24

BUFLATA

R23

E19

R22

LATCHA

E23

R21

C5

R20

E57

R19

E52U5E53

E56

E51

E54

C38

L1

DGNDAAGNDA+5VAA

C12

E34

Figure 10g. Top Assembly

E5

+5VAB

BJ1
EXTRA

E27

E8

E28

L4

E63

E39

GND TIE

E47

E64

BJ2
EXTRA

E6

E3

AGNDB

ENCB

J10 J11

AINB1

J6

J3

AINA1

L3

REF_B

AINB2

J7

E49

REF_A

J4

AINA2

ENCA

J5

E4

ENCBBAR

E50

U1

ENCABAR

E37

E30

E35

E80

E46

E83

PIN 1

J12

E65

E9 E10

E41

E43

E68

E74

E71

E69

E75

E38

E29

E36

GND TIES

E79

E45

E84

GND TIES

E33

DGNDB

E1E2

E60

BUFLATB

E22

C26

E24

LATCHB

E19

E23

C5

E81E82

E52

E66

E56

E54

E42

U5

E44

E67

E73

E72

E70

DGNDAAGNDA+5VAA

E76

E34

U6

C39

E59

E61

E77

GND TIE

E78

BUFLATA

LATCHA

E58

E62

E55

R20

E57

R19

E53

E51

C38

E26

C16

L2

R11

R10

R30

R29

R28

R27

AD10200 EVALUATION BOARD

GS03363 (A)

R15

R14

R13

R24

R23

R22

R21

L1

C12

E25

J2

3.3VDB

R26

R12

R9

R25

R36

R35

R34

R33

R32

R31

ANALOG
DEVICES

COPYRIGHT

E12

2/10 00

GND TIE

E7

BEL

R18

R17

J1

R16

R40

R44

R45

R46

3.3VDA

Figure 10h. Top Silk

–18–

REV. A

OUTLINE DIMENSIONS

Dimensions shown in inches and (mm).

68-Lead Ceramic Leaded Chip Carrier

(Z-68B)

AD10200

0.010 (0.25)

0.008 (0.20)

0.007 (0.18)

DETAIL A

TOE DOWN

ANGLE

0–8 DEGREES

0.060 (1.52)

0.050 (1.27)

0.040 (1.02)

1.070

(27.18)

MIN

0.290 (7.37)
MAX

0.230 (5.84)
MAX

0.800

(20.32)

BSC

DETAIL A

10

26

9

0.055 (1.40)

0.050 (1.27)

0.045 (1.14)

0.960 (24.38)

0.950 (24.13) SQ

0.940 (23.88)

PIN 1

TOP VIEW

(PINS DOWN)

0.021 (0.533)

0.017 (0.432)

0.014 (0.357)

61

60

44

4327

1.190 (30.23)

1.180 (29.97) SQ

1.170 (29.72)

Revision History

Location Page

Data Sheet changed from REV. 0 to REV. A.

Edit to ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Edit to Figure 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Edit to ENCODE Inputs section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Edit to Figure 9a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

REV. A

–19–

C01634–0-8/01(A)

–20–

PRINTED IN U.S.A.