Analog ADuM1100 Data Sheet

Page 1

Data Sheet

ADuM1100

iCoupler Digital Isolator

FEATURES

► High data rate: dc to 100 Mbps (NRZ) ► Compatible with 3.3 V and 5.0 V operation/level translation ► 125°C maximum operating temperature ► Low power operation

► 5 V operation

► 1.0 mA maximum @ 1 Mbps ► 4.5 mA maximum @ 25 Mbps ► 16.8 mA maximum @ 100 Mbps

► 3.3 V operation

► 0.4 mA maximum @ 1 Mbps ► 3.5 mA maximum @ 25 Mbps

► 7.1 mA maximum @ 50 Mbps ► 8-lead SOIC_N package (RoHS compliant version available) ► High common-mode transient immunity: >25 kV/μs ► Safety and regulatory approvals

► UL 1577

► V

= 2500 V rms for 1 minute

ISO

► IEC/EN/CSA 62368-1 ► IEC/CSA 61010-1 ► CQC GB 4943.1 ► DIN EN IEC 60747-17 (VDE 0884-17)

► V

= 560 V peak

IORM

APPLICATIONS

► Digital field bus isolation ► Opto-isolator replacement ► Computer peripheral interface ► Microprocessor system interface ► General instrumentation and data acquisition applications

GENERAL DESCRIPTION

The ADuM11001 is a digital isolator based on Analog Devices Inc., iCoupler® technology. Combining high speed CMOS and monolithic air core transformer technology, this isolation component provides outstanding performance characteristics superior to alternatives, such as optocoupler devices.

Configured as a pin-compatible replacement for existing high speed optocouplers, the ADuM1100 supports data rates as high as 25 Mbps and 100 Mbps.

The ADuM1100 operates with a voltage supply ranging from 3.0 V to 5.5 V, boasts a propagation delay of <18 ns and edge asymmetry of <2 ns, and is compatible with temperatures up to 125°C. It operates at very low power, less than 0.9 mA of quiescent current (sum of both sides), and a dynamic current of less than 160 μA per Mbps of data rate. Unlike other optocoupler alternatives, the ADuM1100 provides dc correctness with a patented refresh feature that continuously updates the output signal.

The ADuM1100 is offered in three grades. The ADuM1100AR and ADuM1100BR can operate up to a maximum temperature of 105°C and support data rates up to 25 Mbps and 100 Mbps, respectively. The ADuM1100UR can operate up to a maximum temperature of 125°C and supports data rates up to 100 Mbps.

FUNCTIONAL BLOCK DIAGRAM

Figure 1.

Protected by U.S. Patents 5,952,849; 6,525,566; 6,922,080; 6,903,578; 6,873,065; 7,075,329.

Rev. L

DOCUMENT FEEDBACK

TECHNICAL SUPPORT

Information furnished by Analog Devices is believed to be accurate and reliable "as is". However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

Page 2

Data Sheet ADuM1100

TABLE OF CONTENTS

Features................................................................ 1

Applications........................................................... 1

General Description...............................................1

Functional Block Diagram......................................1

Specifications........................................................ 3

Electrical Specifications—5 V Operation............3

Electrical Specifications—3.3 V Operation.........5

Electrical Specifications—Mixed 5 V/3 V or

3 V/5 V Operation.............................................7

Package Characteristics.....................................9

Regulatory Information.......................................9

Insulation and Safety-Related Specifications.....9

DIN EN IEC 60747-17 (VDE 0884-17)

Insulation Characteristics............................... 10

Recommended Operating Conditions.............. 11

REVISION HISTORY

1/2025—Rev. K to Rev. L

Changes to Features Section.......................................................................................................................... 1

Changes to Regulatory Information Section and Table 5.................................................................................9

Changes to Table 6..........................................................................................................................................9

Changed DIN V VDE V 0884-10 (VDE V 0884-10):2006-12 Insulation Characteristics Section to DIN

EN IEC 60747-17 (VDE 0884-17) Insulation Characteristics Section..........................................................10

Changes to DIN EN IEC 60747-17 (VDE 0884-17) Insulation Characteristics Section, Table 7, and

Figure 2 Caption.......................................................................................................................................... 10

Added Maximum Data Rate (Mbps) and Minimum Pulse Width (ns) Options............................................... 19

Absolute Maximum Ratings.................................12

ESD Caution.....................................................12

Truth Table....................................................... 12

Pin Configuration and Function Descriptions...... 13

Typical Performance Characteristics...................14

Application Information........................................ 16

PC Board Layout..............................................16

Propagation Delay-Related Parameters...........16

Method of Operation, DC Correctness, and

Magnetic Field Immunity................................ 17

Power Consumption.........................................18

Outline Dimensions............................................. 19

Ordering Guide.................................................19

Maximum Data Rate (Mbps) and Minimum

Pulse Width (ns) Options................................19

analog.com Rev. L | 2 of 19

Page 3

Data Sheet ADuM1100

SPECIFICATIONS

ELECTRICAL SPECIFICATIONS—5 V OPERATION

All voltages are relative to their respective ground. 4.5 V ≤ V the entire recommended operation range, unless otherwise noted. All typical specifications are at T

≤ 5.5 V, 4.5 V ≤ V

DD1

≤ 5.5 V. All minimum/maximum specifications apply over

DD2

= 25°C, V

DD1

= V

DD2

= 5 V.

Table 1.

Parameter Symbol Min Typ Max Unit Test Conditions

DC SPECIFICATIONS

Input Supply Current I Output Supply Current I Input Supply Current (25 Mbps) (See Figure 5) I Output Supply Current1 (25 Mbps) (See Figure 6) I Input Supply Current (100 Mbps) (See Figure 5) I

DD1 (Q)

DD2 (Q)

DD1 (25)

DD2 (25)

DD1 (100)

0.3 0.8 mA VI = 0 V or V

0.01 0.06 mA VI = 0 V or V

DD1

2.2 3.5 mA 12.5 MHz logic signal frequency

0.5 1.0 mA 12.5 MHz logic signal frequency

9.0 14 mA 50 MHz logic signal frequency, ADuM1100BR/ ADuM1100UR only

Output Supply Current1 (100 Mbps) (See Figure 6) I

DD2 (100)

2.0 2.8 mA 50 MHz logic signal frequency, ADuM1100BR/ ADuM1100UR only

Input Current I Logic High Output Voltage V

Logic Low Output Voltage V

−10 +0.01 +10 µA 0 V ≤ VIN ≤ V V

− 0.1 5.0 V IO = −20 μA, VI = V

DD2

− 0.8 4.6 V IO = −4 mA, VI = V

DD2

0.0 0.1 V IO = 20 μA, VI = V

0.03 0.1 V IO = 400 μA, VI = V

0.3 0.8 V IO = 4 mA, VI = V

DD1

SWITCHING SPECIFICATIONS

For ADuM1100AR

Minimum Pulse Width Maximum Data Rate

PW 40 ns CL = 15 pF, CMOS signal levels

25 Mbps CL = 15 pF, CMOS signal levels

For ADuM1100BR/ADuM1100UR

Minimum Pulse Width Maximum Data Rate

PW 6.7 10 ns CL = 15 pF, CMOS signal levels

100 150 Mbps CL = 15 pF, CMOS signal levels

For All Grades

Propagation Delay Time to Logic Low Output

4, 5

PHL

10.5 18 ns CL = 15 pF, CMOS signal levels

(See Figure 7) Propagation Delay Time to Logic High Output

4, 5

PLH

10.5 18 ns CL = 15 pF, CMOS signal levels

(See Figure 7) Pulse Width Distortion |t

PLH

Change vs. Temperature Propagation Delay Skew (Equal Temperature) Propagation Delay Skew (Equal Temperature,

5, 7

Supplies) Output Rise/Fall Time tR, t Common-Mode Transient Immunity at Logic

Low/High Output

Refresh Rate f Input Dynamic Supply Current Output Dynamic Supply Current

− t

PHL

PWD 0.5 2 ns CL = 15 pF, CMOS signal levels

3 ps/°C CL = 15 pF, CMOS signal levels

5, 7

PSK1

PSK2

|CML|, | CMH|

DDI (D)

DDO (D)

3 ns CL = 15 pF, CMOS signal levels

25 35 kV/µs VI = 0 V or V

1.2 Mbps

0.09 mA/Mbps

0.02 mA/Mbps

8 ns CL = 15 pF, CMOS signal levels 6 ns CL = 15 pF, CMOS signal levels

, VCM = 1000 V, transient

DD1

magnitude = 800 V

Output supply current values are with no output load present. See Figure 5 and Figure 6 for information on supply current variation with logic signal frequency. See the

Power Consumption section for guidance on calculating the input and output supply currents for a given data rate and output load.

The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed.

The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed.

analog.com Rev. L | 3 of 19

Page 4

Data Sheet ADuM1100

SPECIFICATIONS

is measured from the 50% level of the falling edge of the V

PHL

edge of the VI signal to the 50% level of the rising edge of the V

Because the input thresholds of the ADuM1100 are at voltages other than the 50% level of typical input signals, the measured propagation delay and pulse width distortion can be affected by slow input rise/fall times. See the Propagation Delay-Related Parameters section and Figure 14 through Figure 18 for information on the impact of given input rise/fall times on these parameters.

Pulse width distortion change vs. temperature is the absolute value of the change in pulse width distortion for a 1°C change in operating temperature.

is the magnitude of the worst-case difference in t

PSK1

recommended operating conditions. t

is the magnitude of the worst-case difference in t

PSK2

temperature, supply voltages, and output load within the recommended operating conditions.

CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining V can be sustained while maintaining V

< 0.8 V. The common-mode voltage slew rates apply to both rising and falling edges. The transient magnitude is the range over

which the common mode is slewed.

Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in signal data rate. See Figure 5 and Figure 6 for information on supply current variation with logic signal frequency. See the Power Consumption section for guidance on calculating the input and output supply currents for a given data rate and output load.

signal to the 50% level of the falling edge of the V

signal.

and/or t

PHL

that is measured between units at the same operating temperature and output load within the

PLH

and/or t

PHL

that is measured between units at the same operating

PLH

> 0.8 V

DD2

signal. t

is measured from the 50% level of the rising

PLH

. CML is the maximum common-mode voltage slew rate that

analog.com Rev. L | 4 of 19

Page 5

Data Sheet ADuM1100

SPECIFICATIONS

ELECTRICAL SPECIFICATIONS—3.3 V OPERATION

All voltages are relative to their respective ground. 3.0 V ≤ V the entire recommended operation range, unless otherwise noted. All typical specifications are at T

≤ 3.6 V, 3.0 V ≤ V

DD1

≤ 3.6 V. All minimum/maximum specifications apply over

DD2

= 25°C, V

DD1

= V

DD2

= 3.3 V.

Table 2.

Parameter Symbol Min Typ Max Unit Test Conditions

DC SPECIFICATIONS

Input Supply Current I Output Supply Current I Input Supply Current (25 Mbps) (See Figure 5) I Output Supply Current1 (25 Mbps) (See Figure 6) I Input Supply Current (50 Mbps) (See Figure 5) I

DD1 (Q)

DD2 (Q)

DD1 (25)

DD2 (25)

DD1 (50)

0.1 0.3 mA VI = 0 V or V

0.005 0.04 mA VI = 0 V or V

DD1

2.0 2.8 mA 12.5 MHz logic signal frequency

0.3 0.7 mA 12.5 MHz logic signal frequency

4.0 6.0 mA 25 MHz logic signal frequency, ADuM1100BR/ ADuM1100UR only

Output Supply Current1 (50 Mbps) (See Figure 6) I

DD2 (50)

1.2 1.6 mA 25 MHz logic signal frequency, ADuM1100BR/ ADuM1100UR only

Input Current I Logic High Output Voltage V

Logic Low Output Voltage V

−10 +0.01 +10 µA 0 V ≤ VIN ≤ V V

− 0.1 3.3 V IO = −20 μA, VI = V

DD2

− 0.5 3.0 V IO = −2.5 mA, VI = V

DD2

0.0 0.1 V IO = 20 μA, VI = V

0.04 0.1 V IO = 400 μA, VI = V

0.3 0.4 V IO = 2.5 mA, VI = V

DD1

SWITCHING SPECIFICATIONS

For ADuM1100AR

Minimum Pulse Width Maximum Data Rate

PW 40 ns CL = 15 pF, CMOS signal levels

25 Mbps CL = 15 pF, CMOS signal levels

For ADuM1100BR/ADuM1100UR

Minimum Pulse Width Maximum Data Rate

PW 10 20 ns CL = 15 pF, CMOS signal levels

50 100 Mbps CL = 15 pF, CMOS signal levels

For All Grades

Propagation Delay Time to Logic Low Output

4, 5

PHL

14.5 28 ns CL = 15 pF, CMOS signal levels

(See Figure 8) Propagation Delay Time to Logic High Output

4, 5

PLH

15.0 28 ns CL = 15 pF, CMOS signal levels

(See Figure 8) Pulse Width Distortion |t

PLH

Change vs. Temperature Propagation Delay Skew (Equal Temperature) Propagation Delay Skew (Equal Temperature,

5, 7

Supplies) Output Rise/Fall Time tR, t Common-Mode Transient Immunity at Logic

Low/High Output

Refresh Rate f Input Dynamic Supply Current Output Dynamic Supply Current

− t

PHL

PWD 0.5 3 ns CL = 15 pF, CMOS signal levels

10 ps/°C CL = 15 pF, CMOS signal levels

5, 7

PSK1

PSK2

|CML|, | CMH|

DDI (D)

DDO (D)

3 ns CL = 15 pF, CMOS signal levels

25 35 kV/µs VI = 0 V or V

1.1 Mbps

0.08 mA/Mbps

0.04 mA/Mbps

15 ns CL = 15 pF, CMOS signal levels 12 ns CL = 15 pF, CMOS signal levels

, VCM = 1000 V, transient

DD1

magnitude = 800 V

Output supply current values are with no output load present. See Figure 5 and Figure 6 for information on supply current variation with logic signal frequency. See the

Power Consumption section for guidance on calculating the input and output supply currents for a given data rate and output load.

The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed.

The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed.

analog.com Rev. L | 5 of 19

Page 6

Data Sheet ADuM1100

SPECIFICATIONS

is measured from the 50% level of the falling edge of the V

PHL

edge of the VI signal to the 50% level of the rising edge of the V

Pulse width distortion change vs. temperature is the absolute value of the change in pulse width distortion for a 1°C change in operating temperature.

is the magnitude of the worst-case difference in t

PSK1

recommended operating conditions. t

is the magnitude of the worst-case difference in t

PSK2

temperature, supply voltages, and output load within the recommended operating conditions.

CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining V can be sustained while maintaining V

< 0.8 V. The common-mode voltage slew rates apply to both rising and falling edges. The transient magnitude is the range over

which the common mode is slewed.

signal to the 50% level of the falling edge of the V

signal.

and/or t

PHL

that is measured between units at the same operating temperature and output load within the

PLH

and/or t

PHL

that is measured between units at the same operating

PLH

> 0.8 V

DD2

signal. t

is measured from the 50% level of the rising

PLH

. CML is the maximum common-mode voltage slew rate that

analog.com Rev. L | 6 of 19

Page 7

Data Sheet ADuM1100

SPECIFICATIONS

ELECTRICAL SPECIFICATIONS—MIXED 5 V/3 V OR 3 V/5 V OPERATION

All voltages are relative to their respective ground. 5 V/3 V operation: 4.5 V ≤ V V

≤ 3.6 V, 4.5 V ≤ V

DD1

noted. All typical specifications are at T

≤ 5.5 V. All minimum/maximum specifications apply over the entire recommended operation range, unless otherwise

DD2

= 25°C, V

= 3.3 V, V

DD1

= 5 V or V

DD2

≤ 5.5 V, 3.0 V ≤ V

DD1

= 5 V, V

DD1

DD2

= 3.3 V.

≤ 3.6 V. 3 V/5 V operation: 3.0 V ≤

DD2

Table 3.

Parameter Symbol Min Typ Max Unit Test Conditions

DC SPECIFICATIONS

Input Supply Current, Quiescent I

DDI (Q)

5 V/3 V Operation 0.3 0.8 mA 3 V/5 V Operation 0.1 0.3 mA

Output Supply Current, Quiescent I

DDO (Q)

5 V/3 V Operation 0.005 0.04 mA 3 V/5 V Operation 0.01 0.06 mA

Input Supply Current, 25 Mbps I

DDI (25)

5 V/3 V Operation 2.2 3.5 mA 12.5 MHz logic signal frequency 3 V/5 V Operation 2.0 2.8 mA 12.5 MHz logic signal frequency

Output Supply Current1, 25 Mbps I

DDO (25)

5 V/3 V Operation 0.3 0.7 mA 12.5 MHz logic signal frequency 3 V/5 V Operation 0.5 1.0 mA 12.5 MHz logic signal frequency

Input Supply Current, 50 Mbps I

DDI (50)

5 V/3 V Operation 4.5 7.0 mA 25 MHz logic signal frequency 3 V/5 V Operation 4.0 6.0 mA 25 MHz logic signal frequency

Output Supply Current1, 50 Mbps I

DDO (50)

5 V/3 V Operation 1.2 1.6 mA 25 MHz logic signal frequency

3 V/5 V Operation 1.0 1.5 mA 25 MHz logic signal frequency Input Currents I Logic High Output Voltage V

5 V/3 V Operation V Logic Low Output Voltage V

5 V/3 V Operation 0.04 0.1 V IO = 400 μA, VI = V

Logic High Output Voltage V

3 V/5 V Operation V Logic Low Output Voltage V

3 V/5 V Operation 0.03 0.1 V IO = 400 μA, VI = V

−10 +0.01 +10 μA 0 V ≤ VIA, VIB, VIC, VID ≤ V V

− 0.1 3.3 V IO = −20 μA, VI = V

DD2

− 0.5 3.0 V IO = −2.5 mA, VI = V

DD2

0.0 0.1 V IO = 20 μA, VI = V

0.3 0.4 V IO = 2.5 mA, VI = V

− 0.1 5.0 V IO = −20 μA, VI = V

DD2

− 0.8 4.6 V IO = −4 mA, VI = V

DD2

0.0 0.1 V IO = 20 μA, VI = V

0.3 0.8 V IO = 4 mA, VI = V

DD1

SWITCHING SPECIFICATIONS

For ADuM1100AR

Minimum Pulse Width

Maximum Data Rate

PW 40 ns CL = 15 pF, CMOS signal levels

25 Mbps CL = 15 pF, CMOS signal levels

For ADuM1100BR/ADuM1100UR

Minimum Pulse Width

Maximum Data Rate

PW 20 ns CL = 15 pF, CMOS signal levels

50 Mbps CL = 15 pF, CMOS signal levels

For All Grades

Propagation Delay Time to Logic Low/High

4, 5

Output

PHL

, t

PLH

5 V/3 V Operation (See Figure 9) 13 21 ns CL = 15 pF, CMOS signal levels 3 V/5 V Operation (See Figure 10) 16 26 ns CL = 15 pF, CMOS signal levels

or V

DD2

analog.com Rev. L | 7 of 19

Page 8

Data Sheet ADuM1100

SPECIFICATIONS

Table 3. (Continued)

Parameter Symbol Min Typ Max Unit Test Conditions

Pulse Width Distortion, |t

PLH

5 V/3 V Operation 0.5 2 ns CL = 15 pF, CMOS signal levels 3 V/5 V Operation 0.5 3 ns CL = 15 pF, CMOS signal levels Change in Pulse Width Distortion vs.

Temperature

5 V/3 V Operation 3 ps/°C CL = 15 pF, CMOS signal levels 3 V/5 V Operation 10 ps/°C CL = 15 pF, CMOS signal levels

Propagation Delay Skew (Equal Temperature)

5 V/3 V Operation 12 ns CL = 15 pF, CMOS signal levels 3 V/5 V Operation 15 ns CL = 15 pF, CMOS signal levels

Propagation Delay Skew (Equal Temperature,

5, 7

Supplies)

5 V/3 V Operation 9 ns CL = 15 pF, CMOS signal levels

3 V/5 V Operation 12 ns CL = 15 pF, CMOS signal levels Output Rise/Fall Time (10% to 90%) tR, t Common-Mode Transient Immunity at Logic Low/

High Output

Refresh Rate f

5 V/3 V Operation 1.2 Mbps 3 V/5 V Operation 1.1 Mbps

Input Dynamic Supply Current

5 V/3 V Operation 0.09 mA/Mbps 3 V/5 V Operation 0.08 mA/Mbps

Output Dynamic Supply Current9C

5 V/3 V Operation 0.04 mA/Mbps 3 V/5 V Operation 0.02 mA/Mbps

− t

PHL

PWD

5, 7

PSK1

PSK2

3 ns CL = 15 pF, CMOS signal levels

|CML|,|CMH| 25 35 kV/µs VI = 0 V or V

, VCM = 1000 V,transient

DD1

magnitude = 800 V

PD1

PD2

Output supply current values are with no output load present. See Figure 5 and Figure 6 for information on supply current variation with logic signal frequency. See the

Power Consumption section for guidance on calculating the input and output supply currents for a given data rate and output load.

The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed.

The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed.

is measured from the 50% level of the falling edge of the V

PHL

edge of the VI signal to the 50% level of the rising edge of the V

Because the input thresholds of the ADuM1100 are at voltages other than the 50% level of typical input signals, the measured propagation delay and pulse width distortion

signal to the 50% level of the falling edge of the V

signal.

signal. t

PLH

is measured from the 50% level of the rising

can be affected by slow input rise/fall times. See the Propagation Delay-Related Parameters section and Figure 14 through Figure 18 for information on the impact of given input rise/fall times on these parameters.

Pulse width distortion change vs. temperature is the absolute value of the change in pulse width distortion for a 1°C change in operating temperature.

is the magnitude of the worst-case difference in t

PSK1

the recommended operating conditions. t

is the magnitude of the worst-case difference in t

PSK2

and/or t

PHL

that is measured between units at the same operating temperature and output load within

PLH

and/or t

PHL

that is measured between units at the same operating

PLH

temperature, supply voltages, and output load within the recommended operating conditions.

CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining V can be sustained while maintaining V

< 0.8 V. The common-mode voltage slew rates apply to both rising and falling edges. The transient magnitude is the range over

> 0.8 V

. CML is the maximum common-mode voltage slew rate that

DD2

which the common mode is slewed.

analog.com Rev. L | 8 of 19

Page 9

Data Sheet ADuM1100

SPECIFICATIONS

PACKAGE CHARACTERISTICS

Table 4.

Parameter Symbol Min Typ Max Unit Test Conditions

Resistance (Input-to-Output)

Capacitance (Input-to-Output) Input Capacitance

IC Junction-to-Case Thermal Resistance, Side 1 θ IC Junction-to-Case Thermal Resistance, Side 2 θ Package Power Dissipation P

The device is considered a 2-terminal device; Pin 1, Pin 2, Pin 3, and Pin 4 are shorted together, and Pin 5, Pin 6, Pin 7, and Pin 8 are shorted together.

Input capacitance is measured at Pin 2 (VI).

C C

I-O

JCI

JCO

REGULATORY INFORMATION

The ADuM1100 certification approvals are listed in Table 5.

Table 5.

UL CSA CQC VDE

UL 1577

Single Protection, 2500 V rms Basic insulation, 400 V rms Basic insulation, 400 V rms Reinforced insulation, 560 V peak

File E214100 File No. 205078 Certificate No. CQC14001117247 Certificate No. 40011599

IEC/EN/CSA 62368-1 CQC GB4943.1 DIN EN IEC 60747-17 (VDE 0884-17)

Reinforced insulation, 150 V rms Reinforced insulation, 150 V rms

IEC/CSA 61010-1

Basic insulation, 300 V rms Reinforced insulation, 150 V rms

Ω

1.0 pF f = 1 MHz

4.0 pF 46 °C/W Thermocouple located at center of package underside 41 °C/W

240 mW

In accordance with UL 1577, each ADuM1100 is proof tested by applying an insulation test voltage ≥3000 V rms for 1 sec (current leakage detection limit = 5 µA).

In accordance with DIN EN IEC 60747-17 (VDE 0884-17), each ADuM1100 is proof tested by applying an insulation test voltage ≥1050 V peak for 1 sec (partial discharge detection limit = 5 pC).

INSULATION AND SAFETY-RELATED SPECIFICATIONS

Table 6.

Parameter Symbol Value Unit Conditions

Rated Dielectric Insulation Voltage 2500 V rms 1-minute duration Minimum External Air Gap (Clearance) L(I01) 4

Minimum External Tracking (Creepage) L(I02) 4 mm Measured from input terminals to output terminals, shortest

Minimum Internal Gap (Internal Clearance) 18 μm Insulation distance through insulation Tracking Resistance (Comparative Tracking Index) CTI >400 V DIN IEC 112/VDE 0303 Part 1 Material Group II Material Group per IEC 60664-1

In accordance with IEC 62368-1/IEC 60601-1 guidelines for the measurement of creepage and clearance distances for a pollution degree of 2 and altitudes ≤2000 meters.

Consideration must be given to pad layout to ensure the minimum required distance for clearance is maintained.

1, 2

mm Measured from input terminals to output terminals, shortest

distance through air

distance path along body

analog.com Rev. L | 9 of 19

Page 10

Data Sheet ADuM1100

SPECIFICATIONS

DIN EN IEC 60747-17 (VDE 0884-17) INSULATION CHARACTERISTICS

This isolator is suitable for reinforced isolation only within the safety limit data. Maintenance of the safety data is ensured by means of protective circuits. The asterisk (*) marking on the package denotes DIN EN IEC 60747-17 (VDE 0884-17) approval.

Table 7.

Description Conditions Symbol Characteristic Unit

Overvoltage Category per IEC 60664-1

≤ 150 V rms I to IV ≤ 300 V rms I to III

≤ 400 V rms I to II Climatic Classification 40/105/21 Pollution Degree per DIN VDE 0110, Table 1 2 Maximum Repetitive Isolation Voltage V Maximum Working Insulation Voltage V Input-to-Output Test Voltage, Method B1 V

× 1.875 = V

IORM

, 100% production test, tm = 1

pd(m)

IORM

IOWM

pd(m)

sec, partial discharge < 5 pC

Input-to-Output Test Voltage, Method A

After Environmental Tests Subgroup 1 V

× 1.6 = V

IORM

, tm = 60 sec, partial discharge <

pd(m)

5 pC

After Input and/or Safety Test Subgroup 2 and Subgroup 3 V

× 1.2 = V

IORM

, tm = 60 sec, partial discharge <

pd(m)

5 pC Maximum Transient Isolation Voltage V Maximum Impulse Voltage Surge voltage in air, waveform per IEC 61000-4-5 V Maximum Surge Isolation Voltage V

= 1.2 × V

TEST

≥ 1.3 × V

TEST

, t =1s (100% production) V

IOTM

(sample test), tested in oil,

IMP

IOTM

IMP

IOSM

waveform per IEC 61000-4-5 Safety-Limiting Values Maximum value allowed in the event of a failure (see

Figure 2)

Case Temperature T Side 1 Current I Side 2 Current I

Insulation Resistance at T

VIO = 500 V R

560 V peak 396 V rms 1050 V peak

896 V peak

672 V peak

4000 V peak 4000 V peak 10000 V

peak

150 °C 160 mA 170 mA

>10

Ω

Figure 2. Thermal Derating Curve, Dependence of Safety-Limiting Values with Case Temperature per DIN EN IEC 60747-17 (VDE 0884-17)

analog.com Rev. L | 10 of 19

Page 11

Data Sheet ADuM1100

SPECIFICATIONS

RECOMMENDED OPERATING CONDITIONS

Table 8.

Parameter Symbol Min Max Unit

Operating Temperature

ADuM1100AR/ADuM1100BR T ADuM1100UR T

Supply Voltages

Logic High Input Voltage, 5 V Operation Logic Low Input Voltage, 5 V Operation Logic High Input Voltage, 3.3 V Operation Logic Low Input Voltage, 3.3 V Operation

1, 2

(See Figure 11 and Figure 12) V

1, 2

(See Figure 11 and Figure 12) V

1, 2

(See Figure 11 and Figure 12) V

1, 2

(See Figure 11 and Figure 12) V

DD1,VDD2

Input Signal Rise and Fall Times 1.0 ms

All voltages are relative to their respective ground.

Input switching thresholds have 300 mV of hysteresis. See the Method of Operation, DC Correctness, and Magnetic Field Immunity section, Figure 19, and Figure 20 for information on immunity to external magnetic fields.

−40 +105 °C

−40 +125 °C

3.0 5.5 V

2.0 V

DD1

0.0 0.8 V

1.5 V

DD1

0.0 0.5 V

analog.com Rev. L | 11 of 19

Page 12

Data Sheet ADuM1100

ABSOLUTE MAXIMUM RATINGS

Table 9.

Parameter Symbol Min Max Unit

Storage Temperature T Ambient Operating Temperature T Supply Voltages Input Voltage Output Voltage Average Current, per Pin

V V V

DD1

−55 +150 °C

−40 +125 °C

, V

−0.5 +6.5 V

DD2

−0.5 V

+ 0.5 V

DD1

+ 0.5 V

DD2

Temperature ≤ 105°C −25 +25 mA Temperature ≤ 125°C

Refers to common-mode transients across the insulation barrier. Commonmode transients exceeding the Absolute Maximum Rating may cause latch-up or permanent damage.

Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability.

ESD CAUTION

Input Current −7 +7 mA Output Current −20 +20 mA

Common-Mode Transients

All voltages are relative to their respective ground.

See Figure 2 for information on maximum allowable current for various temper-

−100 +100 kV/µs

atures.

ESD (electrostatic discharge) sensitive device. Charged devices and circuit boards can discharge without detection. Although

this product features patented or proprietary protection circuitry,

damage may occur on devices subjected to high energy ESD.

Therefore, proper ESD precautions should be taken to avoid

performance degradation or loss of functionality.

TRUTH TABLE

Table 10. Truth Table (Positive Logic)

VI Input V

H Powered Powered H L Powered Powered L X Unpowered Powered H X Powered Unpowered X

VO returns to VI state within 1 μs of power restoration.

State V

DD1

State VO Output

DD2

Figure 3 shows the package branding. The asterisk (*) is the DIN EN 60747-5-2 mark, R is the package designator (R denotes SOIC_N),

YYWW is the date code, and XXXXXX is the lot code.

Figure 3. Package Branding

analog.com Rev. L | 12 of 19

Page 13

Data Sheet ADuM1100

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

Figure 4. Pin Configuration

Table 11. Pin Function Descriptions

Pin No. Mnemonic Description

1 V 2 V 3 V

DD1

4 GND 5 GND 6 V

7 GND 8 V

DD2

Input Supply Voltage, 3.0 V to 5.5 V. Logic Input. Input Supply Voltage, 3.0 V to 5.5 V. Input Ground Reference. Output Ground Reference. Logic Output. Output Ground Reference. Output Supply Voltage, 3.0 V to 5.5 V.

analog.com Rev. L | 13 of 19

Page 14

Data Sheet ADuM1100

TYPICAL PERFORMANCE CHARACTERISTICS

Figure 5. Typical Input Supply Current vs. Logic Signal Frequency for 5 V

and 3.3 V Operation

Figure 6. Typical Output Supply Current vs. Logic Signal Frequency for 5 V

and 3.3 V Operation

Figure 8. Typical Propagation Delays vs. Temperature, 3.3 V Operation

Figure 9. Typical Propagation Delays vs. Temperature, 5 V/3 V Operation

Figure 10. Typical Propagation Delays vs. Temperature, 3 V/5 V Operation

Figure 7. Typical Propagation Delays vs. Temperature, 5 V Operation

analog.com Rev. L | 14 of 19

Page 15

Data Sheet ADuM1100

TYPICAL PERFORMANCE CHARACTERISTICS

Figure 11. Typical Input Voltage Switching Threshold, Low-to-High Transition Figure 12. Typical Input Voltage Switching Threshold, High-to-Low Transition

analog.com Rev. L | 15 of 19

Page 16

Data Sheet ADuM1100

APPLICATION INFORMATION

PC BOARD LAYOUT

The ADuM1100 digital isolator requires no external interface circuitry for the logic interfaces. A bypass capacitor is recommended at the input and output supply pins. The input bypass capacitor can conveniently be connected between Pin 3 and Pin 4 (see Figure

13). Alternatively, the bypass capacitor can be located between

Pin 1 and Pin 4. The output bypass capacitor can be connected between Pin 7 and Pin 8 or Pin 5 and Pin 8. The capacitor value should be between 0.01 µF and 0.1 µF. The total lead length between both ends of the capacitor and the power supply pins should not exceed 20 mm.

Pulse width distortion is the maximum difference between t t

and provides an indication of how accurately the input signal’s

PHL

timing is preserved in the component’s output signal. Propagation delay skew is the difference between the minimum and maximum propagation delay values among multiple ADuM1100 components operated at the same operating temperature and having the same output load.

Depending on the input signal rise/fall time, the measured propagation delay based on the input 50% level can vary from the true propagation delay of the component (as measured from its input switching threshold). This is because the input threshold, as is the case with commonly used optocouplers, is at a different voltage level than the 50% point of typical input signals. This propagation delay difference is given by

∆LH = t′

Figure 13. Recommended Printed Circuit Board Layout

See the AN-1109 Application Note for board layout guidelines.

PROPAGATION DELAY-RELATED PARAMETERS

Propagation delay time describes the length of time it takes for a logic signal to propagate through a component. Propagation delay time to logic low output and propagation delay time to logic high output refer to the duration between an input signal transition and

PLH

∆HL = t′

PHL

where:

and t

PLH

PHL

input 50% level.

t’

and t’

PLH

input switching thresholds.

tR and tF are the input 10% to 90% rise/fall times. VI is the amplitude of the input signal (0 V to V V

and V

ITH (L–H)

the respective output signal transition (see Figure 14).

and

PLH

− t

= (tR/0.8 VI)(0.5 VI − V

PLH

− t

= (tF/0.8 VI)(0.5 VI − V

PHL

ITH (L-H)

)

ITH (H-L)

)

(1)

(2)

are the propagation delays as measured from the

PHL

levels assumed).

are the input switching thresholds.

ITH (H–L)

Figure 14. Propagation Delay Parameters

Figure 15. Impact of Input Rise/Fall Time on Propagation Delay

analog.com Rev. L | 16 of 19

Page 17

Data Sheet ADuM1100

APPLICATION INFORMATION

Figure 16. Typical Propagation Delay Change Due to Input Rise Time

Variation (for V

= 3.3 V and 5 V)

DD1

Figure 18. Typical Pulse Width Distortion Adjustment Due to Input Rise/Fall

METHOD OF OPERATION, DC CORRECTNESS, AND MAGNETIC FIELD IMMUNITY

The two coils in Figure 1 act as a pulse transformer. Positive and negative logic transitions at the isolator input cause narrow (2 ns) pulses to be sent via the transformer to the decoder. The decoder is bistable and therefore either set or reset by the pulses indicating input logic transitions. In the absence of logic transitions at the input for more than ~1 μs, a periodic update pulse of the appropriate polarity is sent to ensure dc correctness at the output. If the decoder receives none of these update pulses for more than about 5 μs, the input side is assumed to be unpowered or nonfunctional, in which case the isolator output is forced to a logic high state by the watchdog timer circuit.

Figure 17. Typical Propagation Delay Change Due to Input Fall Time Variation

(for V

= 3.3 V and 5 V)

DD1

The limitation on the magnetic field immunity of the ADuM1100 is set by the condition in which induced voltage in the transformer’s

receiving coil is sufficiently large to either falsely set or reset the deThe impact of the slower input edge rates can also affect the measured pulse width distortion as based on the input 50% level. This impact can either increase or decrease the apparent pulse width distortion depending on the relative magnitudes of t

PHL

, t

PLH

, and PWD. The case of interest here is the condition that leads to the largest increase in pulse width distortion. The change in this case is given by

∆

= PWD′ − PWD = ∆LH − ∆HL = (t/0.8 VI)(V − V

PWD

), (for t = tR = tF)

ITH (H-L)

ITH (L-H)

−

(3)

where:

PWD = |t PWD’ = |t’

PLH

− t

− t’

PHL

This adjustment in pulse width distortion is plotted as a function of input rise/fall time in Figure 18.

coder. The analysis that follows defines the conditions under which this can occur. The 3.3 V operating condition of the ADuM1100 is examined because it represents the most susceptible mode of operation.

The pulses at the transformer output are greater than 1.0 V in amplitude. The decoder has sensing thresholds at about 0.5 V, therefore establishing a 0.5 V margin in which induced voltages can be tolerated. The voltage induced across the receiving coil is given by

V = (−dβ/dt) ∑π r

where:

β is the magnetic flux density (gauss). N is the number of turns in the receiving coil. rn is the radius of the nth turn in the receiving coil (cm).

Time Variation (for V

, n = 1, 2, . . . , N

DD1

= 3.3 V and 5 V)

(4)

Given the geometry of the receiving coil in the ADuM1100 and an imposed requirement that the induced voltage be at most 50% of

analog.com Rev. L | 17 of 19

Page 18

Data Sheet ADuM1100

APPLICATION INFORMATION

the 0.5 V margin at the decoder, a maximum allowable magnetic field is calculated, as shown in Figure 19.

Note that at combinations of strong magnetic field and high frequency, any loops formed by printed circuit board traces could induce sufficiently large error voltages to trigger the thresholds of succeeding circuitry. Care should be taken in the layout of such traces to avoid this possibility.

POWER CONSUMPTION

The supply current of the ADuM1100 isolator is a function of the supply voltage, the input data rate, and the output load.

The input supply current is given by

= I

DDI

DDI (Q)

= I

DDI

DDI (D)

The output supply current is given by

= I

DDO

Figure 19. Maximum Allowable External Magnetic Field

For example, at a magnetic field frequency of 1 MHz, the maximum allowable magnetic field of 0.2 kgauss induces a voltage of 0.25 V at the receiving coil. This is about 50% of the sensing threshold and does not cause a faulty output transition. Similarly, if such an event were to occur during a transmitted pulse (and was of the worst-case polarity), it would reduce the received pulse from >1.0 V to 0.75 V, still well above the 0.5 V sensing threshold of the decoder.

The preceding magnetic flux density values correspond to specific current magnitudes at given distances away from the ADuM1100 transformers. Figure 20 expresses these allowable current magnitudes as a function of frequency for selected distances. As can be seen, the ADuM1100 is extremely immune and can be affected only

DDO (Q)

= (I

DDO

DDO (D)

f > 0.5f

where:

, I

DDI (D)

DDO (D)

per channel (mA/Mbps).

CL is the output load capacitance (pF). V

is the output supply voltage (V).

DDO

f is the input logic signal frequency (MHz, half the input data rate,

NRZ signaling).

fr is the input stage refresh rate (Mbps). I

, I

DDI (Q)

DDO (Q)

currents (mA).

by extremely large currents operated at high frequency and very close to the component. For the 1 MHz example noted, one would have to place a current of 0.5 kA 5 mm away from the ADuM1100 to affect the component’s operation.

f ≤ 0.5f

× (2f − fr) + I

f > 0.5f

DDI (Q)

f ≤ 0.5f

+ (0.5 × 10−3) × CLV

) × (2f − fr) + I

DDO

DDO (Q)

(5)

(6)

(7)

(8)

are the input and output dynamic supply currents

are the specified input and output quiescent supply

Figure 20. Maximum Allowable Current for Various Current-to-ADuM1100

Spacings

analog.com Rev. L | 18 of 19

Page 19

Data Sheet ADuM1100

OUTLINE DIMENSIONS

Package Drawing (Option) Package Type Package Description

R-8 SOIC_N 8-Lead Standard Small Outline Package, Narrow Body

For the latest package outline information and land patterns (footprints), go to Package Index.

ORDERING GUIDE

Model

ADuM1100AR −40°C to +105°C 8-Lead SOIC_N Tube, 98 R-8 ADuM1100AR-RL7 −40°C to +105°C 8-Lead SOIC_N Reel, 1000 R-8 ADuM1100ARZ −40°C to +105°C 8-Lead SOIC_N Tube, 98 R-8 ADuM1100ARZ-RL7 −40°C to +105°C 8-Lead SOIC_N Reel, 1000 R-8 ADuM1100BR −40°C to +105°C 8-Lead SOIC_N Tube, 98 R-8 ADuM1100BR-RL7 −40°C to +105°C 8-Lead SOIC_N Reel, 1000 R-8 ADuM1100BRZ −40°C to +105°C 8-Lead SOIC_N Tube, 98 R-8 ADuM1100BRZ-RL7 −40°C to +105°C 8-Lead SOIC_N Reel, 1000 R-8 ADuM1100UR −40°C to +125°C 8-Lead SOIC_N Tube, 98 R-8 ADuM1100UR-RL7 −40°C to +125°C 8-Lead SOIC_N Reel, 1000 R-8 ADuM1100URZ −40°C to +125°C 8-Lead SOIC_N Tube, 98 R-8 ADuM1100URZ-RL7 −40°C to +125°C 8-Lead SOIC_N Reel, 1000 R-8

Temperature Range Package Description Packing Quantity Package Option

Z = RoHS Compliant Part.

MAXIMUM DATA RATE (MBPS) AND MINIMUM PULSE WIDTH (NS) OPTIONS

Model

ADuM1100AR 25 40 ADuM1100AR-RL7 25 40 ADuM1100ARZ 25 40 ADuM1100ARZ-RL7 25 40 ADuM1100BR 100 10 ADuM1100BR-RL7 100 10 ADuM1100BRZ 100 10 ADuM1100BRZ-RL7 100 10 ADuM1100UR 100 10 ADuM1100UR-RL7 100 10 ADuM1100URZ 100 10 ADuM1100URZ-RL7 100 10

Z = RoHS Compliant Part.

Maximum Data Rate (Mbps) Minimum Pulse Width (ns)

Rev. L | 19 of 19