AMN12100
TM
WHDI
Receiver
Module Datasheet
Version 1.0
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AMIMON Confidential
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AMIMON Confidential ii
Important Notice
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Table of Contents
Table of Contents
Chapter 1, Introduction ................................................................................... 1
1.1 Features......................................................................................................................................................... 1
Chapter 2, Overview........................................................................................ 3
2.1 AMN2210 WHDI Baseband Receiver .......................................................................................................... 4
2.2 LPC2103 Mini-MAC µController .................................................................................................................. 4
2.3 MAX2828 5GHz (802.11a) Transceiver........................................................................................................ 5
2.4 Power Amplifier (PA).................................................................................................................................... 5
2.5 Board Connector (WHDITM Connector)....................................................................................................... 5
2.6 E2PROM......................................................................................................................................................... 5
2.7 40MHz Clock Gen.......................................................................................................................................... 5
Chapter 3, Interfaces ...................................................................................... 7
3.1 Video Data Input and Conversions............................................................................................................. 7
3.1.1 Video Interface Output Timing Diagram....................................................................................................... 8
3.2 Audio Data Capture ...................................................................................................................................... 9
3.2.1 I2S Bus Specification .................................................................................................................................. 10
3.3 Management Buses and Connectors ....................................................................................................... 12
3.3.1 Two-Wire Serial Bus Interface.................................................................................................................... 12
3.3.2 Interrupts .................................................................................................................................................... 13
3.4 Reset and Wake-up Timer.......................................................................................................................... 14
Chapter 4, WHDI Connector Pin-Outs............................................................ 15
4.1 Signals ......................................................................................................................................................... 15
4.2 Connector Schematics............................................................................................................................... 16
4.3 Pin List......................................................................................................................................................... 17
Chapter 5, Electrical Specifications ............................................................. 19
5.1 Operating Conditions and Electrical Characteristics ............................................................................. 19
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Table of Contents
Chapter 6, Design Guidelines........................................................................ 21
6.1 Digital Layout Recommendation............................................................................................................... 21
6.1.1 Stuck Up ..................................................................................................................................................... 21
6.1.2 General Guidelines..................................................................................................................................... 22
6.1.3 WHDI Lines ................................................................................................................................................22
6.1.4 Power and Ground ..................................................................................................................................... 22
6.2 RF Design Recommendation..................................................................................................................... 23
6.2.1 RF Components ......................................................................................................................................... 23
6.2.2 Power Management ................................................................................................................................... 23
6.2.3 Device Application Notes ........................................................................................................................... 23
6.2.4 Antennas ....................................................................................................................................................23
Chapter 7, Mechanical Dimensions............................................................... 25
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List of Figures
List of Figures
Figure 1: AMN12100 Block Diagram......................................................................................................................... 3
Figure 2: WHDI Baseband Receiver Chipset............................................................................................................ 4
Figure 3: Video Data Receiver Path.......................................................................................................................... 7
Figure 4: Timing Diagram.......................................................................................................................................... 9
Figure 5: I2S Simple System Configurations and Basic Interface Timing ............................................................... 10
Figure 6: I2S Output Timings ................................................................................................................................... 11
Figure 7: Two-Wire / Application-MiniMAC connection........................................................................................... 12
Figure 8: Two-Wire MiniMAC Write Commands ..................................................................................................... 12
Figure 9: Two-Wire Read Command....................................................................................................................... 13
Figure 10: Reset Mechanism ..................................................................................................................................14
Figure 11: WHDI Connector .................................................................................................................................... 16
Figure 12: Receiver RF Power Scheme.................................................................................................................. 23
Figure 13: Mechanical Dimensions ......................................................................................................................... 25
List of Tables
Table 1: Common Supported Video Input Resolutions............................................................................................. 8
Table 2: Video Channel Mapping.............................................................................................................................. 8
Table 3: Video Interface ............................................................................................................................................ 8
Table 4: Audio Interface Ouput Timing.................................................................................................................... 11
Table 5: Device Addresses ..................................................................................................................................... 12
Table 6: WHDI Connector Signals .......................................................................................................................... 15
Table 7: Rx WHDI Connector Pin List..................................................................................................................... 17
Table 8: Absolute Maximum Ratings over Operating Case Temperature Range................................................... 19
Table 9: Recommended Operating Conditions ....................................................................................................... 19
Table 10: Electrical Characteristics over Recommended Range of Supply Voltage and Operating
Conditions........................................................................................................................................... 19
Table 11: Digital Layout Recommendation ............................................................................................................. 21
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Revision History
Version Date Description
0.1 - Initial Release
0.5 19-Jun-07 Added Design Guidelines
Updated Reset Mechanism
Updated Two-Wire Serial Bus Protocol Definition
0.6 19-June-07 Added Mechanical Dimensions
1.0 06-Nov-07 Added FCC certification and compliance
Added Table 2
Updated Table 4
Revision History
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Revision History
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Introduction
Chapter 1
Introduction
The AMN12100 is the first generation of WHDITM receiver module based on AMIMON's AMN2210 baseband
receiver chip. The AMN12100 WHDI
transmitter module, presents the ultimate solution for converting any High Definition (HD) system into a wireless
one. This add-on module enables wireless A/V applications that can easily fit into the living room and eliminate
traditional A/V wiring. The ultimate HD video and audio quality and robustness are unmatched by any other
wireless technology and present a true alternative to cable. The WHDI system transmits uncompressed video and
audio streams wirelessly and thus simplifies and eliminates system issues experienced with any other known
wireless-based solutions, such as lip-sync, large buffers and other burdens like retransmissions or error
propagation.
TM
wireless receiver module, together with the AMN11100 WHDITM wireless
1.1 Features
• Uncompressed and uncompromised HD video quality, using AMIMON's baseband chipsets:
AMN2210: WHDI
• WHDI – Wireless High Definition Interface:
Digital video: 30-bit RGB or YCrCb
Digital audio: I2S and SPDIF
Two-wire serial bus slave interface
Two interrupt lines
• Supports any uncompressed video resolutions, including:
HD: 720p, 1080i, 1080p, 576i, 576p, 480p, 480i
PC: VGA (640x480), SVGA (800x600), XGA (1024x768)
Panel: 854x800, 1280x768, 1366x768
TM
Baseband Receiver
• Audio:
Up to 3Mbps audio stream:
• Strong 256-bit AES encryption
• User-defined two-way channel with minimum 10 Kbps for data and control
• Less than 1mSec latency between source and sink
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2
I
S: Two PCM channels (sampled up to 48 KHz x 24 bit)
SPDIF: Including AC-3, DTS
Introduction
• Small mechanical footprint:
With PCB integrated antennas.
Optional external antennas.
• RF characteristics:
MIMO technology, using 5GHz unlicensed band, 18MHz bandwidth.
Coexists with 802.11a/n and 5.8GHz cordless devices.
Support for Automatic Transmission Power Control (ATPC).
No line of sight needed between transmitter and receiver. It has a range of over 30 meters, suitable for
almost any room.
14mW typical transmission power.
Maximum 45mW transmission power.
• Power requirements:
3.3V (±5%), ~5.6W
• Certification & Compliance:
This device complies with part 15 of the FCC Rules. Operation is subject to the following two conditions:
(1) This device may not cause harmful interference, and (2) this device must accept any interference
received, including interference that may cause undesired operation.
Any changes or modifications not expressly approved by Amimon for compliance could void the user's
authority to operate the equipment.
This equipment has been tested and found to comply with the limits for a Class B digital device, pursuant
to part 15 of the FCC Rules. These limits are designed to provide reasonable protection against harmful
interference in a residential installation. This equipment generates uses and can radiate radio frequency
energy and, if not installed and used in accordance with the instructions, may cause harmful interference
to radio communications. However, there is no guarantee that interference will not occur in a particular
installation. If this equipment does cause harmful interference to radio or television reception, which can
be determined by turning the equipment off and on, the user is encouraged to try to correct the
interference by one or more of the following measures:
Reorient or relocate the receiving antenna.
Increase the separation between the equipment and receiver.
Connect the equipment into an outlet on a circuit different from that to which the receiver is
connected.
Consult the dealer or an experienced radio/TV technician for help.
• Caution: The module should be positioned so that personnel in the area for prolonged periods may safely
remain at least 20 cm (8 in) in an uncontrolled environment from the module. Observe FCC OET Bulletin 56
“Hazards of radio frequency and electromagnetic field” and Bulletin 65 “Human exposure to radio frequency
electromagnetic fields.”
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Overview
Chapter 2
Overview
The AMN12100 WHDI Video Display Unit (VDU) is designed to be at the receiver end of the WHDI downstream.
The AMN12100 receives wireless downstream transmission, demodulates it and regenerates the video, audio
and control content transmitted by the AMN11100 WHDI transmitter. The receiver works at the 5GHz unlicensed
Figure 1 displays a block diagram of the AMN12100. It has an MIMO design of five wireless input channels,
band.
and one slow rate output wireless channel, which generates an upstream channel for data content transmissions.
The outputs from the VDU are digital uncompressed video, digital audio and control, all via the WHDI connector.
The MiniMAC uC is responsible for the control and the management.
Connector
TH
80 Pi n WH D I
Interrupt
Control
Two-Wire
VIDEO
Audio
GPIOs
RESET
AMN2210
WHDITM Baseband Receiver
Clock
20MHz
SPI
Int uC Reset
uC
MiniMAC
Figure 1: AMN12100 Block Diagram
E2PROM
Clock40M
Analog
MUX
(RSSI/
PADET)
MAX2828
5Ghz Rx
MAX2828
5Ghz Rx
MAX2828
5Ghz Rx
MAX2828
5Gh z R x
MAX2828
5Ghz Rx&
Uplink
40M
CLOCK
GEN.
PA
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Overview
The main building blocks of the AMN12100 are as follows:
• AMN2210 WHDI Baseband Transmitter, as briefly described on page
• LPC2103 Mini-MAC µController, as briefly described on page
4
• MAX2828 5GHz (802.11a) Transceiver, as briefly described on page
• Power Amplifier (PA), as briefly described on page
TM
• Board Connector (WHDI
• E2PROM, as described on page
• 40MHz Clock Gen, as described on page
Connector), as described on page 5
5
5
5
4
5
2.1 AMN2210 WHDI Baseband Receiver
The AMN2210 WHDITM baseband receiver chip is the heart of the AMN12100 WHDI Receiver module. The
AMN2210 interfaces the A
/V source through the WHDI connector, and is controlled on board by the MiniMAC uC.
Figure 2: WHDI Baseband Receiver Chipset
The AMN2210 is based on MIMO technology receiving up to five input channels. Five analog-to-digital converters
and one digital-to-analog converter are embedded within the chip.
The AMN2210 internal PLL accepts an input clock frequency of 40MHz. The input frequency is multiplied and
then used as an internal system clock.
2.2 LPC2103 Mini-MAC µController
The LPC2103 microcontroller is based on a 16-bit/32-bit ARM7TDMI-S CPU, with embedded 32kB high-speed
memory. It is used as an external microcontroller for implementing the MAC layer of the WHDI link.
The LPC2103 internal PLL accepts an input clock frequency of 20MHz and generates an internal 60MHz system
clock..
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Overview
2.3 MAX2828 5GHz (802.11a) Transceiver
The VDU has five MAX2828 chips embedded in it. The MAX2828 is a single-chip, RF transceiver IC designed
specifically for single-band 4.9GHz to 5.875GHz, OFDM, 802.11 WLAN applications. It includes all the circuitry
necessary to implement the RF transceiver function, providing a fully integrated receive path, transmit path, VCO,
frequency synthesizer and baseband/control interface. Only the PA, RF switches, RF bandpass filters (BPF), RF
BALUNs and a small number of passive components are required to form the complete RF front-end solution.
AMIMON's WHDI
for the video modem. Future generations of the WHDI modem will use an AMIMON-designed, cost-efficient,
single-chip, integrated RFIC for multiple transmits on the transmitter side and a single-chip integrated RFIC for
multiple receivers on the receiver side.
TM
technology uses the low cost and high availability of the 802.11a/n RF to allow low-cost RF
2.4 Power Amplifier (PA)
In order to extend the operating range for the AMN12100 upstream, the RF transmitter uses a power amplifier.
The power amplifier has an output power detector for TPC purposes. Amimon has implemented Anadigics
AWL6951 PA on the AMN12100.
2.5 Board Connector (WHDITM Connector)
For information regarding the connector specification and pin-outs see section 4.1, AMN12100 Board Connector
(WHDI Connector), page
15.
2.6 E2PROM
The E2PROM is currently a system option, enabling mating and authentication in a multipoint design
environment.
2.7 40MHz Clock Gen
An on-board 40MHz TCXO is connected to the MAX2828 chipsets and the AMN2210 baseband. The clock is
then divided by two by the AMN2210 and supplied to the LPC2103 uC.
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Overview
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3.1 Video Data Input and Conversions
Interfaces
Chapter 3
Interfaces
Figure 3: Video Data Receiver Path
Figure 3 shows the basic control over the video data output. Essentially the receiver mirrors the video format of
the transmitter end and so most of the configurations are done on the transmitter end.
The video output data is uncompressed digital video up to 3*10 bits in width. The video interface provides a direct
connection to the inputs of a display device, an HDMI transmitter, or any other video interface device.
Color Space Converter
The receiver can output either RGB or YCbCr color space. For more details, you may refer to the MAC registers
in the programmer's reference guide.
Color Range Limiter
The YCbCr data range can be limited to 16-235.
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Interfaces
Common Video Output Format
Table 1 lists the common supported video output resolutions.
Table 1: Common Supported Video Input Resolutions
Color Space Video Format
RGB/YCbCr 4:4:4 24 27 27 65 74.25 74.25
Bus
Width
480i 480p XGA 720p 1080i
Input Pixel Clock (MHz)
Video Channel Mapping
The 30 bit video output signals are mapped to the RGB and YCbCr color space according to the options
described in the following table:
Table 2: Video Channel Mapping
Option D[29:20] D[19:10] D[9:0]
#1 RED (Cr) GREEN (Y) BLUE (Cb)
#2 RED (Cr) BLUE (Cb) GREEN (Y)
#3 GREEN (Y) RED (Cr) BLUE (Cb)
#4 GREEN (Y) BLUE (Cb) RED (Cr)
#5 BLUE (Cb) RED (Cr) GREEN (Y)
#6 BLUE (Cb) GREEN (Y) RED (Cr)
The AMN121000 allows any of the output video channels options. The first option is the default from power-up. In
order to change the video channel mapping, refer to the appropriate programmer's reference guide.
3.1.1 Video Interface Output Timing Diagram
3.1.1.1 Timing Requirements
Important: The following parameters relate to the AMN2210 baseband chipset and not to the entire AMN12100
board.
Table 3: Video Interface
Symbol Parameter MIN TYP MAX Units
T
DCKCYC
T
DCKFREQ
T
DCKDUTY
T
DCKPDR
T
DCKPDF
D CLK period
CLK frequency
D
DCLK duty cycle 40% 60% ns
Propagation delay after CLK
rising edge
Propagation delay after CLK
falling edge
D
D
12.8 40 ns
25
78.125
1.0 4.0 ns
1.0 4.0 ns
MHz
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3.1.1.2 Timing Diagram
EDGE = 0 EDGE = 1
Interfaces
Figure 4: Timing Diagram
3.2 Audio Data Capture
AMN12100 audio processing logic block receives the audio stream from the WHDI wireless link and regenerates
the appropriate clock and data. If the transmitter end was configured to SPDIF audio interface, then the audio is
output on the receiver side through the SPDIF. The same is true for the I
No constraints exist for a coherent video and audio clock, where coherent means that the audio and the video
clock must have been created from the same clock source. The AMN12100 supports two-channel audio-sampling
frequencies of up to 48KHz, 32 bits per sample.
2
S interface.
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Interfaces
3.2.1 I2S Bus Specification
The AMN12100 supports a standardized communication structure inter-IC sound (I2S) bus. As shown in Figure 5,
the bus has three lines: continuous serial clock (SCK), word select (WS) and serial data (SD). In addition, it has a
MCLK signal which is synchronized to and a multiple of the WS. The external device generating SCK and WS is
the AMN12100.
Figure 5: I2S Simple System Configurations and Basic Interface Timing
The AMN12100 outputs exactly 32 bits for each channel (left and right). By default, the serial data is valid on the
leading (LOW to HIGH) edge of the clock signal, but it can also be configured to be valid on the edge (HIGH to
LOW) of the clock signal. The WS is also valid by default on the leading edge of the clock signal. The WS line
changes one clock period before the first bit of the transmitted channel.
The AMN12100 mirrors the transmitter's end audio inputs and so the MSB and the LSB position are defined at
the audio source at the transmitter side. In case the audio samples in the transmitter are less than 32 bits long,
they are padded with zeroes to generate receiver output samples of 32 bits.
3.2.1.1 MUTE
The AMN12100 has an error detection mechanism. It outputs a high MUTE signal in case of bad audio reception
(bad frames).
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3.2.1.2 Timing Requirements
Table 4: Audio Interface Ouput Timing
Symbol Parameter MIN TYP MAX Units
T
SCKCYC
T
SCKFREQ
T
SCKDUTY
T
DCKPDR
T
DCKPDF
SCK period 325
SCK frequency 1.024
SCK duty cycle 40
Propagation delay after SCK
rising edge
Propagation delay after SCK
falling edge
976 ns
3.072 MHz
60 %
25 ns
25 ns
3.2.1.3 Timing Diagram
Interfaces
EDGE = 1EDGE = 0
Figure 6: I2S Output Timings
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Interfaces
3.3 Management Buses and Connectors
3.3.1 Two-Wire Serial Bus Interface
The WHDI application observes and controls the AMN12100 via a Two-Wire interface and an interrupt line
connecting the application microcontroller and the AMN12100 MiniMAC microcontroller. The protocol of the TwoWire-bus for the WHDI application / MiniMAC interface is described in the following sections.
The Two-Wire bus is bidirectional and, as its name implies, it has only two wires: a Serial Clock Line (SCL) and a
Serial Data Line (SDA). The Two-Wire architecture includes master and slave devices. The master initiates a
data transfer on the bus and generates the clock signal. The AMN12100 MiniMAC operates as a slave device.
Each slave device is recognized by a unique address and can operate as either a receive-only device or a
transmitter with the ability to both receive and send information.
SDA
Application
MicroController
(Two-Wire Master)
Figure 7: Two-Wire / Application-MiniMAC connection
SCL
WHDI MiniMAC
(Two-Wire Slave)
On top of the Two-Wire low level operation described in sections 3.3.1.2 and 3.3.1.3, the WHDI Application and
the MiniMAC microcontrollers communicate with each other in a defined protocol, which avoids all possibilities of
confusion. The protocol defines command oriented transactions between the application and the WHDI MiniMAC.
Each Two-Wire command has a predefined data byte length and is defined to be exactly one Two-Wire
transaction long.
3.3.1.1 Device Addresses
The MiniMAC device address may be altered by two jumpers on VDU/VSU board.
Table 5: Device Addresses
Device Address
MiniMAC uC 0x62 or 0x82 or 0x90 or 0x70
(Board configuration dependant)
Alternatively, the device address can be set in the MAC SW in advance.
3.3.1.2 MiniMAC uC Write Operation
Figure 8 demonstrates a write transaction which sends 2 data bytes and which ends with the master stop bit.
Each write transaction sends one or more data bytes to the MiniMAC, beginning at an explicit 2 bytes long
address. Multiple data bytes may be written as the MiniMAC stores the received register data until the master
sends a stop bit. The MiniMAC updates the register value upon a successful termination of a write transaction.
Two-Wire Slave address ack
...
I
6
5
writeI
register address ack
A
...
A
15
14
register address ack
A
8
...
A
A
7
6
A
0
register data0 ack
D7 D0D6
...
register data1 ack
D
...
D
7
6
D
STOPSTART
0
Figure 8: Two-Wire MiniMAC Write Commands
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Interfaces
3.3.1.3 MiniMAC uC Read Operation
This operation reads from a specific 2- byte address. The read transaction is divided into two parts. In the first
part, the Two-Wire master sends a write command to the slave containing only the required start address. (The
address is always 2 bytes long.) In the second part, multiple bytes may be read from consecutive addresses. The
MiniMAC puts the appropriate data on the Two-Wire bus and the internal address is automatically incremented. A
stop bit is sent by the master only when the entire transaction has been completed.
Two-Wire Slave address ack register address ack register address
START
I
6
writeI
A
5
...
A
15
14
A
A
8
...
7
A
6
ack
Two-Wire sl ave address ack
A
0
...
I
START Data Byte 0
6
readI
5
...
register dat a ack
register data ack
Data Byte 1
STOP
Figure 9: Two-Wire Read Command
3.3.1.4 WHDI Application / MiniMAC Protocol
The WHDI programmer’s reference defines the MiniMAC registers data structure. Each register has an
associated group id and index offset address.
The group id and the index offset are each 1 byte long. Together they define a register address that is 2 bytes
long.
Each register has an attributed length (in byte units). All registers within the same group have the same length.
A Two-Wire transaction to a specific register includes 2 bytes of register address and the register data bytes. The
register is written in one transaction. If the transaction terminates ahead of time or is too long, the MiniMAC
issues an error interrupt and does not store the received values. The register is read in one transaction, as
described in section
3.3.1.3. If the read transaction finishes ahead of time, the MiniMAC issues an error interrupt.
3.3.2 Interrupts
There is one interrupt connected to the WHDI connector. The interrupt source is the AMN2110 MiniMAC uC. For
details about the interrupt, please refer to the programmer's user guide.
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Interfaces
3.4 Reset and Wake-up Timer
The AMN12100 has one hard RESET input pin connected directly to the AMN2110 and through a MicroPower
circuit to the LPC2103 uC, as described in
pin for about 150msec. Assertion of the LPC2103 reset starts its internal wake-up timer, causing the internal chip
reset to remain asserted until the external reset is de-asserted, the 20MHz clock runs, a fixed number of clocks
have passed and the on-chip flash controller has completed its initialization.
When the LPC2103 internal reset is removed, the processor begins executing at address 0, which is the reset
vector. At that point, all of the processor and peripheral registers have been initialized to predetermined reset
values. The processor initializes the AMN2110 baseband chipset. After the reset is de-asserted for TBD msec, it
is ready to operate.
The wake-up timer monitors the 20MHz clock in order to check whether it is safe to begin code execution.
Figure 10. Upon power up, the MicroPower circuit asserts the uC reset
Figure 10: Reset Mechanism
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AMIMON Confidential 14
WHDI Connector Pin-Outs
Chapter 4
WHDI Connector Pin-Outs
4.1 Signals
Table 6: WHDI Connector Signals
# of
Pins
30 D[29:0] 30-bit RGB (10:10:10) or YCrCb (10:10:10) Video Out
1 DCLK Video data clock Video Out Up to 78.125 MHz
1 DE Data enable Video Out
1 H_SYNC Horizontal sync Video Out
1 V_SYNC Vertical sync Video Out
1 SPDIF SPDIF audio interface Audio Out
1 SD I2S audio interface Serial Data signals
1 SCLK I2S continuous serial clock Audio Out Up to 3.072Mbps
1 WS(LRCLK) I2S Word Select (Left/right clock) which
1 MCLK I2S master clock coherent to WS according to
1 SDA Two-wire Serial Bus Data (Slave Mode) Control I/O Control I/F for WHDI
1 SCL Two-wire Serial Bus Clock (Slave Mode) Control In Control I/F for WHDI
1 INT Interrupt from WHDI module Control Out
1
1 MUTE MUTE signal Audio Out Signals audio error
6 TBD[5:0] TBD0, TBD1, TBD4, TBD5 are reserved in
8 3.3V VCC Power Power 300 mA maximum
6 3.3V_OR_5V High Power rail pins,
15 GND Ground Power Power
Pin Name Description / Functionality Group Direction
Audio Out
Audio Out
Audio Out Rate is adjustable on
TBD TBD
Power Power For board designed
RESET
defines also the sampling rate
specified ratio
Reset / Power-down line Control In
AMN11100, AMN12100 as an option for
external power rail to the on board uC
In AMN11100, AMN12100 connect these
power rail pins to the 3.3V power rail
Remarks
RX side
and can be used by
the next audio device
down the line to mute
the audio when errors
occur
rating per pin
as "High-Power" PA
connect this rail to 5V,
For Rx (AMN12100)
connect always to
3.3V power
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AMIMON Confidential 15
4.2 Connector Schematics
WHDI Connector
Note: For AMN11100 and AMN12100
boards connect to 3.3V power rail
3.3V_OR_5V
Note: uP external power option
R1NCR0603 1 2
R3NCR0603 1 2
WHDI_TBD0
WHDI_TBD1
WHD I_RESET_
WHDI_INT
WHDI_TBD2
WHDI _D28
WHDI _D26
WHDI _D24
WHDI _D22
WHDI _D20
WHDI _D18
WHDI _D16
WHDI _D14
WHDI_DCLK
WHDI_TBD3
WHDI _D12
WHDI _D10
WHDI_D8
WHDI_D6
WHDI_D4
WHDI_D2
WHDI _H_SYNC
WHDI_MCLK
WHD I_I2S_D1
WHDI_LRCLK
J1
FX10A-80P/8-SV1
FX10A-80P_8-SV1
1
1
3
3
5
5
7
7
9
9
S1
S1
11
11
13
13
15
15
17
17
19
19
21
21
23
23
25
25
27
27
29
29
S3
S3
31
31
33
33
35
35
37
37
39
39
41
41
43
43
45
45
47
47
49
49
S5
S5
51
51
53
53
55
55
57
57
59
59
61
61
63
63
65
65
67
67
69
69
S7
S7
71
71
73
73
75
75
77
77
79
79
WHDI Connector Pin-Outs
3.3V
Note: For AMN11100 and AMN12100
2
2
4
4
6
6
8
8
10
10
S2
S2
12
12
14
14
16
16
18
18
20
20
22
22
24
24
26
26
28
28
30
30
S4
S4
32
32
34
34
36
36
38
38
40
40
42
42
44
44
46
46
48
48
50
50
S6
S6
52
52
54
54
56
56
58
58
60
60
62
62
64
64
66
66
68
68
70
70
S8
S8
72
72
74
74
76
76
78
78
80
80
boards connect to 3.3V power rail
3.3V_OR_5V
Note: uP external power option
WHDI_TBD4
WHDI_TBD5
WHDI_SCL
WHDI_SDA
WHDI_TBD6
WHD I_D29
WHD I_D27
WHD I_D25
WHD I_D23
WHD I_D21
WHD I_D19
WHD I_D17
WHD I_D15
WHD I_D13
WHD I_D11
WHDI_D9
WHDI_D7
WHDI_D5
WHDI_D3
WHDI_D1
WHDI_D0
WHDI_DE
WHD I_V_SYNC
WHD I_SPDIF
WHD I_I2S_D0
WHDI_SCLK
uP_V
R2NCR0603 1 2
R4NCR0603 1 2
Note: Max. current rating per pin 0.3 Amp
Figure 11: WHDI Connector
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AMIMON Confidential 16
WHDI Connector Pin-Outs
4.3 Pin List
Table 7: Rx WHDI Connector Pin List
Pin
Signal
Number
1 3.3V 31 1.8V(*) 61 D12
2 3.3V 32 1.8V(*) 62 D7
3 3.3V 33
4 3.3V 34 SCL 64 D5
5 3.3V 35 INT 65 D8
6 3.3V 36 SDA 66 D3
7 3.3V 37 N.C 67 D6
8 3.3V 38 MUTE 68 D1
9 3.3V_OR_5V(**) 39 D28 69 D4
10 3.3V_OR_5V(**) 40 D29 70 D0
11 3.3V_OR_5V(**) 41 D26 71 D2
12 3.3V_OR_5V(**) 42 D27 72 DE
13 3.3V_OR_5V(**) 43 D24 73 HSYNC
14 3.3V_OR_5V(**) 44 D25 74 VSYNC
15 GND 45 D22 75 MCLK
16
17
18
19
20
21
22
23
24
25
26
27
28
29 1.8V(*) 59 N.C
30 1.8V(*)
(*) Optional – Contact Amimon Ltd. for more details.
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
(**)These lines should be connected to a 3.3V power supply. An option for a 5V power supply exists for
extended range. Extended range requires a different AMN1210 version. Contact Amimon Ltd. for more
details.
Pin
Signal
Number
RESET
46 D23 76 SPDIF
47 D20 77 N.C.
48 D21 78 I2S_D0
49 D18 79 LRCLK
50 D19 80 SCLK
51 D16
52 D17
53 D14
54 D15
55 GND
56 D13
57 DCLK
58 D11
60 D9
Pin
Signal
Number
63 D10
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WHDI Connector Pin-Outs
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AMIMON Confidential 18
Electrical Specifications
Chapter 5
Electrical Specifications
5.1 Operating Conditions and Electrical Characteristics
The following tables describe the operating conditions and electrical characteristics required for working with the
AMN12100.
Table 8: Absolute Maximum Ratings over Operating Case Temperature Range
Supply input-voltage range, VI 0 to 3.6 V
Ambient temperature range
Storage temperature range, Tstg
Table 9: Recommended Operating Conditions
Parameter Min. Typ. Max. Unit
DV
V
V
V
V
V
I
OH
I
OL
T
SS
IH
IL
OH
OL
C
Module supply voltage 3.15 3.3 3.45 V
DD
Supply ground 0 V
High-level input voltage 0.7 DV
Low-level input voltage 0.3 DV
High-level output voltage (DV
Low-level output voltage (DV
DD
= MIN, I
DD
= MIN, I
= MAX) 0.8 DV
OH
= MAX) 0.22 DV
OL
High-level output current -8 mA
Low-level output current 8 mA
Operating case temperature 0 70
0°C to 70°C
-40°C to 125°C
DD
DD
V
DD
V
V
DD
V
°C
Table 10: Electrical Characteristics over Recommended Range of Supply Voltage and Operating Conditions
Parameter Test Conditions Min. Typ. Max. Unit
I
I
I
OZ
I
DVDD
C
C
Input current
Off-state output current
Module supply
i
o
Input capacitance
Output capacitance
= VSS to DV
V
I
= DV
V
O
DV
DD
with activity on all I/O terminals
DD
or 0 V
DD
= Max., Video Clock = 75 MHz,
±20
±20
μA
μA
1800 mA
10 pF
10 pF
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Electrical Specifications
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Design Guidelines
Chapter 6
Design Guidelines
6.1 Digital Layout Recommendation
To better understand the layout guidelines, please refer to the AMN12100 schematics which are part of the HDK
package.
6.1.1 Stuck Up
Recommended stuck up for 10 layers design:
• Total thickness 1.6mm
• Tolerance: 10%
Table 11: Digital Layout Recommendation
Conductor Width [mil] Control Impedance [ohm]
StuckUp Before Stripline Differential
thickness Scale Required Design Before Before
Title Des. Oz/mil Layer line space line space Required Design Required Design Type No
Cu 0.5 Oz CS 5 0 5.25 5.25 0 0 100 100 SIG L1
Space 7 mil 15 30 14 31 0 0 50 48
Cu 0.5 Oz L2 11 0 12 0 50 50 0 0 GND L2
Space 4 mil 0 0 0 0 0 0 0 0
Cu 0.5 Oz L3 5 6 4.25 6.75 0 0 100 100 SIG L3
Space 7 mil 6 0 5 0 50 50 0 0
Cu 0.5 Oz L4 0 0 0 0 0 0 0 0 GND L4
Space 4 mil 0 0 0 0 0 0 0 0
Cu 0.5 Oz L5 0 0 0 0 0 0 0 0 VCC L5
Space 9 mil 0 0 0 0 0 0 0 0
Cu 0.5 Oz L6 5 6 4.5 6.5 0 0 100 100 SIG L6
Space 4 mil 6 0 5.5 0 50 50 0 0
Cu 0.5 Oz L7 0 0 0 0 0 0 0 0 GND L7
Space 7 mil 0 0 0 0 0 0 0 0
Cu 0.5 Oz L8 5 6 4.25 6.75 0 0 100 100 SIG L8
Space 4 mil 6 0 5 0 50 50 0 0
Cu 0.5 Oz L9 11 0 12 0 50 50 0 0 GND L9
Space 7 mil 15 30 14 31 0 0 50 48
Cu 0.5 Oz PS 5 0 5.25 5.25 0 0 100 100 SIG L10
Layer
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AMIMON Confidential 21
Design Guidelines
6.1.2 General Guidelines
• Keep traces as short as possible.
• Traces should be routed over full solid reference plans.
• Sensitive lines like reset and clocks should be routed with special care.
These lines should be routed over full solid power plans (ground or power).
Traces should be routed at least 2 times the trace width away from other lines in the same routing layer.
Place a series resistor ~30 ohm at the clock source.
• Keep digital signals away from the analog side.
6.1.3 WHDI Lines
• Place series resistors on all output lines (near the outputs pins).
• Series resistors on input lines are unnecessary. (The series resistors should be placed on the interface
board.)
6.1.4 Power and Ground
• Use a solid ground plan.
• Ground plans separation is unnecessary.
• Place decoupling capacitors near power pins. (Refer to the schematics and BOM for recommended values.)
• Analog power pins should be filtered with ferrite beads. (Refer to the schematics and BOM for recommended
values.)
6.1.4.1 Power Rails/Pins Summary for AMN2210 Chip:
• Analog:
1.2 Volt:
Pins names:
AD12_0_AVDD1V2
AD12_0_ARVDD1V2
AD12_1_AVDD1V2
AD12_1_ARVDD1V2
AD12_2_AVDD1V2
AD12_2_ARVDD1V2
AD12_3_AVDD1V2
AD12_3_ARVDD1V2
AD12_4_AVDD1V2
AD12_4_ARVDD1V2
DA10_AVDD1V2
PLL0_AVDD
PLL1_AVDD
PLLA_AVDD
AD8_AVDD1V2
3.3 Volt:
Pins:
AD8_AVDD3V3
DA10_AVDD3V3
O_PRE_AVDD
IO_PST_AVDD
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AMIMON Confidential 22
Design Guidelines
• Digital:
1.2 Volt:
Pins names:
VDD_0 to VDD_9 (total 10 pins)
3.3 Volt:
Pins:
VDD_IO_0 to VDD_IO_8 (total 9 pins)
6.2 RF Design Recommendation
6.2.1 RF Components
All passive components must have compatible performance with components used in the Amimon reference
design.
6.2.2 Power Management
The power management is divided such that each channel has an independent filtered power supply of 2.85Vdc.
Figure 1 shows the power scheme of the RF section of the receiver.
3.3v
120mA/Low Noise
Power
Amplifier/
300mA
RSSI MUX
3.3V/10mA
TCXO+Buffers
20mA
300mA
LDO
Clock Circuit
LDO
120mA
Synth.
70mA
300mA
LDO
Vcc
MAX2828
120mA
Synth.
70mA
300mA
LDO
Vcc
MAX2828
120mA
Synth.
70mA
300mA
LDO
Vcc
MAX2828
120mA
Synth.
70mA
300mA
LDO
120mA
Vcc
MAX2828
Vcc
Synth.
70mA
MAX2828
Figure 12: Receiver RF Power Scheme
6.2.3 Device Application Notes
For the best performance, follow the application guidelines of the chosen devices.
Regarding the MAX2828 transceiver, follow the Application Note AN3630 that can be downloaded from Maxim-ic
website.
6.2.4 Antennas
The design of the antennas and matching is performed individually for each product. Changing board stack-up or
outline of the RF section can impact the system performance and a matching procedure should be performed.
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Design Guidelines
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Mechanical Dimensions
The following shows the mechanical dimensions for the AMN12100:
Mechanical Dimensions
Chapter 7
Figure 13: Mechanical Dimensions
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Mechanical Dimensions
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