AMD DS42585 Service Manual

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PRELIMINARY

DS42585

Stacked Multi-Chip Package (MCP) Flash Memory and SRAM

Am29DL324D Bottom Boot 32 Megabit (4 M x 8-Bit/2 M x 16-Bit) CMOS 3.0 V o lt-only, Simultaneous Operation Flash Memory and 8 Mbit (1 M x 8-Bit/512 K x 16-Bit) Static RAM

DISTINCTIVE CHARACTERISTICS MCP Features

■ Power supply voltage of 2.7 to 3.3 volt

■ High performance

— 85 ns maximum access time

■ Package

— 73-Ball FBGA

■ Operating Temperature

— –25°C to +85°C

Flash Memory Features

ARCHITECTURAL ADVANTAGES

■ Simultaneous Read/Write oper at io ns

— Data can be continuously read from one bank while

executing erase/program functions in other bank

— Zero latency between read and write operations

■ Secured Silicon (SecSi) Sector: Extra 64 KByte sector

— Factory locked and identifiable: 16 bytes available for

secure, random factory Electronic Serial Number; verifiable as factory locked through autoselect function.

— Customer lockable: Can be read, programmed, or erased

just like other sectors. Once locked, data cannot be changed

■ Zero Power Operation

— Sophisticated power management circuits reduce power

consumed during inactive periods to nearly zero

■ Bottom boot block

■ Manufactured on 0.23 µm process technology

■ Compatible with JEDEC standards

— Pinout and software compatible with single-power-supply

flash standard

PERFORMANCE CHARACTERISTICS

■ High performance

— Access time as fast 70 ns — Program time: 7 µs/word typical utilizing Accelerate function

■ Ultra low power consump tion (typical values)

— 2 mA active read current at 1 MHz — 10 mA active read current at 5 MHz — 200 nA in standby or automatic sleep mode

■ Minimum 1 mill ion write cycles guaranteed per sector

■ 20 Year data retention at 125°C

— Reliable operation for the life of the system

SOFTWARE FEATURES

■ Data Management Software (DMS)

— AMD-supplied software manages data programming and

erasing, enabling EEPROM emulation

— Eases sector erase limitations

■ Supports Common Flash Memory Interface (CFI)

■ Erase Suspend/Erase Resume

— Suspends erase operations to allow programming in same

bank

■ Data# Polling and Toggle Bits

— Provides a software method of detecting the status of

program or erase cycles

■ Unlock Bypass Program command

— Reduces overall programming time when issuing multiple

program command sequences

HARDWARE FEATURES

■ Any combination of sectors can be erased

■ Ready/Busy# output (RY/BY#)

— Hardware method for detecting program or erase cycle

completion

■ Hardware reset pin (RESET#)

— Hardware method of resetting the internal state machine to

reading array data

■ WP#/ACC input pin

— Write protect (WP#) function allows protection of two outermost

boot sectors, regardless of sector protect status

— Acceleration (ACC) function accelerates program timing

■ Sector protection

— Hardware method of locking a sector, either in-system or

using programming equipment, to prevent any program or erase operation within that sector

— Temporary Sector Unprotect allows changing data in

protected sectors in-system

SRAM Features

■ Power dissipation

— Operating: 50 mA maximum — Standby: 7 µA maximum

■ CE1s# and CE2s Chip Select

■ Power down features us ing CE1s# and CE2s

■ Data retention supply voltage: 1.5 to 3.3 volt

■ Byte data control: LB#s (DQ0–DQ7), UB#s (DQ8–DQ15)

This document contains information on a product under development at Advanced Micro Devices. The information is intended to help you evaluate thi s product. AMD reserves t he right to chan ge or discontinue w ork on this proposed product without notice.

Refer to AMD’s Website (www.amd.com) for the latest information.

Publication# 25032 Rev: A Amendment/0 Issue Date: May 22, 2001

GENERAL DESCRIPTION

PRELIMINARY

Am29DL324 Features

The Am2 9DL324 is a 3 2 megabit, 3.0 volt-only flash memory devices, organiz ed as 2,097 ,152 words of 16 bits each or 4,194,304 bytes of 8 bits each. Word mode data appears on DQ0–DQ15; byte mode data appears on DQ0–DQ7. The device is designed to be programmed in-system with the standard 3.0 volt V supply, and can also be progr ammed in standar d EPROM programmers.

The device is available with an access time of 85 ns. The device is offered in a 73-ball FBGA package. Standard con trol pins—chip enable (CE#f), write enable (WE#), and out put enab le (OE #)—c ontro l nor mal read and write operations, and avoid bus contention issues.

The device requires only a single 3.0 volt power sup- ply for both read and write functions. Internally generated and regulated voltag es are pr ovided for the program and erase operations.

Simultaneous Read/Write Ope rations with Zero Latency

The Simultaneous Read/Write architecture provides simultaneous operation by dividing the memory space into two banks. The device can improve overall system performance b y a llowi ng a hos t s yste m to program or erase in one bank, then immediately and simultaneously read from the othe r bank, with zero latency. This releases the system from waiting for the completion of program or erase operations.

The Am29DL324D has 16 Mb in each bank. The Secured Silicon (SecSi) Sector is an extra 64

Kbit sector capable of being permanently lo cked by AMD or customers. The SecSi Sector Indicator Bit (DQ7) is permane ntly set to a 1 if the part is factory locked, and set to a 0 if c ustomer lockable. This way, customer lockable parts ca n nev er be us ed to r eplace a factory locked part.

Factory locked parts provide several options. The SecSi Sector may store a secu re, random 16 by te ESN (Electronic Serial Number). Customer Lockable parts may utilize the Sec Si Sector as bonus space , reading and writing like any other flash sector, or may permanently lock their own code there.

DMS (Data Management Software) allows systems to easily take ad vantag e of the adva nced ar chitec ture of the simultaneous read/write product line by allowing

removal of EEPROM devices. DMS will also allow the system software to be simplified, as it will p erform all functions necessary to modify data in file structures, as opposed to single-byte modi fications. To write or update a particular piece of data (a phone number or configuration data, for example), the user only needs to state which piece of data is to be updated, and where the updated data is located in the system. This is an advantage compared to systems where user-written software must keep tr ack of the old da ta location, status, logical to physical translation of the data onto the Flash memory device (or m emory devices), and more. Using DMS, user-written software does not need to interface with the Flash memory directly. Instead, the user's software accesses t he Fl as h memory by calling one of onl y six func tions . AMD provides this software to simplify system design and software integration efforts.

The device offers complete compatibility with the

JEDEC single-power-supply Flash command set standard. Commands ar e written to the comman d

register using standard microprocessor write timings. Reading data out of the device is similar to reading from other Flash or EPROM devices.

The host system can detect whether a program or erase operation is complete by using the device sta- tus bits: RY/BY# pin, DQ7 (D ata# Polling) and DQ6/DQ2 (toggle bits). After a program or erase cycle has been completed, the device automatically returns to reading array data.

The sector erase architecture allows memory sectors to be erased and reprogra mmed withou t affecting the data contents of other sectors. The device is fully erased when shipped from the factory.

Hardware data protection measures include a low

detector that automatically inhibits write opera-

tions during power transitions. The hardware secto r protection feature disables both program and erase operations in any combination of the sectors of memory. This can be achieved in-system or via programming equipment.

The device offers two power-saving features. Whe n addresses have been sta ble f or a spe cified am ount o f time, the device enters the automatic sleep mode. The system can also place the device into the standby mode. Power consumption is greatly reduced in both modes.

2 DS42585

PRELIMINARY

TABLE OF CONTENTS

Distinctive Characteristics . . . . . . . . . . . . . . . . . . 1

MCP Features . . . . . . . . . . . . . . . . . . . . . . . . . . . .1

Flash Memory Features . . . . . . . . . . . . . . . . . . . . .1

Architectural Advantages . . . . . . . . . . . . . . . . . . .1

Performance Characteristics . . . . . . . . . . . . . . . .1

Software Features . . . . . . . . . . . . . . . . . . . . . . . .1

Hardware Features . . . . . . . . . . . . . . . . . . . . . . .1

SRAM Features . . . . . . . . . . . . . . . . . . . . . . . . . . .1

General Description. . . . . . . . . . . . . . . . . . . . . . . . 2

Am29DL324 Features . . . . . . . . . . . . . . . . . . . . . .2

Simultaneous Read/Write Operations with

Zero Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2

Product Selector Guide . . . . . . . . . . . . . . . . . . . . . 5

MCP Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . 5

Flash Memory Block Diagram. . . . . . . . . . . . . . . . 6

Connection Diagram . . . . . . . . . . . . . . . . . . . . . . . 7

Special Handling Instructions for FBGA Package .7

Pin Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Ordering Information. . . . . . . . . . . . . . . . . . . . . . . 8

Device Bus Operations . . . . . . . . . . . . . . . . . . . . . 8

Table 1. Device Bus Operations—Flash Word Mode, CIOf = V CIOs = V

Table 2. Device Bus Operations—Flash Word Mode, CIOf = V CIOs = V

Table 3. Device Bus Operations—Flash Byte Mode, CIOf = V CIOs = V

Word/Byte Configuration . . . . . . . . . . . . . . . . . . . 12

Requirements for Reading Array Data . . . . . . . . .12

Writing Commands/Command Sequences . . . . .12

Accelerated Program Operation . . . . . . . . . . . .12

Autoselect Functions . . . . . . . . . . . . . . . . . . . . .12

Simultaneous Read/Write Operations with Zero

Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12

Standby Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Automatic Sleep Mode . . . . . . . . . . . . . . . . . . . . .13

RESET#: Hardware Reset Pin . . . . . . . . . . . . . . .13

Output Disable Mode . . . . . . . . . . . . . . . . . . . . . .13

Table 4. Device Bank Division . . . . . . . . . . . . . .13

Table 5. Sector Addresses for Bottom Boot

Sector Devices . . . . . . . . . . . . . . . . . . . . . . . . . .14

Table 6. SecSi Sector Addresses for Bottom

Boot Devices . . . . . . . . . . . . . . . . . . . . . . . . . . .15

Autoselect Mode . . . . . . . . . . . . . . . . . . . . . . . . . 16

Sector/Sector Block Protection and Unprotection 16

Table 7. Bottom Boot Sector/Sector Block

Addresses for Protection/Unprotection . . . . . . .16

Write Protect (WP#) . . . . . . . . . . . . . . . . . . . . . . .16

Temporary Sector/Sector Block Unprotect . . . . . .17

Figure 1. Temporary Sector Unprotect

Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Figure 2. In-System Sector/Sector Blo ck

Protect and Unprotect Algorithms. . . . . . . . . . . 18

; SRAM Word Mode,

. . . . . . . . . . . . . . . . . . . . . . . . . . . . .9

; SRAM Byte Mode,

. . . . . . . . . . . . . . . . . . . . . . . . . . . .10

; SRAM Byte Mode,

. . . . . . . . . . . . . . . . . . . . . . . . . . . .11

SecSi (Secured Silicon) Sector Flash Memory

Region . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Factory Locked: SecSi Sector Programmed

and Protected At the Factory . . . . . . . . . . . . . . 19

Customer Lockable: SecSi Sector NOT

Programmed or Protected At the Factory . . . . . 19

Hardware Data Protection . . . . . . . . . . . . . . . . . . 19

Low V

Write Inhibit . . . . . . . . . . . . . . . . . . . . 19

Write Pulse “Glitch” Protection . . . . . . . . . . . . . 19

Logical Inhibit . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Power-Up Write Inhibit . . . . . . . . . . . . . . . . . . . 20

Common Flash Memory Interface (CFI) . . . . . . . 20

Table 8. CFI Query Identification String . . . . . . 20

Table 9. System Interface String . . . . . . . . . . . 21

Table 10. Device Geometry Definition . . . . . . . 21

Table 11. Primary Vendor-Specific Extended

Query . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Command Definitions. . . . . . . . . . . . . . . . . . . . . . 23

Reading Array Data . . . . . . . . . . . . . . . . . . . . . . . 23

Reset Command . . . . . . . . . . . . . . . . . . . . . . . . . 23

Autoselect Command Sequence . . . . . . . . . . . . . 23

Enter SecSi Sector/Exit SecSi Sector

Command Sequence . . . . . . . . . . . . . . . . . . . . . . 24

Byte/Word Program Command Sequence . . . . . 24

Unlock Bypass Command Sequence . . . . . . . . 24

Figure 3. Program Operation. . . . . . . . . . . . . . . 25

Chip Erase Command Sequence . . . . . . . . . . . . 25

Sector Erase Command Sequence . . . . . . . . . . . 25

Erase Suspend/Erase Resume Commands . . . . 26

Figure 4. Erase Operation . . . . . . . . . . . . . . . . . 26

Table 12. DS42585 Command Definitions . . . . 27

Write Operation Status. . . . . . . . . . . . . . . . . . . . . 28

DQ7: Data# Polling . . . . . . . . . . . . . . . . . . . . . . . 28

Figure 5. Data# Polling Algorithm . . . . . . . . . . . 28

RY/BY#: Ready/Busy# . . . . . . . . . . . . . . . . . . . . . 29

DQ6: Toggle Bit I . . . . . . . . . . . . . . . . . . . . . . . . . 29

Figure 6. Toggle Bit Algorithm . . . . . . . . . . . . . . 29

DQ2: Toggle Bit II . . . . . . . . . . . . . . . . . . . . . . . . 30

Reading Toggle Bits DQ6/DQ2 . . . . . . . . . . . . . . 30

DQ5: Exceeded Timing Limits . . . . . . . . . . . . . . . 30

DQ3: Sector Erase Timer . . . . . . . . . . . . . . . . . . 30

Table 13. Write Operation Status . . . . . . . . . . . 31

Absolute Maximum Ratings. . . . . . . . . . . . . . . . . 32

Operating Ranges. . . . . . . . . . . . . . . . . . . . . . . . . 32

Industrial (I) Devices . . . . . . . . . . . . . . . . . . . . . 32

f/VCCs Supply Voltage . . . . . . . . . . . . . . . . . 32

DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 33

CMOS Compatible . . . . . . . . . . . . . . . . . . . . . . . 33

SRAM DC and Operating Characteristics. . . . . . 34

Zero-Power Flash . . . . . . . . . . . . . . . . . . . . . . . 35

Figure 9. I

Current vs. Time (Showing

CC1

Active and Automatic Sleep Currents). . . . . . . . 35

Figure 10. Typical I

vs. Frequency . . . . . . . . 35

CC1

Test Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Figure 11. Test Setup . . . . . . . . . . . . . . . . . . . . 36

Table 14. Test Specifications . . . . . . . . . . . . . . 36

DS42585 3

PRELIMINARY

Key To Switching Waveforms. . . . . . . . . . . . . . . 36

Figure 12. Input Waveforms and Measurement

Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . 37

SRAM CE#s Timing . . . . . . . . . . . . . . . . . . . . . . .37

Figure 13. Timing Diagram for Alternating

Between SRAM to Flash. . . . . . . . . . . . . . . . . . 37

Flash Read-Only Operations . . . . . . . . . . . . . . . .38

Figure 14. Read Operation Timings . . . . . . . . . 38

Hardware Reset (RESET#) . . . . . . . . . . . . . . . . .39

Figure 15. Reset Timings . . . . . . . . . . . . . . . . . 39

Flash Word/Byte Configuration (CIOf) . . . . . . . . .40

Figure 16. CIOf Timings for Read Operations . 40 Figure 17. CIOf Timings for Write Operations. . 40

Flash Erase and Program Operations . . . . . . . . .41

Figure 18. Program Operation Timings. . . . . . . 42

Figure 19. Accelerated Program Timing

Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Figure 20. Chip/Sector Erase Operation

Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Figure 21. Back-to-back Read/Write Cycle

Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Figure 22. Data# Polling Timings (During

Embedded Algorithms) . . . . . . . . . . . . . . . . . . . 44

Figure 23. Toggle Bit Timings (During

Embedded Algorithms) . . . . . . . . . . . . . . . . . . . 45

Figure 24. DQ2 vs. DQ6 . . . . . . . . . . . . . . . . . . 45

Temporary Sector/Sector Block Unprotect . . . . . .46

Figure 25. Temporary Sector/Sector Block

Unprotect Timing Diagram . . . . . . . . . . . . . . . . 46

Figure 26. Sector/Sector Block Protect and

Unprotect Timing Diagram. . . . . . . . . . . . . . . . . 47

Alternate CE#f Controlled Erase and Program

Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Figure 27. Flash Alternate CE#f Controlled

Write (Erase/Program) Operation Timings . . . . 49

SRAM Read Cycle . . . . . . . . . . . . . . . . . . . . . . . 50

Figure 28. SRAM Read Cycle—Address

Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Figure 29. SRAM Read Cycle . . . . . . . . . . . . . . 51

SRAM Write Cycle . . . . . . . . . . . . . . . . . . . . . . . . 52

Figure 30. SRAM Write Cycle—WE# Control . . 52

Figure 31. SRAM Write Cycle—CE1#s Control. 53

Figure 32. SRAM Write Cycle—UB#s and

LB#s Control . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Flash Erase And Programming Performance . . . 55

Flash Latchup Characteristics. . . . . . . . . . . . . . . 55

Package Pin Capacitance . . . . . . . . . . . . . . . . . . 55

Flash Data Retention . . . . . . . . . . . . . . . . . . . . . . 55

SRAM Data Retention. . . . . . . . . . . . . . . . . . . . . . 56

Figure 33. CE1#s Controlled Data Retention

Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Figure 34. CE2s Controlled Data Retention

Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . 57

FLB073—73-Ball Fine-Pitch Grid Array

8 x 11 mm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 58

Revision A (May 22, 2001) . . . . . . . . . . . . . . . . . 58

4 DS42585

PRELIMINARY

PRODUCT SELECTOR GUIDE

Part Number DS42585

Standard Voltage Range: VCC = 2.7–3.3 V Flash Memory SRAM Max Access Time (ns) 85 85 CE# Access (ns) 85 85 OE# Access (ns) 40 45

MCP BLOCK DIAGRAM

A0 to A20

–

WP#/ACC

RESET#

CE#f

CIOf

LB#s

UB#s

WE#

OE#

CE1#s

CE2s

CIOs

A0 to A20

A0 to A19

A0 to A18

VCCf

32 M Bit

Flash Memory

VCCs/V

CCQ

8 M Bit

Static RAM

VSS/V

DQ0 to DQ15/A

SSQ

DQ0 to DQ15/A

RY/BY#

–

DQ0 to DQ15/A

–

DS42585 5

PRELIMINARY

FLASH MEMORY BLOCK DIAGRAM

A0–A20

Upper Bank Address

Upper Bank

OE# BYTE#

Y-Decoder

A0–A20

RESET#

WE#

CE#

BYTE#

WP#/ACC

DQ0–DQ15

RY/BY#

A0–A20A0–A20

STATE

CONTROL

& COMMAND REGISTER

X-Decoder

Status

Control

X-Decoder

Latches and Control Logic

DQ0–DQ15

DQ0–DQ15 DQ0–DQ15

A0–A20

Lower Bank Address

Lower Bank

Y-Decoder

Latches and

Control Logic

OE# BYTE#

6 DS42585

CONNECTION DIAGRAM

PRELIMINARY

73-Ball FBGA

CE#f

OE#

LB#

UB#

A18

A17

DQ1

DQ9

WP#/ACC

RESET#

RY/BY#

DQ3

WE#

CE2s

A20

DQ4

A19

A10

DQ6

DQ13

A11

A12

A13

A14

DQ15/A-1

A15

A16

CIOf

A10

B10

F10

G10

Flash only

SRAM only

Shared

CE1#s

DQ0

DQ8

DQ10

DQ2

DQ11

CIOs

Special Handling Instructions for FBGA Package

Special handling is required for Flash Memory products in FBGA packages.

DQ12

DQ5

DQ7

DQ14

L10

M10

Flash memory dev ices in FBGA pa ckages may be damaged if exposed to ultrasonic cleaning methods. The package and/or data integrity may be compromised if the package body is exposed to temperatures above 150

°C for prolonged periods of time.

DS42585 7

PRELIMINARY

PIN DESCRIPTION

A0–A18 = 19 Address Inputs (Common) A-1, A19–A20 = 3 Address Inputs (Flash) SA = Highest Order Address Pin (SRAM)

Byte mode DQ0–DQ15 = 16 Data Inpu ts /Outpu ts (Co mmo n) CE#f = Chip Enable (Flash) CE#s = Chip Enable (SRAM) OE# = Output Enable (Common) WE# = Write Enable (Common) RY/BY# = Ready/Busy Output UB#s = Upper Byte Control (SRAM) LB#s = Lower Byte Control (SRAM) CIOf = I/O Configuration (Flash)

CIOf = V

CIOf = V CIOs = I/O Configuration (SRAM)

CIOs = V

CIOs = V RESET# = Hardware Reset Pin, Active Low

= Word mode (x16),

= Byte mode (x8)

= Word mode (x16),

= Byte mode (x8)

LOGIC SYMBOL

A0–A18

A-1, A19–A20 SA

CE#f CE1#s

CE2s OE# WE# WP#/ACC RESET# UB#s LB#s CIOf CIOs

16 or 8

DQ0–DQ15

RY/BY#

WP#/ACC = Hardware Write Protect/

Acceleration Pin (Flash) V

f = Flash 3.0 volt-only single power sup-

ply (see Product Selector Guide for

speed options and voltage sup p ly

tolerances)

s = SRAM Power Supply

= Device Ground (Common)

NC = Pin Not Connected Internally

ORDERING INFORMATION

Valid Combination

Order Number Package Marking

DS42585 DS42585

DEVICE BUS OPERATIONS

This section describe s the requirements and use of the device bus operations, which are initiated through the internal co mmand reg ister. The comma nd regist er itself does not occupy any addressable memory location. The register is a latch used to store the commands, along with the address and data information needed to execu te th e c omm and . The c on ten ts of

the register serve as inputs to the internal state machine. The state machine outputs dictate the function of the device. Tables 1 through 3 lists the de vice bus operations, the inputs and control levels they require, and the resulting output. The following subsections describe each of these operations in further detail.

8 DS42585

PRELIMINARY

Table 1. Device Bus Operations—Flash Word Mode, CIOf = VIH; SRAM Word Mode, CIOs = VCC

Operation (Notes 1, 2)

CE#f CE1#s CE2s OE# WE# SA LB#s UB#s RESET#

Read from Flash L

Write to Flash L

Standby

0.3 V

Output Disable

Flash Hardware Reset

Sector Protect (Note 4)

Sector Unprotect (Note 4)

HX XL HX XL HX

HLH

XL HX

WP#/ACC

(Note 3)

LH X X X H L/H D

H L X X X H ( No te 3) D

XX X X X

0.3 V

DQ0– DQ7 DQ8–DQ15

OUT

HHigh-ZHigh-Z

HH X L X HH X X L

H L/H High-Z High-Z

HH X X X

X X X X X L L/H High-Z High-Z

HL X X X V

L/H D

(Note 5) D

Temporary Sector Unprotect

Read from SRAM H L H L H X

Write to SRAM H L H X L X

HX XL

XX X X X V

HL High-Z D

HX LH D LL

HL High-Z D

(Note 5) D

OUT

High-Z

OUT

High-Z

LH DINHigh-Z

Legend: L = Logic Low = VIL, H = Logic High = VIH, VID = 8.5–12.5 V, VHH = 9.0 ± 0.5 V, X = Don’t Care, SA = Sector Address,

= Address In, DIN = Data In, D

= Data Out

OUT

Notes:

1. Other operations except for those indicated in this column are inhibited.

2. Do not apply CE#f = V

3. If WP#/ACC = V If WP#/ACC = V

, CE1#s = VIL and CE2s = VIH at the same time.

, the boot sectors will be protected. If WP#/ACC = VIH the boot sectors protection will be removed.

(9V), the program time will be reduced by 40%.

ACC

4. The sector protect and sector unprotect functions may also be implemented via programming equipment. See the “Sector/Sector Block Protection and Unprotection” section.

5. If WP#/ACC = V

, the two outermost boot sectors remain protected. If WP#/ACC = VIH, the two outermost boot sector protection

depends on whether they were last protected or unprotected using the method described in “Sector/Sector Block Protection and Unprotection”. If WP#/ACC = V

all sectors will be unprotected.

HH,

DS42585 9

PRELIMINARY

Table 2. Device Bus Operations—Flash Word Mode, CIOf = V

Operation (Notes 1, 2)

CE#f CE1#s CE2s OE# WE# SA

Read from Flash L

Write to Flash L

Standby

0.3 V

Output Disable

Flash Hardware Reset

Sector Protect (Note 5)

HX XL HX XL HX

HLH

XL HX

LH X X X H L/H D

H L L X X H (Note 3) D

XX X X X

HH X L X HH X X L

HH X X X

X X X X X L L/H High-Z High-Z

HL X X X V

LB#s

(Note 3)

UB#s

(Note 3)

; SRAM Byte Mode, CIOs = VSS

WP#/ACC

(Note 4)

DQ0–DQ7 DQ8–DQ15

OUT

H High-Z High-Z

RESET#

0.3 V

H L/H High-Z High-Z

L/H D

OUT

Sector Unprotect (Note 5)

Temporary Sector Unprotect

Read from SRAM H L H L H SA X X H X D Write to SRAM H L H X L SA X X H X D

HX XL HX XL

HL X X X V

XX X X X V

(Note 6) D

OUT

High-Z

High-Z High-Z

Legend: L = Logic Low = VIL, H = Logic High = VIH, VID = 8.5–12.5 V, VHH = 9.0 ± 0.5 V, X = Don’t Care, SA = Sector Address,

= Address In, DIN = Data In, D

= Data Out

OUT

Notes:

1. Other operations except for those indicated in this column are inhibited.

2. Do not apply CE#f = V

, CE1#s = VIL and CE2s = VIH at the same time.

3. Don’t care or open LB#s or UB#s.

4. If WP#/ACC = V If WP#/ACC = V

, the boot sectors will be protected. If WP#/ACC = VIH the boot sectors protection will be removed.

(9V), the program time will be reduced by 40%.

ACC

5. The sector protect and sector unprotect functions may also be implemented via programming equipment. See the “Sector/Sector Block Protection and Unprotection” section.

6. If WP#/ACC = V

, the two outermost boot sectors remain protected. If WP#/ACC = VIH, the two outermost boot sector protection

depends on whether they were last protected or unprotected using the method described in “Sector/Sector Block Protection and Unprotection”. If WP#/AC C = V

all sectors will be unprotected.

HH,

10 DS42585

PRELIMINARY

T a ble 3. Device Bus Operations—Flash Byte Mode, CIOf = VIL; SRAM Byte Mode, CIOs = VSS

Operation (Notes 1, 2)

CE#f CE1#s CE2s

Read from Flash L

Write to Flash L

Standby

0.3 V

Output Disable

Flash Hardware Reset

Sector Protect (Note 5)

Sector Unprotect (Note 5)

DQ15/

HX XL HX XL HX

HLH

XL HX

LB#s

(Note 3)

A–1

OE#

WE# SA

A–1LH X X X H L/H D

A–1HL X X X H

XX X X X

UB#s

(Note 3)

RESET#

0.3 V

WP#/ACC

(Note 4)

(Note 3)

DQ0–DQ7 DQ8–DQ15

OUT

H High-Z High-Z

High-Z

XHHX L X HHXX X L

H L/H High-Z High-Z

A–1HH X X X

X X X X X X L L/H High-Z High-Z

HL X X X V

L/H D

(Note 6) D

Temporary Sector Unprotect

Read from SRAM

HLHXLHSAX X H X D

Write to SRAM H L H X X L SA X X H X D

Hx XL

XX X X X V

(Note 6) D

OUT

High-Z

Legend: L = Logic Low = VIL, H = Logic High = VIH, VID = 8.5–12.5 V, VHH = 9.0 ± 0.5 V, X = Don’t Care, SA = Sector Address, A

= Address In, DIN = Data In, D

= Data Out

OUT

Notes:

1. Other operations except for those indicated in this column are inhibited.

2. Do not apply CE#f = V

, CE1#s = VIL and CE2s = VIH at the same time.

3. Don’t care or open LB#s or UB#s.

4. If WP#/ACC = V If WP#/ACC = V

, the boot sectors will be protected. If WP#/ACC = VIH the boot sectors protection will be removed.

(9V), the program time will be reduced by 40%.

ACC

5. The sector protect and sector unprotect functions may also be implemented via programming equipment. See the “Sector/Sector Block Protection and Unprotection” section.

6. If WP#/ACC = V

, the two outermost boot sectors remain protected. If WP#/ACC = VIH, the two outermost boot sector protection

depends on whether they were last protected or unprotected using the method described in “Sector/Sector Block Protection and Unprotection”. If WP#/AC C = V

all sectors will be unprotected.

HH,

DS42585 11

PRELIMINARY

Word/Byte Configuration

The CIOf pin controls whether the device data I/O pins operate in the byte or word conf iguratio n. If the CIOf pin is set at lo gic ‘1’, the device is in wo rd configuration, DQ0–DQ15 are active and controlled by CE# and OE#.

If the CIOf pin is set at logic ‘0’, the device is in byte configuration, and o nly data I/O pi ns DQ0–DQ7 are active and control led by CE# and OE# . The data I/O pins DQ8–DQ14 are tri-stated, and the DQ15 pin is used as an input for the LSB (A-1) address function.

Requirements for Reading Array Data

To read array data from the outputs, the system must drive the CE#f and OE# pins to V

. CE#f is the power

control and sele cts the de vice. OE# is the outpu t control and gates array data to the output pins. WE# should remain at V

. The CIOf pin dete rmines

whether the de vice outputs a rray data in word s or bytes.

The internal state machine is set for reading array data upon device power-up, or af ter a har dware r eset. This ensures that no sp urious alteration of th e memory content occurs during the power transition. No command is necessary in this m ode to obtai n array data . Standard micropr ocessor read cycle s that asse rt valid addresses on the de vice addre ss in puts produ ce vali d data on the device data outp uts. Each bank remai ns enabled for read access until the co mmand register contents are altered.

See “Requirements for Reading Array Data” for more information. Refer to the AC Flash Read-Only Operations table for timing specifications and to Figure 14 for the timing diagram. I

in the DC Char acteristics

CC1

table represents the active current specification for reading array data.

Writing Commands/Command Sequences

To write a command or command sequence (which includes programming data to the device and erasin g sectors of memory), th e system must driv e WE# an d CE#f to V

For program operation s, the CIOf pin determines whether the device accept s program data in by tes or words. Refer to “Word/Byte Configuration” for more information.

The device features an Unlock Bypas s mode to facilitate faster programming. Once a bank enters the Unlock Bypass mode, only two write cycles are required to program a word or byte, instead of four. The “Word/Byte Configuration” section has details on programming data to the device using both standard and Unlock Bypass command sequences.

, and OE# to VIH.

An erase operation can erase one sector, multiple sectors, or the entire device. Tables 5–6 indicate the address space that each sector occupies. The device address space is divided into two banks: Bank 1 contains the boot/parameter sec tor s, and Ban k 2 co ntai ns the larger, c ode sectors of uniform size. A “bank address” is the address b its r equ ir ed t o un iqu ely s el ect a bank. Similarly, a “sector address” is the address bits required to uniquely select a sector.

in the DC Characteristics table represents the ac-

CC2

tive current specification for the write mode. The AC Characteristics section contains timing specification tables and timing diagrams for write operations.

Accelerated Program Operation

The device offers accelerated p rogram oper ations through the ACC function. This is one of two functions provided by the WP#/ACC pin. This function is primarily intended to allow faster manufacturing throughput at the factory.

If the system asserts V

on this pin, the devic e auto-

matically enters th e aforemention ed Unlock B ypass mode, temporarily unprotects any protected sectors, and uses the h igher vo ltage on the pin to re duce th e time required for program operations. The system would use a two-cycle program command sequence as required by the Unloc k Bypass mo de. Removing

from the WP#/ACC pin returns the device to nor-

mal operation. Note that the WP#/ACC pin must not be at V

for operations other than accelerated pro-

gramming, or device damage may result. In ad dition, the WP#/ACC pin must not be left floating or unconnected; inconsistent behavior of the device may result.

Autoselect Functions

If the system writes the autoselect command sequence, the device enters the autoselect mode. The system can then read autosel ect co des from the internal register (which is separate from the memory array) on DQ7–DQ0. Standar d read cycle timings app ly in this mode. Refer to the Autoselect Mode and Autoselect Command Sequence sections for more information.

Simultaneous Read/Write Operations with Zero Latency

This device is capable of reading data from one bank of memory while programming or erasing in the other bank of memory. An erase operation may also be su spended to read from or program to another location within the same bank (except the sector being erased). Figu re 21 s hows how read and w rite cycles may be initiated for simultaneous operation with zero latency. I

CC6

and I represent the current specifications for read-while-program and read-while-erase, respectively.

in the DC Characterist ics table

CC7

12 DS42585

PRELIMINARY

Standby Mode

When the system is not reading or writing to the device, it can place the device in the standby mode. In this mode, current consumption is greatly reduced, and the outputs are placed in the high impedance state, independent of the OE# input.

The device enters th e CMOS s tandby mode when th e CE#f and RESET# pins are both held at V

± 0.3 V.

(Note that this is a more restricted voltage range than

.) If CE#f and RESET# are held at VIH, but not

within V

± 0.3 V, the device will be in the standby

mode, but the stan dby curren t will b e gr eater. The device requires standard access time (t

) for read

access when the devi ce is in either of these stand by modes, before it is ready to read data.

If the device is deselecte d during erasur e or programming, the device draws active current until the operation is completed.

in the DC Characteristics table represents the

CC3

standby current specif ic ati on.

Automatic Sleep Mode

The automatic sleep mode minimizes Flash device energy consumption. The device automati cally enables this mode w hen ad dresses remain s table for t

ACC

+ 30 ns. The aut omatic sle ep mode is in dependent o f the CE#f, WE#, and OE# control signals. Standard address access timi ngs provide new data when addresses are changed. While in sleep mode, o utput data is latc hed and always a vailable to the system.

in the DC Characteristics table represents the

CC4

automatic sleep mode current specification.

RESET#: Hardware Reset Pin

The RESET# pin provides a hardware method of resetting the device to reading array data. When th e

RESET# pin is driven low for at least a period of t

the device immediately terminates any operation in progress, tristates all output pins, and ignores all read/write commands for the duration of the RESET# pulse. The device al so resets the i nternal state machine to reading arra y data. The o peration that was interrupted should be reinitiated once the device is ready to accept another command sequence, to ensure data integrity.

Current is reduced for the duration of the RESET# pulse. When RESET# is held at V vice draws CMOS standby current (I held at V

but not within V

± 0.3 V, the standby cur-

± 0.3 V, the de-

). If RESET# is

CC4

rent will be greater. The RESET# pin may be tied to the system reset cir-

cuitry. A system reset would thus also reset the Flash memory, enabling the system to read the boot-up firmware from the Flash memory.

If RESET# is asserted during a program or erase operation, the RY/BY# pin remains a “0” (busy) until the internal reset operation is complete, which requires a time of t

(during Embed ded Algorithm s). The

READY

system can thus monitor RY/BY# to determine whether the reset ope ratio n is co mplete . If RES ET# is asserted when a program or erase operation is not executing (RY/ BY# pin is “1”), the reset operation is completed within a time of t ded Algorithms). The system can read data t the RESET# pin returns to V

(not during Embed-

READY

after

Refer to the AC Characteristics tables for RESET# parameters and to Figure 15 for the timing diagram.

Output Disable Mode

When the OE# input is at VIH, output from the device is disabled. The output pins are placed in the high impedance state.

Device

Part Number

Am29DL324D 16 Mbit

Megabits Sector Sizes Megabits Sector Sizes

Table 4. Device Bank Division

Bank 1 Bank 2

Eight 8 Kbyte/4 Kword,

thirty-one 64 Kbyte/32 Kword

16 Mbit

DS42585 13

Thirty-two

64 Kbyte/32 Kword

PRELIMINARY

Table 5. Sector Addresses for Bottom Boot Sector Devices

Am29DL324DB

Bank 1

Sector

SA0 000000000 8/4 000000h–001FFFh SA1 000000001 8/4 002000h–003FFFh SA2 000000010 8/4 004000h–005FFFh SA3 000000011 8/4 006000h–007FFFh SA4 000000100 8/4 008000h–009FFFh SA5 000000101 8/4 00A000h–00BFFFh SA6 000000110 8/4 00C000h–00DFFFh SA7 000000111 8/4 00E000h–00FFFFh SA8 000001XXX 64/32 010000h–01FFFFh

SA9 000010XXX 64/32 020000h–02FFFFh SA10 000011XXX 64/32 030000h–03FFFFh SA11 000100XXX 64/32 040000h–04FFFFh SA12 000101XXX 64/32 050000h–05FFFFh SA13 000110XXX 64/32 060000h–06FFFFh SA14 000111XXX 64/32 070000h–07FFFFh SA15 001000XXX 64/32 080000h–08FFFFh SA16 001001XXX 64/32 090000h–09FFFFh SA17 001010XXX 64/32 0A0000h–0AFFFFh SA18 001011XXX 64/32 0B0000h–0BFFFFh SA19 001100XXX 64/32 0C0000h–0CFFFFh SA20 001101XXX 64/32 0D0000h–0DFFFFh SA21 001110XXX 64/32 0E0000h–0EFFFFh SA22 001111XXX 64/32 0F0000h–0FFFFFh SA23 010000XXX 64/32 100000h–10FFFFh SA24 010001XXX 64/32 110000h–11FFFFh SA25 010010XXX 64/32 120000h–12FFFFh SA26 010011XXX 64/32 130000h–13FFFFh SA27 010100XXX 64/32 140000h–14FFFFh SA28 010101XXX 64/32 150000h–15FFFFh SA29 010110XXX 64/32 160000h–16FFFFh SA30 010111XXX 64/32 170000h–17FFFFh SA31 011000XXX 64/32 180000h–18FFFFh SA32 011001XXX 64/32 190000h–19FFFFh SA33 011010XXX 64/32 1A0000h–1AFFFFh SA34 011011XXX 64/32 1B0000h–1BFFFFh SA35 011100XXX 64/32 1C0000h–1CFFFFh SA36 011101XXX 64/32 1D0000h–1DFFFFh SA37 011110XXX 64/32 1E0000h–1EFFFFh SA38 011111XXX 64/32 1F0000h–1FFFFFh

Sector Address

A20–A12

Sector Size

(Kbytes/Kwords)

(x8)

Address Range

(x16)

Address Range

000000h–000FFFh 001000h–001FFFh 002000h–002FFFh 003000h–003FFFh 004000h–004FFFh 005000h–005FFFh 006000h–006FFFh 007000h–007FFFh 008000h–00FFFFh 010000h–017FFFh 018000h–01FFFFh 020000h–027FFFh 028000h–02FFFFh 030000h–037FFFh 038000h–03FFFFh 040000h–047FFFh 048000h–04FFFFh 050000h–057FFFh 058000h–05FFFFh 060000h–067FFFh 068000h–06FFFFh 070000h–077FFFh 078000h–07FFFFh 080000h–087FFFh 088000h–08FFFFh 090000h–097FFFh

098000h–09FFFFh 0A0000h–0A7FFFh 0A8000h–0AFFFFh 0B0000h–0B7FFFh 0B8000h–0BFFFFh 0C0000h–0C7FFFh 0C8000h–0CFFFFh 0D0000h–0D7FFFh 0D8000h–0DFFFFh 0E0000h–0E7FFFh 0E8000h–0EFFFFh 0F0000h–0F7FFFh 0F8000h–0FFFFFh

14 DS42585

PRELIMINARY

Table 5. Sector Addresses for Bottom Boot Sector Devices (Continued)

Am29DL324DB

Bank 2

Sector

SA39 100000XXX 64/32 200000h–20FFFFh 100000h–107FFFh SA40 100001XXX 64/32 210000h–21FFFFh 108000h–10FFFFh SA41 100010XXX 64/32 220000h–22FFFFh 110000h–117FFFh SA42 100011XXX 64/32 230000h–23FFFFh 118000h–11FFFFh SA43 100100XXX 64/32 240000h–24FFFFh 120000h–127FFFh SA44 100101XXX 64/32 250000h–25FFFFh 128000h–12FFFFh SA45 100110XXX 64/32 260000h–26FFFFh 130000h–137FFFh SA46 100111XXX 64/32 270000h–27FFFFh 138000h–13FFFFh SA47 101000XXX 64/32 280000h–28FFFFh 140000h–147FFFh SA48 101001XXX 64/32 290000h–29FFFFh 148000h–14FFFFh SA49 101010XXX 64/32 2A0000h–2AFFFFh 150000h–157FFFh SA50 101011XXX 64/32 2B0000h–2BFFFFh 158000h–15FFFFh SA51 101100XXX 64/32 2C0000h–2CFFFFh 160000h–167FFFh SA52 101101XXX 64/32 2D0000h–2DFFFFh 168000h–16FFFFh SA53 101110XXX 64/32 2E0000h–2EFFFFh 170000h–177FFFh SA54 101111XXX 64/32 2F0000h–2FFFFFh 178000h–17FFFFh SA55 111000XXX 64/32 300000h–30FFFFh 180000h–187FFFh SA56 110001XXX 64/32 310000h–31FFFFh 188000h–18FFFFh SA57 110010XXX 64/32 320000h–32FFFFh 190000h–197FFFh SA58 110011XXX 64/32 330000h–33FFFFh 198000h–19FFFFh SA59 110100XXX 64/32 340000h–34FFFFh 1A0000h–1A7FFFh SA60 110101XXX 64/32 350000h–35FFFFh 1A8000h–1AFFFFh SA61 110110XXX 64/32 360000h–36FFFFh 1B0000h–1B7FFFh SA62 110111XXX 64/32 370000h–37FFFFh 1B8000h–1BFFFFh SA63 111000XXX 64/32 380000h–38FFFFh 1C0000h–1C7FFFh SA64 111001XXX 64/32 390000h–39FFFFh 1C8000h–1CFFFFh SA65 111010XXX 64/32 3A0000h–3AFFFFh 1D0000h–1D7FFFh SA66 111011XXX 64/32 3B0000h–3BFFFFh 1D8000h–1DFFFFh SA67 111100XXX 64/32 3C0000h–3CF FFFh 1E0000h–1E7FFFh SA68 111101XXX 64/32 3D0000h–3DF FFFh 1E8000h–1EFFFFh SA69 111110XXX 64/32 3E0000h–3EFFFFh 1F0000h–1F7FFFh SA70 111111XXX 64/32 3F0000h–3FFFFFh 1F 8000h–1FFFFFh

Sector Address

A20–A12

Sector Size

(Kbytes/Kwords)

(x8)

Address Range

(x16)

Address Range

Note: The address range is A20:A-1 in byte mode (CIOf=VIL) or A20:A0 in word mode (CIOf=VIH). The bank address bit is A20 for Am29DL324DB.

Table 6. SecSi Sector Addresses for Bottom Boot Devices

Sector Address

Device

Am29DL324DB 000000XXX 64/32 000000h–00FFFFh 00000h–07FFFh

A20–A12

Sector

Size

(x8)

Address Range

(x16)

Address Range

DS42585 15

PRELIMINARY

Autoselect Mode

The autoselect mode prov ides manufactur er and device identification, and sector protection verification, through identifier codes output on DQ7–DQ0. This mode is primarily intended for programming equipment to automatically match a device to be programmed wi th its corres ponding pr ogrammin g algorithm. However, the autoselect codes can also be accessed in-system through the command register.

To access the autoselect codes in-system, the host system can issue the autoselect command via the command register, as shown in Table 12. This method does not require V

. Refer to the Autoselect Com-

mand Sequence section for more information.

Sector/Sector Block Protec ti on and Unprotection

(Note: For the following discussi on, the term “sector” applies to both sectors and sector blocks. A sector block consists of two or more adjacent sectors that are protected or unprotected at the same time (see Table

7).

Table 7. Bottom Boot Sector/Sector Block

Addresses for Protection/Unpro tect ion

Sector A20–A12

SA70

SA69–SA67

SA66–SA63 SA62–SA59 SA58–SA55 SA54–SA51 SA50–SA47 1010XXXXX 256 (4x64) Kbytes SA46–SA43 SA42–SA39 SA38–SA35 SA34–SA31 SA30–SA27 SA26–SA23 SA22–SA19 SA18–SA15 SA14–SA11

SA10–SA8

SA7 SA6 SA5 SA4 000000100 8 Kbytes

111111XXX 64 Kbytes

111110XXX,

111101XXX,

111100XXX 1110XXXXX 256 (4x64) Kbytes 1101XXXXX 256 (4x64) Kbytes 1100XXXXX 256 (4x64) Kbytes 1011XXXXX 256 (4x64) Kbytes

1001XXXXX 256 (4x64) Kbytes 1000XXXXX 256 (4x64) Kbytes 0111XXXXX 256 (4x64) Kbytes 0110XXXXX 256 (4x64) Kbytes 0101XXXXX 256 (4x64) Kbytes 0100XXXXX 256 (4x64) Kbytes 0011XXXXX 256 (4x64) Kbytes 0010XXXXX 256 (4x64) Kbytes 0001XXXXX 256 (4x64) Kbytes 000011XXX,

000010XXX,

000001XXX

000000111 8 Kbytes 000000110 8 Kbytes

000000101 8 Kbytes

Sector/Sector Block

Size

192 (3x64) Kbytes

Sector

SA3 000000011 8 Kbytes SA2 SA1 SA0

A20–A12

000000010 8 Kbytes 000000001 8 Kbytes 000000000 8 Kbytes

Sector/Sector Block

Size

The hardware sector protection feature disables both program and erase operations in any sector. The hardware sector unpr otection feature re- enables both program and erase operations in previously protected sectors. Note th at the sect or unprote ct algorit hm unprotects all sectors in par allel. All previously protected sectors must be individually re-protected. To change data in protected sect ors efficiently, the temporary sector un protect function is available. See “Temporary Sector/Sector Bloc k Unpr ote ct ”.

Sector protectio n and unprotection ca n be implemented as follows.

Sector protection and unprotection r e qui re s V

on the

RESET# pin only, and can be implemented either in-system or via programming equipment. Figure 2 shows the algorithms and Figure 26 shows the timing diagram. This method uses standard m icroprocess or bus cycle timing. Fo r sector unpr otect, all unprotecte d sectors must first be protected prior to the first sector unprotect write cycle.

The device is shipped with all sectors unprotected. It is possible to determine whether a secto r is pro-

tected or unprotected. See the Autoselect Mode section for details.

Write Protect (WP#)

The Write Protect function provides a hardware method of protecting certai n boot sectors without using V WP#/ACC pin.

If the system asserts V vice disables program and erase functions in the two “outermost” 8 Kbyte b oot sectors indep endently of whether those sectors were protected or unprotected using the method described in “Sector/Sector Block Protection and Unprotection”. The two outermost 8 Kbyte boot sectors are the two sectors containing the lowest addresses in the bottom-boot-configured device.

If the system asserts V vice reverts to whether the two outermost 8 Kbyte boot sectors were last set to be protected or unp rotected. That is, sector protecti on or unprotection for these tw o sectors depends on whether they were last protected or unprotected using the method desc ribed in “Sec- tor/Sector Block Protection and Unprotection”.

. This function is one of two provided by the

on the WP#/ACC pin, the de-

16 DS42585

PRELIMINARY

Note that the WP#/ACC pin must not be left floating or unconnected; incons istent be havior of the de vice may result.

Temporary Sector/Sector Block Unprotect

7). This feature allows temporary unprotection of previ-

ously protected sectors to change data in-system. The Sector Unprotect mo de is activa ted by setti ng the R ESET# pin to V formerly protected sectors can be programmed or erased by select ing t he se ctor addr esse s. Onc e V removed from the RESET# pin, all the previously protected sectors are protected again. Figure 1 shows the algorithm, and Figure 25 shows the timin g diagrams, for this feature.

(8.5 V – 12.5 V). During this mode,

START

RESET# = V

(Note 1)

Perform Erase or

Program Operations

RESET# = V

Temporary Sector

Unprotect Completed

(Note 2)

Notes:

1. All protected sectors unprotected (If WP#/ACC = V outermost boot sectors will remain protected).

2. All previously protected sectors are prote cte d once again.

Figure 1. Temporary Sector Unprotect Operation

DS42585 17

PRELIMINARY

Temporary Sector

Unprotect Mode

Increment

PLSCNT

= 25?

Yes

Device failed

Sector Protect

Algorithm

START

PLSCNT = 1

RESET# = V

Wait 1 µs

First Write

Cycle = 60h?

Set up sector

address

Sector Protect:

Write 60h to sector

address with

A6 = 0, A1 = 1,

A0 = 0

Wait 150 µs

Verify Sector

Protect: Write 40h

to sector address

with A6 = 0,

A1 = 1, A0 = 0

Read from

sector address

with A6 = 0,

A1 = 1, A0 = 0

Data = 01h?

Protect another

sector?

Remove V

from RESET#

Write reset

command

Sector Protect

complete

Yes

START

Protect all sectors:

The indicated portion

of the sector protect

Reset

PLSCNT = 1

Yes

algorithm must be

performed for all

unprotected sectors

prior to issuing the

first sector

unprotect address

Increment

PLSCNT

= 1000?

Yes

Device failed

Sector Unprotect

PLSCNT = 1

RESET# = V

Wait 1 µs

First Write

Cycle = 60h?

All sectors protected?

Set up first sector

address

Sector Unprotect:

Write 60h to sector

address with

A6 = 1, A1 = 1,

A0 = 0

Wait 15 ms

Verify Sector

Unprotect: Write

40h to sector address with

A6 = 1, A1 = 1,

A0 = 0

Read from

sector address

with A6 = 1,

A1 = 1, A0 = 0

Data = 00h?

Last sector

verified?

Remove V

from RESET#

Yes

Temporary Sector

Unprotect Mode

Set up

next sector

address

Algorithm

Write reset

command

Note: The term “sector” in the figure applies to both sectors and sector blocks.

Figure 2. In-System Sector/Sector Block Protect and Unprotect Algorithms

18 DS42585

Sector Unprotect

complete

+ 40 hidden pages