AMD DS42553 Service Manual

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DS42553

Stacked Multi-Chip Package (MCP) Flash Memory and SRAM

Am29DL323D Top Boot 32 Megabit (4 M x 8-Bit/2 M x 16-Bit) CMOS 3.0 Volt-only,
Simultaneous Operation Flash Memory and 4 Mbit (512 K x 8-Bit/ 256 K x 16-Bit) Static RAM

DISTINCTIVE CHARACTERISTICS
MCP Features

■ Power supply voltage of 2.7 to 3.3 volt

■ High performance

— 90 ns maximum access time

■ Package

— 73-Ball FBGA

■ Operating Temperature

— –25°C to +85°C

Flash Memory Features

ARCHITECTURAL ADVANTAGES

■ Simultaneous Read/Write oper at io ns

— Data can be continuously read from one bank while

executing erase/program functions in other bank

— Zero latency between read and write operations

■ Secured Silicon (SecSi) Sector: Extra 64 KByte sector

— Factory locked and identifiable: 16 bytes available for

secure, random factory Electronic Serial Number; verifiable
as factory locked through autoselect function.

— Customer lockable: Can be read, programmed, or erased

just like other sectors. Once locked, data cannot be changed

■ Zero Power Operation

— Sophisticated power management circuits reduce power

consumed during inactive periods to nearly zero

■ Top boot block

■ Manufactured on 0.23 µm process technology

■ Compatible with JEDEC standards

— Pinout and software compatible with single-power-supply

flash standard

PERFORMANCE CHARACTERISTICS

■ High performance

— Access time as fast 70 ns
— Program time: 7 µs/word typical utilizing Accelerate function

■ Ultra low power consump tion (typical values)

— 2 mA active read current at 1 MHz
— 10 mA active read current at 5 MHz
— 200 nA in standby or automatic sleep mode

■ Minimum 1 mill i on write cycl es guaranteed per sector

■ 20 Year data retention at 125°C

— Reliable operation for the life of the system

SOFTWARE FEATURES

■ Data Management Software (DMS)

— AMD-supplied software manages data programming and

erasing, enabling EEPROM emulation

— Eases sector erase limitations

■ Supports Common Flash Memory Interface (CFI)

■ Erase Suspend/Erase Resume

— Suspends erase operations to allow programming in same

bank

■ Data# Polling and Toggle Bits

— Provides a software method of detecting the status of

program or erase cycles

■ Unlock Bypass Program command

— Reduces overall programming time when issuing multiple

program command sequences

HARDWARE FEATURES

■ Any combination of sectors can be erased

■ Ready/Busy# output (RY/BY#)

— Hardware method for detecting program or erase cycle

completion

■ Hardware reset pin (RESET#)

— Hardware method of resetting the internal state machine to

reading array data

■ WP#/ACC input pin

— Write protect (WP#) function allows protection of two outermost

boot sectors, regardless of sector protect status

— Acceleration (ACC) function accelerates program timing

■ Sector protection

— Hardware method of locking a sector, either in-system or

using programming equipment, to prevent any program or
erase operation within that sector

— Temporary Sector Unprotect allows changing data in

protected sectors in-system

SRAM Features

■ Power dissipation

— Operating: 50 mA maximum
— Standby: 7 µA maximum

■ CE1s# and CE2s Chip Select

■ Power down features us in g C E 1s # and CE2s

■ Data retention supply voltage: 1.5 to 3.3 volt

■ Byte data control: LB#s (DQ0–DQ7), UB#s (DQ8–DQ15)

This document contains information on a product under development at Advanced Micro Devices. The information
is intended to help you evaluate thi s product. AMD reserves t he right to chan ge or discontinue work o n this proposed
product without notice.

Refer to AMD’s Website (www.amd.com) for the latest information.

Publication# 24218 Rev: B Amendment/1
Issue Date: March 15, 2001

GENERAL DESCRIPTION
Am29DL323 Features

The Am29DL323 is a 32 megabit, 3.0 volt-only flash
memory devices, organiz ed as 2,097, 152 words of 16
bits each or 4,194,304 bytes of 8 bits each. Word
mode data appears on DQ0–DQ15; byte mode data
appears on DQ0–DQ7. The device is designed to be
programmed in-system with the standard 3.0 volt V
supply, and can also be programm ed in standard
EPROM programmers.

The device is available with an access time of 90 ns.
The device is offered in a 73-ball FBGA package.
Standard con trol pins—chip enable (CE#f), write en­able (WE#), and out put enab le (OE #)—c ontro l nor mal
read and write operations, and avoid bus contention
issues.

The device requires only a single 3.0 volt power sup-
ply for both read and write functions. Internally
generated and regulated voltag es are pr ovided for the
program and erase operations.

CC

Simultaneous Read/Write Ope rations with
Zero Latency

The Simultaneous Read/Write architecture provides
simultaneous operation by dividing the memory
space into two banks. The device can improve overall
system performance b y a llowi ng a hos t sy ste m to pr o­gram or erase in one bank, then immediately and
simultaneously read from the othe r bank, with zero la­tency. This releases the system from waiting for the
completion of program or erase operations.

The Am29DL323D has 8 M b in Bank 1 and 24 Mb in
Bank 2.

The Secured Silicon (SecSi) Sector is an extra 64
Kbit sector capable of being permanently lo cked by
AMD or customers. The SecSi Sector Indicator Bit
(DQ7) is permane ntly set to a 1 if the part is factory
locked, and set to a 0 if c ustomer lockable. This
way, customer lockable parts ca n nev er be us ed to re ­place a factory locked part.

Factory locked parts provide several options. The
SecSi Sector may store a secu re, random 16 by te
ESN (Electronic Serial Number). Customer Lockable
parts may utilize the Sec Si Sector as bonus space ,
reading and writing like any other flash sector, or may
permanently lock their own code there.

DMS (Data Management Software) allows systems
to easily take ad vantag e of the adva nced ar chitec ture

of the simultaneous read/write product line by allowing
removal of EEPROM devices. DMS will also allow the
system software to be simplified, as it will p erform all
functions necessary to modify data in file structures,
as opposed to single-byte modi fications. To write or
update a particular piece of data (a phone number or
configuration data, for example), the user only needs
to state which piece of data is to be updated, and
where the updated data is located in the system. This
is an advantage compared to systems where
user-written software must keep tr ack of the old da ta
location, status, logical to physical translation of the
data onto the Flash memory device (or m emory de­vices), and more. Using DMS, user-written software
does not need to interface with the Flash memory di­rectly. Instead, the user's software accesses t he Fl ash
memory by calling one of onl y six func tions . AMD pro­vides this software to simplify system design and
software integration efforts.

The device offers complete compatibility with the

JEDEC single-power-supply Flash command set
standard. Commands ar e written to the comman d

register using standard microprocessor write timings.
Reading data out of the device is similar to reading
from other Flash or EPROM devices.

The host system can detect whether a program or
erase operation is complete by using the device sta-
tus bits: RY/BY# pin, DQ7 (D ata# Polling) and
DQ6/DQ2 (toggle bits). After a program or erase cycle
has been completed, the device automatically returns
to reading array data.

The sector erase architecture allows memory sec­tors to be erased and reprogra mmed withou t affecting
the data contents of other sectors. The device is fully
erased when shipped from the factory.

Hardware data protection measures include a low

detector that automatically inhibits write opera-

V

CC

tions during power transitions. The hardware secto r
protection feature disables both program and erase
operations in any combination of the sectors of mem­ory. This can be achieved in-system or via
programming equipment.

The device offers two power-saving features. Whe n
addresses have been sta ble f or a spe cified am ount o f
time, the device enters the automatic sleep mode.
The system can also place the device into the
standby mode. Power consumption is greatly re­duced in both modes.

2 DS42553

TABLE OF CONTENTS

Distinctive Characteristics . . . . . . . . . . . . . . . . . . 1

MCP Features . . . . . . . . . . . . . . . . . . . . . . . . . . . .1

Flash Memory Features . . . . . . . . . . . . . . . . . . . . .1

Architectural Advantages . . . . . . . . . . . . . . . . . . .1

Performance Characteristics . . . . . . . . . . . . . . . .1

Software Features . . . . . . . . . . . . . . . . . . . . . . . .1

Hardware Features . . . . . . . . . . . . . . . . . . . . . . .1

SRAM Features . . . . . . . . . . . . . . . . . . . . . . . . . . .1

General Description. . . . . . . . . . . . . . . . . . . . . . . . 2

Am29DL323 Features . . . . . . . . . . . . . . . . . . . . . .2

Simultaneous Read/Write Operations with Zero

Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2

Product Selector Guide . . . . . . . . . . . . . . . . . . . . . 5

MCP Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . 5

Flash Memory Block Diagram. . . . . . . . . . . . . . . . 6

Connection Diagram . . . . . . . . . . . . . . . . . . . . . . . 7

Special Handling Instructions for FBGA Package .7

Pin Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Ordering Information. . . . . . . . . . . . . . . . . . . . . . . 8

Device Bus Operations . . . . . . . . . . . . . . . . . . . . . 8

Table 1. Device Bus Operations—Flash Word
Mode, CIOf = V
CIOs = V

CC

Table 2. Device Bus Operations—Flash Word
Mode, CIOf = V
CIOs = V

SS

Table 3. Device Bus Operations—Flash Byte
Mode, CIOf = V
CIOs = V

SS

Word/Byte Configuration . . . . . . . . . . . . . . . . . . . 12

Requirements for Reading Array Data . . . . . . . . .12

Writing Commands/Command Sequences . . . . .12

Accelerated Program Operation . . . . . . . . . . . .12

Autoselect Functions . . . . . . . . . . . . . . . . . . . . .12

Simultaneous Read/Write Operations with Zero

Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12

Standby Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Automatic Sleep Mode . . . . . . . . . . . . . . . . . . . . .13

RESET#: Hardware Reset Pin . . . . . . . . . . . . . . .13

Output Disable Mode . . . . . . . . . . . . . . . . . . . . . .13

Table 4. Device Bank Division . . . . . . . . . . . . . .13

Table 5. Sector Addresses for Top Boot Sector

Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14

Table 6. SecSi

Boot Devices . . . . . . . . . . . . . . . . . . . . . . . . . . .15

Autoselect Mode . . . . . . . . . . . . . . . . . . . . . . . . . 16

Sector/Sector Block Protection and Unprotection 16

Table 7. Top Boot Sector/Sector Block

Addresses for Protection/Unprotection . . . . . . .16

Write Protect (WP#) . . . . . . . . . . . . . . . . . . . . . . .16

Temporary Sector/Sector Block Unprotect . . . . . .17

Figure 1. Temporary Sector Unprotect

Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Figure 2. In-System Sector/Sec tor Blo ck

Protect and Unprotect Algorithms. . . . . . . . . . . 18

; SRAM Word Mode,

IH

. . . . . . . . . . . . . . . . . . . . . . . . . . . . .9

; SRAM Byte Mode,

IH

. . . . . . . . . . . . . . . . . . . . . . . . . . . .10

; SRAM Byte Mode,

IL

. . . . . . . . . . . . . . . . . . . . . . . . . . . .11

 Sector Addresses for Top

SecSi (Secured Silicon) Sector Flash Memory

Region . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Factory Locked: SecSi Sector Programmed

and Protected At the Factory . . . . . . . . . . . . . . 19

Customer Lockable: SecSi Sector NOT

Programmed or Protected At the Factory . . . . . 19

Hardware Data Protection . . . . . . . . . . . . . . . . . . 19

Low V

Write Inhibit . . . . . . . . . . . . . . . . . . . . 19

CC

Write Pulse “Glitch” Protection . . . . . . . . . . . . . 19

Logical Inhibit . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Power-Up Write Inhibit . . . . . . . . . . . . . . . . . . . 20

Common Flash Memory Interface (CFI) . . . . . . . 20

Table 8. CFI Query Identification String . . . . . . 20

Table 9. System Interface String . . . . . . . . . . . 21

Table 10. Device Geometry Definition . . . . . . . 21

Table 11. Primary Vendor-Specific Extended

Query . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Command Definitions. . . . . . . . . . . . . . . . . . . . . . 23

Reading Array Data . . . . . . . . . . . . . . . . . . . . . . . 23

Reset Command . . . . . . . . . . . . . . . . . . . . . . . . . 23

Autoselect Command Sequence . . . . . . . . . . . . . 23

Enter SecSi Sector/Exit SecSi Sector

Command Sequence . . . . . . . . . . . . . . . . . . . . . . 24

Byte/Word Program Command Sequence . . . . . 24

Unlock Bypass Command Sequence . . . . . . . . 24

Figure 3. Program Operation. . . . . . . . . . . . . . . 25

Chip Erase Command Sequence . . . . . . . . . . . . 25

Sector Erase Command Sequence . . . . . . . . . . . 25

Erase Suspend/Erase Resume Commands . . . . 26

Figure 4. Erase Operation . . . . . . . . . . . . . . . . . 26

Table 12. DS42553 Command Definitions . . . . 27

Write Operation Status. . . . . . . . . . . . . . . . . . . . . 28

DQ7: Data# Polling . . . . . . . . . . . . . . . . . . . . . . . 28

Figure 5. Data# Polling Algorithm . . . . . . . . . . . 28

RY/BY#: Ready/Busy# . . . . . . . . . . . . . . . . . . . . . 29

DQ6: Toggle Bit I . . . . . . . . . . . . . . . . . . . . . . . . . 29

Figure 6. Toggle Bit Algorithm. . . . . . . . . . . . . . 29

DQ2: Toggle Bit II . . . . . . . . . . . . . . . . . . . . . . . . 30

Reading Toggle Bits DQ6/DQ2 . . . . . . . . . . . . . . 30

DQ5: Exceeded Timing Limits . . . . . . . . . . . . . . . 30

DQ3: Sector Erase Timer . . . . . . . . . . . . . . . . . . 30

Table 13. Write Operation Status . . . . . . . . . . . 31

Absolute Maximum Ratings. . . . . . . . . . . . . . . . . 32

Operating Ranges. . . . . . . . . . . . . . . . . . . . . . . . . 32

Industrial (I) Devices . . . . . . . . . . . . . . . . . . . . . 32

f/VCCs Supply Voltage . . . . . . . . . . . . . . . . . 32

V

CC

DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 33

CMOS Compatible . . . . . . . . . . . . . . . . . . . . . . . 33

SRAM DC and Operating Characteristics. . . . . . 34

Zero-Power Flash . . . . . . . . . . . . . . . . . . . . . . . 35

Figure 9. I

Current vs. Time (Showing

CC1

Active and Automatic Sleep Currents). . . . . . . . 35

Figure 10. Typical I

vs. Frequency . . . . . . . . 35

CC1

Test Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Figure 11. Test Setup . . . . . . . . . . . . . . . . . . . . 36

Table 14. Test Specifications . . . . . . . . . . . . . . 36

DS42553 3

Key To Switching Waveforms. . . . . . . . . . . . . . . 36

Figure 12. Input Waveforms and

Measurement Levels . . . . . . . . . . . . . . . . . . . . 36

AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . 37

SRAM CE#s Timing . . . . . . . . . . . . . . . . . . . . . . .37

Figure 13. Timing Diagram for Alternating

Between SRAM to Flash. . . . . . . . . . . . . . . . . . 37

Flash Read-Only Operations . . . . . . . . . . . . . . . .38

Figure 14. Read Operation Timings . . . . . . . . . 38

Hardware Reset (RESET#) . . . . . . . . . . . . . . . . .39

Figure 15. Reset Timings . . . . . . . . . . . . . . . . . 39

Flash Word/Byte Configuration (CIOf) . . . . . . . . .40

Figure 16. CIOf Timings for Read Operations . 40
Figure 17. CIOf Timings for Write Operations. . 40

Flash Erase and Program Operations . . . . . . . . .41

Figure 18. Program Operation Timings. . . . . . . 42

Figure 19. Accelerated Program Timing

Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Figure 20. Chip/Sector Erase Operation

Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Figure 21. Back-to-back Read/Write Cycle

Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Figure 22. Data# Polling Timings (During

Embedded Algorithms) . . . . . . . . . . . . . . . . . . . 44

Figure 23. Toggle Bit Timings (During

Embedded Algorithms) . . . . . . . . . . . . . . . . . . . 45

Figure 24. DQ2 vs. DQ6 . . . . . . . . . . . . . . . . . . 45

Temporary Sector/Sector Block Unprotect . . . . . .46

Figure 25. Temporary Sector/Sector Block

Unprotect Timing Diagram . . . . . . . . . . . . . . . . 46

Figure 26. Sector/Sector Block Protect and

Unprotect Timing Diagram . . . . . . . . . . . . . . . . 47

Alternate CE#f Controlled Erase and Program

Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48

Figure 27. Flash Alternate CE#f Controlled

Write (Erase/Program) Operation Timings . . . . 49

SRAM Read Cycle . . . . . . . . . . . . . . . . . . . . . . . 50

Figure 28. SRAM Read Cycle—Address

Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Figure 29. SRAM Read Cycle . . . . . . . . . . . . . . 51

SRAM Write Cycle . . . . . . . . . . . . . . . . . . . . . . . . 52

Figure 30. SRAM Write Cycle—WE# Control . . 52
Figure 31. SRAM Write Cycle—CE1#s Control. 53
Figure 32. SRAM Write Cycle—UB#s and

LB#s Control . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Flash Erase And Programming Performance . . . 55

Flash Latchup Characteristics. . . . . . . . . . . . . . . 55

Package Pin Capacitance . . . . . . . . . . . . . . . . . . 55

FLASH Data Retention . . . . . . . . . . . . . . . . . . . . . 55

SRAM Data Retention. . . . . . . . . . . . . . . . . . . . . . 56

Figure 33. CE1#s Controlled Data Retention

Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Figure 34. CE2s Controlled Data Retention

Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . 57

FLB073—73-Ball Fine-Pitch Grid Array

8 x 11 mm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 58

Revision A (October 9, 2000) . . . . . . . . . . . . . . . 58

Revision B (March 8, 2001) . . . . . . . . . . . . . . . . . 58

Global . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

Flash Memory Block Diagram . . . . . . . . . . . . . . 58

Table 7, Top Boot Sector/Sector Block

Addresses for Protection/Unprotection . . . . . . . 58

Sector/Sector Block Protection/Unprotection . . 58
Customer Lockable: SecSi Sector NOT

Programmed or Protected At the Factory . . . . . 58

Common Flash Memory Interface (CFI) . . . . . . 58

Command Definitions . . . . . . . . . . . . . . . . . . . . 58

Revision B+1 (March 15, 2001) . . . . . . . . . . . . . . 58

4 DS42553

PRODUCT SELECTOR GUIDE

Part Number DS42553

Standard Voltage Range: VCC = 2.7–3.3 V Flash Memory SRAM
Max Access Time (ns) 90 85
CE# Access (ns) 90 85
OE# Access (ns) 40 45

MCP BLOCK DIAGRAM

A0 to A20

–

A

WP#/ACC

RESET#

CE#f

CIOf

LB#s

UB#s

WE#

OE#

CE1#s

CE2s

CIOs

1

SA

A0 to A20

A0 to A19

A0 to A17

VCCf

32 M Bit

Flash Memory

VCCs/V

CCQ

4 M Bit

Static RAM

V

SS

VSS/V

DQ0 to DQ15/A

SSQ

DQ0 to DQ15/A

RY/BY#

–

1

DQ0 to DQ15/A

–

1

–

1

DS42553 5

FLASH MEMORY BLOCK DIAGRAM

V

CC

V

SS

A0–A20

Upper Bank Address

Upper Bank

OE# BYTE#

Y-Decoder

A0–A20

RESET#

WE#

CE#

BYTE#

WP#/ACC

DQ0–DQ15

RY/BY#

A0–A20A0–A20

STATE

CONTROL

&
COMMAND
REGISTER

X-Decoder

Status

Control

X-Decoder

Latches and Control Logic

DQ0–DQ15

DQ0–DQ15 DQ0–DQ15

A0–A20

Lower Bank Address

Lower Bank

Y-Decoder

Latches and

Control Logic

OE# BYTE#

6 DS42553

CONNECTION DIAGRAM

73-Ball FBGA

Top View

A1

NC

B1

NC

C1

NC

F1

NC

G1

NC

D2

A3

E2

A2

F2

A1

G2

A0

H2

CE#f

C3

A7

D3

A6

E3

A5

F3

A4

G3

V

SS

H3

OE#

C4

LB#

D4

UB#

E4

A18

F4

A17

G4

DQ1

H4

DQ9

B5

NC

C5

WP#/ACC

D5

RESET#

E5

RY/BY#

H5

DQ3

B6

NC

C6

WE#

D6

CE2s

E6

A20

H6

DQ4

C7

A8

D7

A19

E7

A9

F7

A10

G7

DQ6

H7

DQ13

C8

A11

D8

A12

E8

A13

F8

A14

G8

SA

H8

DQ15/A-1

D9

A15

E9

NC

F9

NC

G9

A16

H9

CIOf

A10

NC

B10

NC

F10

NC

G10

NC

Flash only

SRAM only

Shared

J2

CE1#s

L1

NC

J3

DQ0

K3

DQ8

J4

DQ10

K4

DQ2

J5

V

CC

K5

DQ11

L5

NC

J6

V

f

CC

K6

CIOs

L6

NC

M1

NC

Special Handling Instructions for FBGA
Package

Special handling is required for Flash Memory prod­ucts in FBGA packages.

J7

s

DQ12

K7

DQ5

J8

DQ7

K8

DQ14

V

J9

SS

L10

NC

M10

NC

Flash memory dev ices in FBGA pa ckages may be
damaged if exposed to ultrasonic cleaning methods.
The package and/or data integrity may be compro­mised if the package body is exposed to temperatures
above 150

°C for prolonged periods of time.

DS42553 7

PIN DESCRIPTION

A0–A17 = 18 Address Inputs (Common)
A-1, A18–A20 = 4 Address Inputs (Flash)
SA = Highest Order Address Pin (SRAM)

Byte mode
DQ0–DQ15 = 16 Data Inpu ts /Outpu ts (Co mmo n)
CE#f = Chip Enable (Flash)
CE#s = Chip Enable (SRAM)
OE# = Output Enable (Common)
WE# = Write Enable (Common)
RY/BY# = Ready/Busy Output
UB#s = Upper Byte Control (SRAM)
LB#s = Lower Byte Control (SRAM)
CIOf = I/O Configuration (Flash)

CIOf = V

CIOf = V
CIOs = I/O Configuration (SRAM)

CIOs = V

CIOs = V
RESET# = Hardware Reset Pin, Active Low

= Word mode (x16),

IH

= Byte mode (x8)

IL

= Word mode (x16),

IH

= Byte mode (x8)

IL

LOGIC SYMBOL

18

A0–A17

A-1, A18–A20
SA

CE#f
CE1#s

CE2s
OE#
WE#
WP#/ACC
RESET#
UB#s
LB#s
CIOf
CIOs

16 or 8

DQ0–DQ15

RY/BY#

WP#/ACC = Hardware Write Protect/

Acceleration Pin (Flash)
V

f = Flash 3.0 volt-only single power sup-

CC

ply (see Product Selector Guide for

speed options and voltage sup p ly

tolerances)

s = SRAM Power Supply

V

CC

V

SS

= Device Ground (Common)

NC = Pin Not Connected Internally

ORDERING INFORMATION

Valid Combination

Order Number Package Marking

DS42553 DS42553

DEVICE BUS OPERATIONS

This section describe s the requirements and use of
the device bus operations, which are initiated through
the internal co mmand reg ister. The comma nd regist er
itself does not occupy any addressable memory loca­tion. The register is a latch used to store the
commands, along with the address and data informa­tion needed to execu te th e c omm and . The c on ten ts of

the register serve as inputs to the internal state ma­chine. The state machine outputs dictate the function
of the device. Tables 1 through 3 lists the de vice bus
operations, the inputs and control levels they require,
and the resulting output. The following subsections de­scribe each of these operations in further detail.

8 DS42553

Table 1. Device Bus Operations—Flash Word Mode, CIOf = VIH; SRAM Word Mode, CIOs = VCC

Operation
(Notes 1, 2)

CE#f CE1#s CE2s OE# WE# SA LB#s UB#s RESET#

Read from Flash L

Write to Flash L

Standby

V

0.3 V

Output Disable

Flash Hardware
Reset

Sector Protect
(Note 4)

Sector Unprotect
(Note 4)

HX
XL
HX
XL
HX

±

CC

XL

HLH

HX

L

XL
HX

X

XL
HX

L

XL
HX

L

XL

WP#/ACC

(Note 3)

LH X X X H L/H D

H L X X X H ( No te 3) D

±

V

XX X X X

CC

0.3 V

DQ0– DQ7 DQ8–DQ15

OUT

IN

D

OUT

D

IN

HHigh-ZHigh-Z

HH X L X
HH X X L

H L/H High-Z High-Z

HH X X X

X X X X X L L/H High-Z High-Z

HL X X X V

HL X X X V

ID

ID

L/H D

(Note 5) D

IN

IN

X

X

Temporary Sector
Unprotect

X

Read from SRAM H L H L H X

Write to SRAM H L H X L X

HX
XL

XX X X X V

ID

LL

HL High-Z D

HX
LH D
LL

HL High-Z D

HX

(Note 5) D

D

D

IN

OUT

OUT

IN

High-Z

D

OUT

OUT

High-Z

D

IN

IN

LH DINHigh-Z

Legend: L = Logic Low = VIL, H = Logic High = VIH, VID = 8.5–12.5 V, VHH = 9.0 ± 0.5 V, X = Don’t Care, SA = Sector Address,

= Address In, DIN = Data In, D

A

IN

= Data Out

OUT

Notes:

1. Other operations except for those indicated in this column are inhibited.

2. Do not apply CE#f = V

3. If WP#/ACC = V
If WP#/ACC = V

, CE1#s = VIL and CE2s = VIH at the same time.

IL

, the boot sectors will be protected. If WP#/ACC = VIH the boot sectors protection will be removed.

IL

(9V), the program time will be reduced by 40%.

ACC

4. The sector protect and sector unprotect functions may also be implemented via programming equipment. See the “Sector/Sector
Block Protection and Unprotection” section.

5. If WP#/ACC = V

, the two outermost boot sectors remain protected. If WP#/ACC = VIH, the two outermost boot sector protection

IL

depends on whether they were last protected or unprotected using the method described in “Sector/Sector Block Protection and
Unprotection”. If WP#/ACC = V

all sectors will be unprotected.

HH,

DS42553 9

Table 2. Device Bus Operations—Flash Word Mode, CIOf = V

Operation
(Notes 1, 2)

CE#f CE1#s CE2s OE# WE# SA

Read from Flash L

Write to Flash L

V

Standby

CC

0.3 V

Output Disable

Flash Hardware
Reset

Sector Protect
(Note 5)

HX

XL

HX

XL

HX

±

XL

HLH

HX

L

XL

HX

X

XL

HX

L

XL

LH X X X H L/H D

H L L X X H (Note 3) D

XX X X X

HH X L X
HH X X L

HH X X X

X X X X X L L/H High-Z High-Z

HL X X X V

LB#s

(Note 3)

UB#s

(Note 3)

; SRAM Byte Mode, CIOs = VSS

IH

CC

±

WP#/ACC

(Note 4)

DQ0–DQ7 DQ8–DQ15

OUT

IN

H High-Z High-Z

RESET#

V

0.3 V

H L/H High-Z High-Z

ID

L/H D

IN

D

OUT

D

IN

X

Sector Unprotect
(Note 5)

Temporary Sector
Unprotect

X

Read from SRAM H L H L H SA X X H X D
Write to SRAM H L H X L SA X X H X D

L

HX

XL

HX

XL

HL X X X V

XX X X X V

ID

ID

(Note 6) D

(Note 6) D

IN

IN

OUT

IN

X

High-Z

High-Z
High-Z

Legend: L = Logic Low = VIL, H = Logic High = VIH, VID = 8.5–12.5 V, VHH = 9.0 ± 0.5 V, X = Don’t Care, SA = Sector Address,

= Address In, DIN = Data In, D

A

IN

= Data Out

OUT

Notes:

1. Other operations except for those indicated in this column are inhibited.

2. Do not apply CE#f = V

, CE1#s = VIL and CE2s = VIH at the same time.

IL

3. Don’t care or open LB#s or UB#s.

4. If WP#/ACC = V
If WP#/ACC = V

, the boot sectors will be protected. If WP#/ACC = VIH the boot sectors protection will be removed.

IL

(9V), the program time will be reduced by 40%.

ACC

5. The sector protect and sector unprotect functions may also be implemented via programming equipment. See the “Sector/Sector
Block Protection and Unprotection” section.

6. If WP#/ACC = V

, the two outermost boot sectors remain protected. If WP#/ACC = VIH, the two outermost boot sector protection

IL

depends on whether they were last protected or unprotected using the method described in “Sector/Sector Block Protection and
Unprotection”. If WP#/AC C = V

all sectors will be unprotected.

HH,

10 DS42553

T a ble 3. Device Bus Operations—Flash Byte Mode, CIOf = VIL; SRAM Byte Mode, CIOs = VSS

Operation
(Notes 1, 2 )

CE#f CE1#s CE2s

Read from Flash L

Write to Flash L

V

Standby

CC

0.3 V

Output Disable

Flash Hardware
Reset

Sector Protect
(Note 5)

Sector Unprotect
(Note 5)

DQ15/

HX
XL
HX
XL
HX

±

XL

HLH

HX

L

XL
HX

X

XL
HX

L

XL
HX

L

XL

LB#s

(Note 3)

A–1

OE#

WE# SA

A–1LH X X X H L/H D

A–1HL X X X H

XX X X X

UB#s

(Note 3)

RESET#

±

V

CC

0.3 V

WP#/ACC

(Note 4)

(Note 3)

DQ0–DQ7 DQ8–DQ15

OUT

D

IN

H High-Z High-Z

High-Z

High-Z

XHHX L X
HHXX X L

H L/H High-Z High-Z

A–1HH X X X

X X X X X X L L/H High-Z High-Z

HL X X X V

HL X X X V

ID

ID

L/H D

(Note 6) D

IN

IN

X

X

Temporary
Sector Unprotect

Read from
SRAM

X

HLHXLHSAX X H X D

Write to SRAM H L H X X L SA X X H X D

Hx
XL

XX X X X V

ID

(Note 6) D

IN

OUT

IN

High-Z

High-Z

High-Z

Legend: L = Logic Low = VIL, H = Logic High = VIH, VID = 8.5–12.5 V, VHH = 9.0 ± 0.5 V, X = Don’t Care, SA = Sector Address,
A

= Address In, DIN = Data In, D

IN

= Data Out

OUT

Notes:

1. Other operations except for those indicated in this column are inhibited.

2. Do not apply CE#f = V

, CE1#s = VIL and CE2s = VIH at the same time.

IL

3. Don’t care or open LB#s or UB#s.

4. If WP#/ACC = V
If WP#/ACC = V

, the boot sectors will be protected. If WP#/ACC = VIH the boot sectors protection will be removed.

IL

(9V), the program time will be reduced by 40%.

ACC

5. The sector protect and sector unprotect functions may also be implemented via programming equipment. See the “Sector/Sector
Block Protection and Unprotection” section.

6. If WP#/ACC = V

, the two outermost boot sectors remain protected. If WP#/ACC = VIH, the two outermost boot sector protection

IL

depends on whether they were last protected or unprotected using the method described in “Sector/Sector Block Protection and
Unprotection”. If WP#/AC C = V

all sectors will be unprotected.

HH,

DS42553 11

Word/Byte Configuration

The CIOf pin controls whether the device data I/O pins
operate in the byte or word conf iguratio n. If the CIOf
pin is set at lo gic ‘1’, the device is in wor d configura­tion, DQ0–DQ15 are active and controlled by CE# and
OE#.

If the CIOf pin is set at logic ‘0’, the device is in byte
configuration, and o nly data I/O pi ns DQ0–DQ7 are
active and control led by CE# and OE# . The data I/O
pins DQ8–DQ14 are tri-stated, and the DQ15 pin is
used as an input for the LSB (A-1) address function.

Requirements for Reading Array Data

To read array data from the outputs, the system must
drive the CE#f and OE# pins to V

. CE#f is the power

IL

control and sele cts the de vice. OE# is the outpu t con­trol and gates array data to the output pins. WE#
should remain at V

. The CIOf pin dete rmines

IH

whether the de vice outputs a rray data in word s or
bytes.

The internal state machine is set for reading array data
upon device power-up, or af ter a har dware r eset. This
ensures that no sp urious alteration of th e memory
content occurs during the power transition. No com­mand is necessary in this m ode to obtai n array data .
Standard micropr ocess or read cyc les that asse rt vali d
addresses on the de vice addre ss in puts produ ce vali d
data on the device data outp uts. Each bank remai ns
enabled for read access until the co mmand register
contents are altered.

See “Requirements for Reading Array Data” for more
information. Refer to the AC Flash Read-Only Opera­tions table for timing specifications and to Figure 14 for
the timing diagram. I

in the DC Char acteristics

CC1

table represents the active current specification for
reading array data.

Writing Commands/Command Sequences

To write a command or command sequence (which in­cludes programming data to the device and erasin g
sectors of memory), th e system must driv e WE# an d
CE#f to V

For program operation s, the CIOf pin determines
whether the device accept s program data in by tes or
words. Refer to “Word/Byte Configuration” for more
information.

The device features an Unlock Bypas s mode to facil­itate faster programming. Once a bank enters the
Unlock Bypass mode, only two write cycles are re­quired to program a word or byte, instead of four. The
“Word/Byte Configuration” section has details on pro­gramming data to the device using both standard and
Unlock Bypass command sequences.

, and OE# to VIH.

IL

An erase operation can erase one sector, multiple sec­tors, or the entire device. Tables 5–6 indicate the
address space that each sector occupies. The device
address space is divided into two banks: Bank 1 con­tains the boot/parameter sec tor s, and Ban k 2 co ntai ns
the larger, c ode sectors of uniform size. A “bank ad­dress” is the address b its r equ ir ed t o un iqu ely s el ect a
bank. Similarly, a “sector address” is the address bits
required to uniquely select a sector.

in the DC Characteristics table represents the ac-

I

CC2

tive current specification for the write mode. The AC
Characteristics section contains timing specification
tables and timing diagrams for write operations.

Accelerated Program Operation

The device offers accelerated p rogram oper ations
through the ACC function. This is one of two functions
provided by the WP#/ACC pin. This function is prima­rily intended to allow faster manufacturing throughput
at the factory.

If the system asserts V

on this pin, the devic e auto-

HH

matically enters th e aforemention ed Unlock B ypass
mode, temporarily unprotects any protected sectors,
and uses the h igher vo ltage on the pin to re duce th e
time required for program operations. The system
would use a two-cycle program command sequence
as required by the Unloc k Bypass mo de. Removing

from the WP#/ACC pin returns the device to nor-

V

HH

mal operation. Note that the WP#/ACC pin must not
be at V

for operations other than accelerated pro-

HH

gramming, or device damage may result. In ad dition,
the WP#/ACC pin must not be left floating or uncon­nected; inconsistent behavior of the device may result.

Autoselect Functions

If the system writes the autoselect command se­quence, the device enters the autoselect mode. The
system can then read autosel ect co des from the inter­nal register (which is separate from the memory array)
on DQ7–DQ0. Standar d read cycle timings app ly in
this mode. Refer to the Autoselect Mode and Autose­lect Command Sequence sections for more
information.

Simultaneous Read/Write Operations with
Zero Latency

This device is capable of reading data from one bank
of memory while programming or erasing in the other
bank of memory. An erase operation may also be su s­pended to read from or program to another location
within the same bank (except the sector being
erased). Figu re 21 s hows how read and w rite cycles
may be initiated for simultaneous operation with zero
latency. I

CC6

and I
represent the current specifications for read-while-pro­gram and read-while-erase, respectively.

in the DC Characterist ics table

CC7

12 DS42553

Standby Mode

When the system is not reading or writing to the de­vice, it can place the device in the standby mode. In
this mode, current consumption is greatly reduced,
and the outputs are placed in the high impedance
state, independent of the OE# input.

The device enters th e CMOS s tandby m ode when th e
CE#f and RESET# pins are both held at V

± 0.3 V.

CC

(Note that this is a more restricted voltage range than

.) If CE#f and RESET# are held at VIH, but not

V

IH

within V

± 0.3 V, the device will be in the standby

CC

mode, but the stan dby cur ren t will b e gr eater. The de­vice requires standard access time (t

) for read

CE

access when the devi ce is in either of these stand by
modes, before it is ready to read data.

If the device is deselecte d during erasur e or program­ming, the device draws active current until the
operation is completed.

in the DC Characteristics table represents the

I

CC3

standby current specif ic ati on.

Automatic Sleep Mode

The automatic sleep mode minimizes Flash device en­ergy consumption. The device automati cally enables
this mode w hen ad dresses remain s table for t

ACC

+
30 ns. The automa tic sleep mod e is indepe ndent of
the CE#f, WE#, and OE# control signals. Standard ad­dress access timi ngs provide new data when
addresses are changed. While in sleep mode, o utput
data is latc hed and always a vailable to the system.

in the DC Characteristics table represents the

I

CC4

automatic sleep mode current specification.

RESET#: Hardware Reset Pin

The RESET# pin provides a hardware method of re­setting the device to reading array data. When th e

RESET# pin is driven low for at least a period of t

RP

the device immediately terminates any operation in
progress, tristates all output pins, and ignores all
read/write commands for the duration of the RESET#
pulse. The device al so resets the i nternal state ma­chine to reading arra y data. The o peration that was
interrupted should be reinitiated on ce the device is
ready to accept another command sequence, to en­sure data integrity.

Current is reduced for the duration of the RESET#
pulse. When RESET# is held at V
vice draws CMOS standby current (I
held at V

but not within V

IL

± 0.3 V, the standby cur-

SS

± 0.3 V, the de-

SS

). If RESET# is

CC4

rent will be greater.
The RESET# pin may be tied to the system reset cir-

cuitry. A system reset would thus also reset the Flash
memory, enabling the system to read the boot-up firm­ware from the Flash memory.

If RESET# is asserted during a program or erase op­eration, the RY/BY# pin remains a “0” (busy) until the
internal reset operation is complete, which requires a
time of t

(during Embed ded Algorithm s). The

READY

system can thus monitor RY/BY# to determine
whether the reset ope ratio n is co mplete . If RES ET# is
asserted when a program or erase operation is not ex­ecuting (RY/ BY# pin is “1”), the reset operation is
completed within a time of t
ded Algorithms). The system can read data t
the RESET# pin returns to V

(not during Embed-

READY

.

IH

RH

after

Refer to the AC Characteristics tables for RESET# pa­rameters and to Figure 15 for the timing diagram.

Output Disable Mode

When the OE# input is at VIH, output from the device is
disabled. The output pins are placed in the high
impedance state.

,

Device

Part Number

Am29DL323D 8 Mbit

Megabits Sector Sizes Megabits Sector Sizes

T a ble 4. Device Bank Division

Bank 1 Bank 2

Eight 8 Kbyte/4 Kword,

fifteen 64 Kbyte/32 Kword

24 Mbit

64 Kbyte/32 Kword

DS42553 13

Forty-eight

Table 5. Sector Addresses for Top Boot Sector Devices

Am29DL323DT

Bank 2

Sector

SA0 000000xxx 64/32 000000h–00FFFFh 000000h–07FFFh
SA1 000001xxx 64/32 010000h–01FFFFh 008000h–0FFFFh
SA2 000010xxx 64/32 020000h–02FFFFh 010000h–17FFFh
SA3 000011xxx 64/32 030000h–03FFFFh 018000h–01FFFFh
SA4 000100xxx 64/32 040000h–04FFFFh 020000h–027FFFh
SA5 000101xxx 64/32 050000h–05FFFFh 028000h–02FFFFh
SA6 000110xxx 64/32 060000h–06FFFFh 030000h–037FFFh
SA7 000111xxx 64/32 070000h–07FFFFh 038000h–03FFFFh
SA8 001000xxx 64/32 080000h–08FFFFh 040000h–047FFFh

SA9 001001xxx 64/32 090000h–09FFFFh 048000h–04FFFFh
SA10 001010xxx 64/32 0A0000h–0AFFFFh 050000h–057FFFh
SA11 001011xxx 64/32 0B0000h–0BFFFFh 058000h–05FFFFh
SA12 001100xxx 64/32 0C0000h–0CFFFFh 060000h–067FFFh
SA13 001101xxx 64/32 0D0000h–0DFFFFh 068000h–06FFFFh
SA14 001110xxx 64/32 0E0000h–0EFFFFh 070000h–077FFFh
SA15 001111xxx 64/32 0F0000h–0FFFFFh 078000h–07FFFFh
SA16 010000xxx 64/32 100000h–10FFFFh 080000h–087F FFh
SA17 010001xxx 64/32 110000h–11FFFFh 088000h–08FFFFh
SA18 010010xxx 64/32 120000h–12FFFFh 090000h–097F FFh
SA19 010011xxx 64/32 130000h–13FFFFh 098000h–09FFFFh
SA20 010100xxx 64/32 140000h–14FFFFh 0A0000h–0A7FFFh
SA21 010101xxx 64/32 150000h–15FFFFh 0A8000h–0AFFFFh
SA22 010110xxx 64/32 160000h–16FFFFh 0B0000h–0B7FFFh
SA23 010111xxx 64/32 170000h–17FFFFh 0B8000h–0BFFFFh
SA24 011000xxx 64/32 180000h–18FFFFh 0C0000h–0C7FFFh
SA25 011001xxx 64/32 190000h–19FFFFh 0C8000h–0CF F FFh
SA26 011010xxx 64/32 1A0000h–1AFFFFh 0D0000h–0D7FFFh
SA27 011011xxx 64/32 1B0000h–1BFFFFh 0D8000h–0DFFFFh
SA28 011100xxx 64/32 1C0000h–1CFFFFh 0E0000h–0E7FFFh
SA29 011101xxx 64/32 1D0000h–1DFFFFh 0E8000h–0EFFFFh
SA30 011110xxx 64/32 1E0000h–1EFFFFh 0F0 000h–0F7FFFh
SA31 011111xxx 64/32 1F0000h–1FFFFFh 0F8000h–0FFFFFh
SA32 100000xxx 64/32 200000h–20FFFFh 100000h–107F FFh
SA33 100001xxx 64/32 210000h–21FFFFh 108000h–10FFFFh
SA34 100010xxx 64/32 220000h–22FFFFh 110000h–117FFFh
SA35 100011xxx 64/32 230000h–23FFFFh 118000h–11FFFFh
SA36 100100xxx 64/32 240000h–24FFFFh 120000h–127F FFh
SA37 100101xxx 64/32 250000h–25FFFFh 128000h–12FFFFh
SA38 100110xxx 64/32 260000h–26FFFFh 130000h–137FFFh
SA39 100111xxx 64/32 270000h–27FFFFh 138000h–13FFFFh
SA40 101000xxx 64/32 280000h–28FFFFh 140000h–147F FFh
SA41 101001xxx 64/32 290000h–29FFFFh 148000h–14FFFFh
SA42 101010xxx 64/32 2A0000h–2AFFFFh 150000h–157FFFh
SA43 101011xxx 64/32 2B0000h–2BFFFFh 158000h–15FFFFh
SA44 101100xxx 64/32 2C0000h–2CFFFFh 160000h–167FFFh
SA45 101101xxx 64/32 2D0000h–2DFFFFh 168000h–16FFFFh
SA46 101110xxx 64/32 2E0000h–2EFFFFh 170000h–177FFFh
SA47 101111xxx 64/32 2F0000h–2FFFFFh 178000h–17FFFFh

Sector Address

A20–A12

Sector Size

(Kbytes/Kwords)

(x8)

Address Range

(x16)

Address Range

14 DS42553

Table 5. Sector Addresses for Top Boot Sector Devices (Continued)

Am29DL323DT

Bank 1

Sector

SA48 110000xxx 64/32 300000h–30FFFFh 180000h–187FFFh
SA49 110001xxx 64/32 310000h–31FFFFh 188000h–18FFFFh
SA50 110010xxx 64/32 320000h–32FFFFh 190000h–197FFFh
SA51 110011xxx 64/32 330000h–33FFFFh 198000h–19FFFFh
SA52 110100xxx 64/32 340000h–34FFFFh 1A0000h–1A7FFFh
SA53 110101xxx 64/32 350000h–35FFFFh 1A8000h–1AFFFFh
SA54 110110xxx 64/32 360000h–36FFFFh 1B0000h–1B7FFFh
SA55 110111xxx 64/32 370000h–37FFFFh 1B8000h–1BFFFFh
SA56 111000xxx 64/32 380000h–38FFFFh 1C0000h–1C7FFFh
SA57 111001xxx 64/32 390000h–39FFFFh 1C8000h–1CFFFFh
SA58 111010xxx 64/32 3A0000h–3AFFFFh 1D0000h–1D7FFFh
SA59 111011xxx 64/32 3B0000h–3BFFFFh 1D8000h–1DFFFFh
SA60 111100xxx 64/32 3C0000h–3CFFFFh 1E0000h–1E7F FFh
SA61 111101xxx 64/32 3D0000h–3DFFFFh 1E8000h–1EFFFFh
SA62 111110xxx 64/32 3E0000h–3EFFFFh 1F0 000h–1F7FFFh
SA63 111111000 8/4 3F0000h–3F1FFFh 1F8000h–1F8FFFh
SA64 111111001 8/4 3F2000h–3F3FFFh 1F9000h–1F9FFFh
SA65 111111010 8/4 3F4000h–3F5FFFh 1FA000h–1FAFFFh
SA66 111111011 8/4 3F6000h–3F7FFFh 1FB 000h–1FBFFFh
SA67 111111100 8/4 3F8000h–3F9FFFh 1FC000h–1FCFFFh
SA68 111111101 8/4 3FA000h–3FBFFFh 1FD000h–1FDFFFh
SA69 111111110 8/4 3FC000h–3FDFFFh 1FE000h–1FEFFFh
SA70 111111111 8/4 3FE000h–3FFFFFh 1FF000h–1FFFFFh

Sector Address

A20–A12

Sector Size

(Kbytes/Kwords)

(x8)

Address Range

(x16)

Address Range

Note: The address ran ge is A20:A-1 in byte mode (CIOf =VIL) or A20:A0 in word mode (CIOf=VIH). The bank address bits are A20
and A19 for Am29DL323DT.

Table 6. SecSi Sector Addresses for Top Boot Devices

Device

Am29DL323DT 111111xxx 64/32 3F0000h–3FFFFFh 1F8000h–1FFFFh

Sector Address

A20–A12

Sector

Size

(x8)

Address Range

(x16)

Address Range

DS42553 15

Autoselect Mode

The autoselect mode prov ides manufactur er and de­vice identification, and sector protection verification,
through identifier codes output on DQ7–DQ0. This
mode is primarily intended for programming equip­ment to automatically match a device to be
programmed wi th its corres ponding pr ogrammin g al­gorithm. However, the autoselect codes can also be
accessed in-system through the command register.

To access the autoselect codes in-system, the host
system can issue the autoselect command via the
command register, as shown in Table 12. This method
does not require V

. Refer to the Autoselect Com-

ID

mand Sequence section for more information.

Sector/Sector Block Protec ti on and
Unprotection

(Note: For the following discussi on, the term “sector”
applies to both sectors and sector blocks. A sector
block consists of two or more adjacent sectors that are
protected or unprotected at the s ame time (see Table

7).

T able 7. Top Boot Sector/Sector Block Addresses

for Protection/Unprotection

Sector A20–A12

SA0

SA1-SA3

SA4-SA7

SA8-SA11
SA12-SA15
SA16-SA19
SA20-SA23
SA24-SA27
SA28-SA31
SA32-SA35
SA36-SA39
SA40-SA43
SA44-SA47
SA48-SA51
SA52-SA55
SA56-SA59

SA60-SA62

SA63
SA64
SA65
SA66

000000XXX 64 Kbytes

000001XXX,

000010XXX

000011XXX
0001XXXXX 256 (4x64) Kbytes
0010XXXXX 256 (4x64) Kbytes
0011XXXXX 256 (4x64) Kbytes
0100XXXXX 256 (4x64) Kbytes
0101XXXXX 256 (4x64) Kbytes
0110XXXXX 256 (4x64) Kbytes
0111XXXXX 256 (4x64) Kbytes
1000XXXXX 256 (4x64) Kbytes
1001XXXXX 256 (4x64) Kbytes
1010XXXXX 256 (4x64) Kbytes
1011XXXXX 256 (4x64) Kbytes
1100XXXXX 256 (4x64) Kbytes
1101XXXXX 256 (4x64) Kbytes
1110XXXXX 256 (4x64) Kbytes
111100XXX,

111101XXX,

111110XXX

111111000 8 Kbytes
111111001 8 Kbytes
111111010 8 Kbytes
111111 011 8 Kbyt es

Sector/

Sector Block Size

192 (3x64) Kbytes

192 (4x64) Kbytes

Sector A20–A12

SA67 111111100 8 Kbytes
SA68 111111101 8 Kbytes
SA69
SA70

11111111 0 8 Kbytes
111111111 8 K bytes

Sector/

Sector Block Size

The hardware sector protection feature disables both
program and erase operations in any sector. The hard­ware sector unpr otection feature re- enables both
program and erase operations in previously protected
sectors. Note th at the sect or unprote ct algorit hm un­protects all sectors in par allel. All previously protected
sectors must be individually re-protected. To change
data in protected sect ors efficiently, the temporary
sector un protect function is available. See “Temporary
Sector/Sector Bloc k Unpr ote ct ”.

Sector protectio n and unprotection ca n be imple­mented as follows.

Sector protection and unprotection r e qui res V

on the

ID

RESET# pin only, and can be implemented either
in-system or via programming equipment. Figure 2
shows the algorithms and Figure 26 shows the timing
diagram. This method uses standard m icroprocess or
bus cycle timing. Fo r sector unpr otect, all unprotecte d
sectors must first be protected prior to the first sector
unprotect write cycle.

The device is shipped with all sectors unprotected.
It is possible to determine whether a secto r is pro-

tected or unprotected. See the Autoselect Mode
section for details.

Write Protect (WP#)

The Write Protect function provides a hardware
method of protecting certai n boot sectors without
using V
WP#/ACC pin.

If the system asserts V
vice disables program and erase functions in the two
“outermost” 8 Kbyte b oot sectors indep endently of
whether those sectors were protected or unprotected
using the method described in “Sector/Sector Block
Protection and Unprotection”. The two outermost 8
Kbyte boot sectors are the two sectors containing the
lowest addresses in the bottom-boot-configured
device.

If the system asserts V
vice reverts to whether the two outermost 8 Kbyte boot
sectors were last set to be protected or unp rotected.
That is, sector protecti on or unprotection for these tw o
sectors depends on whether they were last protected
or unprotected using the method desc ribed in “Sec-
tor/Sector Block Protection and Unprotection”.

. This function is one of two provided by the

ID

on the WP#/ACC pin, the de-

IL

on the WP#/ACC pin, the de-

IH

16 DS42553

Note that the WP#/ACC pin must not be left floating or
unconnected; incons istent be havior of the de vice may
result.

Temporary Sector/Sector Block Unprotect

(Note: For the following discussi on, the term “sector”
applies to both sectors and sector blocks. A sector
block consists of two or more adjacent sectors that are
protected or unprotected at the s ame time (see Table

7).
This feature allows temporary unprotection of previ-

ously protected sectors to change data in-system. The
Sector Unprotect mo de is activa ted by setti ng the R E­SET# pin to V
formerly protected sectors can be programmed or
erased by select ing t he se ctor addr esse s. Onc e V
removed from the RESET# pin, all the previously pro­tected sectors are protected again. Figure 1 shows the
algorithm, and Figure 25 shows the timin g diagrams,
for this feature.

(8.5 V – 12.5 V). During this mode,

ID

is

ID

START

RESET# = V

(Note 1)

Perform Erase or

Program Operations

RESET# = V

Temporary Sector

Unprotect Completed

(Note 2)

Notes:

1. All protected sectors unprotected (If WP#/ACC = V
outermost boot sectors will remain protected).

2. All previously protected sectors are prote cte d once
again.

ID

IH

,

IL

Figure 1. Temporary Sector Unprotect Operation

DS42553 17

Temporary Sector

Unprotect Mode

Increment

PLSCNT

No

PLSCNT

= 25?

Yes

Device failed

Sector Protect

Algorithm

START

PLSCNT = 1

RESET# = V

Wait 1 µs

No

First Write

Cycle = 60h?

Set up sector

address

Sector Protect:

Write 60h to sector

address with

A6 = 0, A1 = 1,

A0 = 0

Wait 150 µs

Verify Sector

Protect: Write 40h

to sector address

with A6 = 0,

A1 = 1, A0 = 0

Read from

sector address

with A6 = 0,

A1 = 1, A0 = 0

No

Data = 01h?

Protect another

sector?

Remove V

from RESET#

Write reset

command

Sector Protect

complete

Yes

Yes

No

START

Protect all sectors:

The indicated portion

of the sector protect

ID

Reset

PLSCNT = 1

Yes

ID

algorithm must be

performed for all

unprotected sectors

prior to issuing the

first sector

unprotect address

Increment

PLSCNT

No

PLSCNT

= 1000?

Yes

Device failed

Sector Unprotect

PLSCNT = 1

RESET# = V

Wait 1 µs

First Write

Cycle = 60h?

No

All sectors
protected?

Set up first sector

address

Sector Unprotect:

Write 60h to sector

address with

A6 = 1, A1 = 1,

A0 = 0

Wait 15 ms

Verify Sector

Unprotect: Write

40h to sector
address with

A6 = 1, A1 = 1,

A0 = 0

Read from

sector address

with A6 = 1,

A1 = 1, A0 = 0

No

Data = 00h?

Last sector

verified?

Remove V

from RESET#

Yes

Yes

Yes

Yes

ID

No

Temporary Sector

Unprotect Mode

Set up

next sector

address

No

ID

Algorithm

Write reset

command

Note: The term “sector” in the figure applies to both sectors and sector blocks.

Figure 2. In-System Sector/Sector Block Protect and Unprotect Algorithms

18 DS42553

Sector Unprotect

complete