AMD DS42546 Service Manual

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DS42546

Stacked Multi-Chip Package (MCP) Flash Memory and SRAM

Am29DL163D Top Boot 16 Megabit (2 M x 8-Bit/1 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash Memory and 4 Mbit (512 K x 8-Bit/ 256 K x 16-Bit) Static RAM

DISTINCTIVE CHARACTERISTICS MCP Features

■ Power supply voltage of 2.7 to 3.3 volt

■ High performance

— 85 ns maximum access time

■ Package

— 69-Ball FBGA

■ Operating Temperature

— –25°C to +85°C

Flash Memory Features

ARCHITECTURAL ADVANTAGES

■ Simultaneous Read/Write oper at io ns

— Data can be continuously read from one bank while

executing erase/program functions in other bank

— Zero latency between read and write operations

■ Secured Silicon (SecSi) Sector: Extra 64 KByte sector

— Factory locked and identifiable: 16 bytes available for

secure, random factory Electronic Serial Number; verifiable as factory locked through autoselect function.

— Customer lockable: Can be read, programmed, or erased

just like other sectors. Once locked, data cannot be changed

■ Zero Power Operation

— Sophisticated power management circuits reduce power

consumed during inactive periods to nearly zero

■ Top boot block

■ Manufactured on 0.23 µm process technology

■ Compatible with JEDEC standards

— Pinout and software compatible with single-power-supply

flash standard

PERFORMANCE CHARACTERISTICS

■ High performance

— 85 ns access time — Program time: 7 µs/word typical utilizing Accelerate function

■ Ultra low power consump tion (typical values)

— 2 mA active read current at 1 MHz — 10 mA active read current at 5 MHz — 200 nA in standby or automatic sleep mode

■ Minimum 1 mill i on write cycl es guaranteed per sector

■ 20 Year data retention at 125°C

— Reliable operation for the life of the system

SOFTWARE FEATURES

■ Data Management Software (DMS)

— AMD-supplied software manages data programming and

erasing, enabling EEPROM emulation

— Eases sector erase limitations

■ Supports Common Flash Memory Interface (CFI)

■ Erase Suspend/Erase Resume

— Suspends erase operations to allow programming in same

bank

■ Data# Polling and Toggle Bits

— Provides a software method of detecting the status of

program or erase cycles

■ Unlock Bypass Program command

— Reduces overall programming time when issuing multiple

program command sequences

HARDWARE FEATURES

■ Any combination of sectors can be erased

■ Ready/Busy# output (RY/BY#)

— Hardware method for detecting program or erase cycle

completion

■ Hardware reset pin (RESET#)

— Hardware method of resetting the internal state machine to

reading array data

■ WP#/ACC input pin

— Write protect (WP#) function allows protection of two outermost

boot sectors, regardless of sector protect status

— Acceleration (ACC) function accelerates program timing

■ Sector protection

— Hardware method of locking a sector, either in-system or

using programming equipment, to prevent any program or erase operation within that sector

— Temporary Sector Unprotect allows changing data in

protected sectors in-system

SRAM Features

■ Power dissipation

— Operating: 50 mA maximum — Standby: 7 µA maximum

■ CE1#s and CE2s Chip Select

■ Power down features us in g C E 1# s and CE2s

■ Data retention supply voltage: 1.5 to 3.3 volt

■ Byte data control: LB#s (DQ0–DQ7), UB#s (DQ8–DQ15)

This document contains information on a product under development at Advanced Micro Devices. The information is intended to help you evaluate thi s product. AMD reserves t he right to chan ge or discontinue work o n this proposed product without notice.

Refer to AMD’s Website (www.amd.com) for the latest information.

Publication# 24137 Rev: B Amendment/1 Issue Date: March 15, 2001

GENERAL DESCRIPTION Am29DL163 Features

The Am29DL163 is a 16 megabit, 3.0 volt-only flash memory device, o rganize d as 1,0 48,576 words of 16 bits each or 2,097,152 bytes of 8 bits each. Word mode data appears on DQ0–DQ15; byte mode data appears on DQ0–DQ7. The device is d esigned to be programmed in-system with the standard 3.0 volt V supply, and can also be progr ammed in standar d EPROM programmers.

The device is available with an access time of 85 ns. The device is offered in a 69-ball FBGA package. Standard con trol pins—chip enable (CE#f), write enable (WE#), and out put enab le (OE #)—c ontro l nor mal read and write operations, and avoid bus contention issues.

The device requires only a single 3.0 volt power sup- ply for both read and write functions. Internally generated and regulated voltag es are pr ovided for the program and erase operations.

Simultaneous Read/Write Ope rations with Zero Latency

The Simultaneous Read/Write architecture provides simultaneous operation by dividing the memory space into two banks. The device can improve overall system performance b y a llowi ng a hos t sy ste m to pr ogram or erase in one bank, then immediately and simultaneously read from the othe r bank, with zero latency. This releases the system from waiting for the completion of program or erase operations.

The Am29DL163D has 4 M b in Bank 1 and 12 Mb in Bank 2.

The Secured Silicon (SecSi) Sector is an extra 64 Kbit sector capable of being permanently lo cked by AMD or customers. The SecSi Sector Indicator Bit (DQ7) is permane ntly set to a 1 if the part is factory locked, and set to a 0 if c ustomer lockable. This way, customer lockable parts ca n nev er be us ed to re place a factory locked part.

Factory locked parts provide several options. The SecSi Sector may store a secu re, random 16 by te ESN (Electronic Serial Number). Customer Lockable parts may utilize the Sec Si Sector as bonus space , reading and writing like any other flash sector, or may permanently lock their own code there.

DMS (Data Management Software) allows systems to easily take ad vantag e of the adva nced ar chitec ture

of the simultaneous read/write product line by allowing removal of EEPROM devices. DMS will also allow the system software to be simplified, as it will p erform all functions necessary to modify data in file structures, as opposed to single-byte modi fications. To write or update a particular piece of data (a phone number or configuration data, for example), the user only needs to state which piece of data is to be updated, and where the updated data is located in the system. This is an advantage compared to systems where user-written software must keep tr ack of the old da ta location, status, logical to physical translation of the data onto the Flash memory device (or m emory devices), and more. Using DMS, user-written software does not need to interface with the Flash memory directly. Instead, the user's software accesses t he Fl ash memory by calling one of onl y six func tions . AMD provides this software to simplify system design and software integration efforts.

The device offers complete compatibility with the

JEDEC single-power-supply Flash command set standard. Commands ar e written to the comman d

register using standard microprocessor write timings. Reading data out of the device is similar to reading from other Flash or EPROM devices.

The host system can detect whether a program or erase operation is complete by using the device sta- tus bits: RY/BY# pin, DQ7 (D ata# Polling) and DQ6/DQ2 (toggle bits). After a program or erase cycle has been completed, the device automatically returns to reading array data.

The sector erase architecture allows memory sectors to be erased and reprogra mmed withou t affecting the data contents of other sectors. The device is fully erased when shipped from the factory.

Hardware data protection measures include a low

detector that automatically inhibits write opera-

tions during power transitions. The hardware secto r protection feature disables both program and erase operations in any combination of the sectors of memory. This can be achieved in-system or via programming equipment.

The device offers two power-saving features. Whe n addresses have been sta ble f or a spe cified am ount o f time, the device enters the automatic sleep mode. The system can also place the device into the standby mode. Power consumption is greatly reduced in both modes.

2 DS42546

TABLE OF CONTENTS

Distinctive Characteristics . . . . . . . . . . . . . . . . . . 1

MCP Features . . . . . . . . . . . . . . . . . . . . . . . . . . . .1

Flash Memory Features . . . . . . . . . . . . . . . . . . . . .1

Architectural Advantages . . . . . . . . . . . . . . . . . . 1

Performance Characteristics. . . . . . . . . . . . . . . . 1

Software Features . . . . . . . . . . . . . . . . . . . . . . . 1

Hardware Features . . . . . . . . . . . . . . . . . . . . . . . 1

SRAM Features . . . . . . . . . . . . . . . . . . . . . . . . . . .1

General Description. . . . . . . . . . . . . . . . . . . . . . . . 2

Am29DL163 Features . . . . . . . . . . . . . . . . . . . . . .2

Simultaneous Read/Write Operations with Zero

Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2

Product Selector Guide . . . . . . . . . . . . . . . . . . . . . 5

MCP Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . 5

Flash Memory Block Diagram. . . . . . . . . . . . . . . . 6

Connection Diagram . . . . . . . . . . . . . . . . . . . . . . . 7

Special Handling Instructions for FBGA Package .7

Pin Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Ordering Information. . . . . . . . . . . . . . . . . . . . . . . 8

Device Bus Operations . . . . . . . . . . . . . . . . . . . . . 8

Table 1. Device Bus Operations—Flash Word Mode, CIOf = V CIOs = V

Table 2. Device Bus Operations—Flash Word Mode, CIOf = V CIOs = V

Table 3. Device Bus Operations—Flash Byte Mode, CIOf = V CIOs = V

Word/Byte Configuration . . . . . . . . . . . . . . . . . . . 12

Requirements for Reading Array Data . . . . . . . . .12

Writing Commands/Command Sequences . . . . .12

Accelerated Program Operation . . . . . . . . . . . .12

Autoselect Functions . . . . . . . . . . . . . . . . . . . . .12

Simultaneous Read/Write Operations with Zero

Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12

Standby Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Automatic Sleep Mode . . . . . . . . . . . . . . . . . . . . .13

RESET#: Hardware Reset Pin . . . . . . . . . . . . . . .13

Output Disable Mode . . . . . . . . . . . . . . . . . . . . . .13

Table 4. Device Bank Division . . . . . . . . . . . . . .13

Table 5. Sector Addresses for Top Boot Sector

Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14

Table 6. SecSi Sector Addresses for Top

Boot Devices . . . . . . . . . . . . . . . . . . . . . . . . . . .14

Autoselect Mode . . . . . . . . . . . . . . . . . . . . . . . . . 15

Sector/Sector Block Protection and Unprotection 15

Table 7. Top Boot Sector/Sector Block

Addresses for Protection/Unprotection . . . . . . .15

Write Protect (WP#) . . . . . . . . . . . . . . . . . . . . . . .15

Temporary Sector/Sector Block Unprotect . . . . . .15

Figure 1. Temporary Sector Unprotect

Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Figure 2. In-System Sector/Sec tor Blo ck

Protect and Unprotect Algorithms. . . . . . . . . . . 17

; SRAM Word Mode,

. . . . . . . . . . . . . . . . . . . . . . . . . . . . .9

; SRAM Byte Mode,

. . . . . . . . . . . . . . . . . . . . . . . . . . . .10

; SRAM Byte Mode,

. . . . . . . . . . . . . . . . . . . . . . . . . . . .11

SecSi (Secured Silicon) Sector Flash Memory

Region . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Factory Locked: SecSi Sector Programmed

and Protected At the Factory . . . . . . . . . . . . . . 18

Customer Lockable: SecSi Sector NOT

Programmed or Protected At the Factory . . . . . 18

Hardware Data Protection . . . . . . . . . . . . . . . . . . 18

Low VCC Write Inhibit . . . . . . . . . . . . . . . . . . . . 18

Write Pulse “Glitch” Protection . . . . . . . . . . . . . 18

Logical Inhibit . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Power-Up Write Inhibit . . . . . . . . . . . . . . . . . . . 19

Common Flash Memory Interface (CFI) . . . . . . . 19

Table 8. CFI Query Identification String . . . . . . 19

Table 9. System Interface String . . . . . . . . . . . 20

Table 10. Device Geometry Definition . . . . . . . 20

Table 11. Primary Vendor-Specific Extended

Query . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Command Definitions. . . . . . . . . . . . . . . . . . . . . . 22

Reading Array Data . . . . . . . . . . . . . . . . . . . . . . . 22

Reset Command . . . . . . . . . . . . . . . . . . . . . . . . . 22

Autoselect Command Sequence . . . . . . . . . . . . . 22

Enter SecSi Sector/Exit SecSi Sector

Command Sequence . . . . . . . . . . . . . . . . . . . . . . 23

Byte/Word Program Command Sequence . . . . . 23

Unlock Bypass Command Sequence . . . . . . . . 23

Figure 3. Program Operation. . . . . . . . . . . . . . . 24

Chip Erase Command Sequence . . . . . . . . . . . . 24

Sector Erase Command Sequence . . . . . . . . . . . 24

Erase Suspend/Erase Resume Commands . . . . 25

Figure 4. Erase Operation . . . . . . . . . . . . . . . . . 25

Table 12. DS42546 Command Definitions . . . . 26

Write Operation Status. . . . . . . . . . . . . . . . . . . . . 27

DQ7: Data# Polling . . . . . . . . . . . . . . . . . . . . . . . 27

Figure 5. Data# Polling Algorithm . . . . . . . . . . . 27

RY/BY#: Ready/Busy# . . . . . . . . . . . . . . . . . . . . . 28

DQ6: Toggle Bit I . . . . . . . . . . . . . . . . . . . . . . . . . 28

Figure 6. Toggle Bit Algorithm. . . . . . . . . . . . . . 28

DQ2: Toggle Bit II . . . . . . . . . . . . . . . . . . . . . . . . 29

Reading Toggle Bits DQ6/DQ2 . . . . . . . . . . . . . . 29

DQ5: Exceeded Timing Limits . . . . . . . . . . . . . . . 29

DQ3: Sector Erase Timer . . . . . . . . . . . . . . . . . . 29

Table 13. Write Operation Status . . . . . . . . . . . 30

Absolute Maximum Ratings. . . . . . . . . . . . . . . . . 31

Operating Ranges. . . . . . . . . . . . . . . . . . . . . . . . . 31

Industrial (I) Devices . . . . . . . . . . . . . . . . . . . . . 31

f/VCCs Supply Voltage . . . . . . . . . . . . . . . . . 31

DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 32

CMOS Compatible . . . . . . . . . . . . . . . . . . . . . . . . 32

SRAM DC and Operating Characteristics. . . . . . 33

Zero-Power Flash . . . . . . . . . . . . . . . . . . . . . . . . 34

Figure 9. I

Current vs. Time (Showing

CC1

Active and Automatic Sleep Currents). . . . . . . . 34

Figure 10. Typical I

vs. Frequency . . . . . . . . 34

CC1

Test Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Figure 11. Test Setup . . . . . . . . . . . . . . . . . . . . 35

Table 14. Test Specifications . . . . . . . . . . . . . . 35

DS42546 3

Key To Switching Waveforms. . . . . . . . . . . . . . . 35

Figure 12. Input Waveforms and

Measurement Levels . . . . . . . . . . . . . . . . . . . . 35

AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . 36

SRAM CE#s Timing . . . . . . . . . . . . . . . . . . . . . . 36

Figure 13. Timing Diagram for Alternating

Between SRAM to Flash. . . . . . . . . . . . . . . . . . 36

Flash Read-Only Operations . . . . . . . . . . . . . . . 37

Figure 14. Read Operation Timings . . . . . . . . . 37

Hardware Reset (RESET#) . . . . . . . . . . . . . . . . . 38

Figure 15. Reset Timings . . . . . . . . . . . . . . . . . 38

Flash Word/Byte Configuration (CIOf) . . . . . . . . .39

Figure 16. CIOf Timings for Read Operations . 39 Figure 17. CIOf Timings for Write Operations. . 39

Flash Erase and Program Operations . . . . . . . . .40

Figure 18. Program Operation Timings. . . . . . . 41

Figure 19. Accelerated Program Timing

Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Figure 20. Chip/Sector Erase Operation

Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Figure 21. Back-to-back Read/Write Cycle

Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Figure 22. Data# Polling Timings (During

Embedded Algorithms) . . . . . . . . . . . . . . . . . . . 43

Figure 23. Toggle Bit Timings (During

Embedded Algorithms) . . . . . . . . . . . . . . . . . . . 44

Figure 24. DQ2 vs. DQ6 . . . . . . . . . . . . . . . . . . 44

Temporary Sector/Sector Block Unprotect . . . . . .45

Figure 25. Temporary Sector/Sector Block

Unprotect Timing Diagram . . . . . . . . . . . . . . . . 45

Figure 26. Sector/Sector Block Protect and

Unprotect Timing Diagram . . . . . . . . . . . . . . . . 46

Alternate CE#f Controlled Erase and Program

Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47

Figure 27. Flash Alternate CE#f Controlled

Write (Erase/Program) Operation Timings . . . . 48

SRAM Read Cycle . . . . . . . . . . . . . . . . . . . . . . . 49

Figure 28. SRAM Read Cycle—Address

Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Figure 29. SRAM Read Cycle . . . . . . . . . . . . . . 50

SRAM Write Cycle . . . . . . . . . . . . . . . . . . . . . . . . 51

Figure 30. SRAM Write Cycle—WE# Control . . 51 Figure 31. SRAM Write Cycle—CE1#s Control. 52 Figure 32. SRAM Write Cycle—UB#s and

LB#s Control . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Flash Erase And Programming Performance . . 54

Flash Latchup Characteristics. . . . . . . . . . . . . . . 54

Package Pin Capacitance . . . . . . . . . . . . . . . . . . 54

FLASH Data Retention . . . . . . . . . . . . . . . . . . . . . 54

SRAM Data Retention Characteristics . . . . . . . . 55

Figure 33. CE1#s Controlled Data Retention

Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Figure 34. CE2s Controlled Data Retention

Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . 56

FLA069—69-Ball Fine-Pitch Grid Array

8 x 11 mm. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 57

Revision A (July 10, 2000) . . . . . . . . . . . . . . . . . 57

Revision B (March 7, 2001) . . . . . . . . . . . . . . . . . 57

Global . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

Sector/Sector Block Protection/Unprotection . . 57

Common Flash Memory Interface (CFI) . . . . . . 57

Command Definitions . . . . . . . . . . . . . . . . . . . . 57

AC Characteristics—Alternate CE#f Controlled

Erase and Program Operations . . . . . . . . . . . . 57

Revision B+1 (March 15, 2001) . . . . . . . . . . . . . . 57

4 DS42546

PRODUCT SELECTOR GUIDE

Part Number DS42546

Standard Voltage Range: VCC = 2.7–3.3 V Flash Memory SRAM Max Access Time (ns) 85 85 CE# Access (ns) 85 85 OE# Access (ns) 35 45

MCP BLOCK DIAGRAM

A0 to A19

–

WP#/ACC

RESET#

CE#f

CIOf

LB#s

UB#s

WE#

OE#

CE1#s

CE2s

CIOs

A0 to A19

A0 to A17

VCCf

16 Mbit

Flash Memory

VCCs/V

CCQ

4 Mbit

Static RAM

VSS/V

DQ0 to DQ15/A

SSQ

DQ0 to DQ15/A

RY/BY#

–

DQ0 to DQ15/A

–

DS42546 5

FLASH MEMORY BLOCK DIAGRAM

V V

CC SS

A0–A19

RESET#

WE#

CE#

CIOf

WP#/ACC

DQ0–DQ15

A0–A19

RY/BY#

A0–A19A0–A19

STATE

CONTROL

& COMMAND REGISTER

Upper Bank Address

Lower Bank Address

Y-Decoder

Status

Control

Y-Decoder

Upper Bank

X-Decoder

Lower Bank

OE# CIOf

Latches and Control Logic

Latches and

Control Logic

DQ0–DQ15

DQ0–DQ15 DQ0–DQ15

6 DS42546

CONNECTION DIAGRAM

69-Ball FBGA

Top View

A1 A5 A6

NC NC NC

B3B1 B4 B5 B6 B7 B8

C2 C3 C4 C5 C6 C7 C8 C9

A3 D2 D3 D4 D5 D6 D7 D8 D9 A2

F1 F10F3 F4F2 F7 F8 F9

E2 E3 E4 E7 E8 E9 A1 A4 A17 A10 A14 NC

G2 G3 G4 G5 G6 G7 G8 G9

CE#f

H2 H3 H4 H5 H6 H7 H8

CE1#s

A6 UB#s RESET# CE2s A19 A12 A15

A5 A18 RY/BY# NC A9 A13 NC

OE# DQ9 DQ3 DQ4 DQ13 DQ15/A

DQ0

DQ8

LB#s WP#/ACC WE# A8 A11

DQ1A0 DQ6 SA A16

DQ10

DQ2

DQ11

CIOs

DQ12 DQ7 V

DQ5

DQ14

1 CIOf

A10

Flash only

SRAM only

Shared

E10

K1 K5 K6

NC NC NC

Special Handling Instructions for FBGA Package

Special handling is required for Flash Memory products in FBGA packages.

K10

Flash memory dev ices in FBGA pa ckages may be damaged if exposed to ultrasonic cleaning methods. The package and/or data integrity may be compromised if the package body is exposed to temperatures above 150

°C for prolonged periods of time.

DS42546 7

PIN DESCRIPTION

A0–A17 = 18 Address Inputs (Common) A–1, A18–A19 = 3 Address Inputs (Flash) SA = Highest Order Address Input

(SRAM) Byte mode DQ0–DQ15 = 16 Data Inputs/Outputs (Common) CE#f = Chip Enable (Flash) CE#s = Chip Enable (SRAM) OE# = Output Enable (Common) WE# = Write Enable (Common) RY/BY# = Ready/Busy Output UB#s = Upper Byte Control (SRAM) LB#s = Lower Byte Control (SRAM) CIOf = I/O Configuration (Flash)

CIOf = V

CIOf = V CIOs = I/O Configuration (SRAM)

CIOs = V

CIOs = V RESET# = Hardware Reset Pin, Active Low

= Word mode (x16),

= Byte mode (x8)

= Word mode (x16),

= Byte mode (x8)

LOGIC SYMBOL

A0–A17

A–1, A18–A19 SA

CE#f CE1#s

CE2s OE# WE# WP#/ACC RESET# UB#s LB#s CIOf CIOs

16 or 8

DQ0–DQ15

RY/BY#

WP#/ACC = Hardware Write Protect/

Acceleration Pin (Flash) V

f = Flash 3.0 volt-only single power sup-

ply (see Product Selector Guide for

speed options and voltage sup p ly

tolerances)

s = SRAM Power Supply

= Device Ground (Common)

NC = Pin Not Connected Internally

ORDERING INFORMATION

Valid Combination

Order Number Package Marking

DS42546 DS42546

DEVICE BUS OPERATIONS

This section describe s the requirements and use of the device bus operations, which are initiated through the internal co mmand reg ister. The comma nd regist er itself does not occupy any addressable memory location. The register is a latch used to store the commands, along with the address and data information needed to execu te th e c omm and . The c on ten ts of

the register serve as inputs to the internal state machine. The state machine outputs dictate the function of the device. Tables 1 through 3 lists the de vice bus operations, the inputs and control levels they require, and the resulting output. The following subsections describe each of these operations in further detail.

8 DS42546

Table 1. Device Bus Operations—Flash Word Mode, CIOf = VIH; SRAM Word Mode, CIOs = VCC

Operation (Notes 1, 2)

CE#f CE1#s CE2s OE# WE# SA LB#s UB#s RESET#

Read from Flash L

Write to Flash L

Standby

0.3 V

Output Disable

Flash Hardware Reset

Sector Protect (Note 4)

Sector Unprotect (Note 4)

HX XL HX XL HX

HLH

XL HX

WP#/ACC

(Note 3)

LH X X X H L/H D

H L X X X H (Note 3) D

XX X X X

0.3 V

DQ0– DQ7 DQ8–DQ15

OUT

HHigh-ZHigh-Z

HH X L X HH X X L

H L/H High-Z High-Z

HH X X X

X X X X X L L/H High-Z High-Z

HL X X X V

L/H D

(Note 5) D

Temporary Sector Unprotect

Read from SRAM H L H L H X

Write to SRAM H L H X L X

HX XL

XX X X X V

HL High-Z D

HX LH D LL

HL High-Z D

(Note 5) D

OUT

High-Z

OUT

High-Z

LH DINHigh-Z

Legend: L = Logic Low = VIL, H = Logic High = VIH, VID = 8.5–12.5 V, VHH = 9.0 ± 0.5 V, X = Don’t Care, SA = Sector Address,

= Address In, DIN = Data In, D

= Data Out

OUT

Notes:

1. Other operations except for those indicated in this column are inhibited.

2. Do not apply CE#f = V

3. If WP#/ACC = V If WP#/ACC = V

, CE1#s = VIL and CE2s = VIH at the same time.

, the boot sectors will be protected. If WP#/ACC = VIH the boot sectors protection will be removed.

(9V), the program time will be reduced by 40%.

ACC

4. The sector protect and sector unprotect functions may also be implemented via programming equipment. See the “Sector/Sector Block Protection and Unprotection” section.

5. If WP#/ACC = V

, the two outermost boot sectors remain protected. If WP#/ACC = VIH, the two outermost boot sector protection

depends on whether they were last protected or unprotected using the method described in “Sector/Sector Block Protection and Unprotection”. If WP#/ACC = V

all sectors will be unprotected.

HH,

DS42546 9

Table 2. Device Bus Operations—Flash Wo rd Mode, CIOf = V

Operation (Notes 1, 2)

CE#f CE1#s CE2s OE# WE# SA

Read from Flash L

Write to Flash L

Standby

0.3 V

Output Disable

Flash Hardware Reset

Sector Protect (Note 5)

HX XL HX XL HX

HLH

XL HX

LH X X X H L/H D

H L L X X H (Note 3) D

XX X X X

HH X L X HH X X L

HH X X X

X X X X X L L/H High-Z High-Z

HL X X X V

LB#s

(Note 3)

UB#s

(Note 3)

; SRAM Byte Mode, CIOs = VSS

WP#/ACC

(Note 4)

DQ0–DQ7 DQ8–DQ15

OUT

H High-Z High-Z

RESET#

0.3 V

H L/H High-Z High-Z

L/H D

OUT

Sector Unprotect (Note 5)

Temporary Sector Unprotect

Read from SRAM H L H L H SA X X H X D Write to SRAM H L H X L SA X X H X D

HX XL HX XL

HL X X X V

XX X X X V

(Note 6) D

OUT

High-Z

High-Z High-Z

Legend: L = Logic Low = VIL, H = Logic High = VIH, VID = 8.5–12.5 V, VHH = 9.0 ± 0.5 V, X = Don’t Care, SA = Sector Address,

= Address In, DIN = Data In, D

= Data Out

OUT

Notes:

1. Other operations except for those indicated in this column are inhibited.

2. Do not apply CE#f = V

, CE1#s = VIL and CE2s = VIH at the same time.

3. Don’t care or open LB#s or UB#s.

4. If WP#/ACC = V If WP#/ACC = V

, the boot sectors will be protected. If WP#/ACC = VIH the boot sectors protection will be removed.

(9V), the program time will be reduced by 40%.

ACC

5. The sector protect and sector unprotect functions may also be implemented via programming equipment. See the “Sector/Sector Block Protection and Unprotection” section.

6. If WP#/ACC = V

, the two outermost boot sectors remain protected. If WP#/ACC = VIH, the two outermost boot sector protection

depends on whether they were last protected or unprotected using the method described in “Sector/Sector Block Protection and Unprotection”. If WP#/AC C = V

all sectors will be unprotected.

HH,

10 DS42546

T a ble 3. Device Bus Operations—Flash Byte Mode, CIOf = VIL; SRAM Byte Mode, CIOs = VSS

Operation (Notes 1, 2 )

CE#f CE1#s CE2s

Read from Flash L

Write to Flash L

Standby

0.3 V

Output Disable

Flash Hardware Reset

Sector Protect (Note 5)

Sector Unprotect (Note 5)

DQ15/

HX XL HX XL HX

HLH

XL HX

LB#s

(Note 3)

A–1

OE#

WE# SA

A–1LH X X X H L/H D

A–1HL X X X H

XX X X X

UB#s

(Note 3)

RESET#

0.3 V

WP#/ACC

(Note 4)

(Note 3)

DQ0–DQ7 DQ8–DQ15

OUT

H High-Z High-Z

High-Z

XHHX L X HHXX X L

H L/H High-Z High-Z

A–1HH X X X

X X X X X X L L/H High-Z High-Z

HL X X X V

L/H D

(Note 6) D

Temporary Sector Unprotect

Read from SRAM

Write to SRAM H L H X X L SA X X H X D

XX X X X V

HLHXLHSAX X H X D

(Note 6) D

OUT

High-Z

Legend: L = Logic Low = VIL, H = Logic High = VIH, VID = 8.5–12.5 V, VHH = 9.0 ± 0.5 V, X = Don’t Care, SA = Sector Address, A

= Address In, DIN = Data In, D

= Data Out

OUT

Notes:

1. Other operations except for those indicated in this column are inhibited.

2. Do not apply CE#f = V

, CE1#s = VIL and CE2s = VIH at the same time.

3. Don’t care or open LB#s or UB#s.

4. If WP#/ACC = V If WP#/ACC = V

, the boot sectors will be protected. If WP#/ACC = VIH the boot sectors protection will be removed.

(9V), the program time will be reduced by 40%.

ACC

5. The sector protect and sector unprotect functions may also be implemented via programming equipment. See the “Sector/Sector Block Protection and Unprotection” section.

6. If WP#/ACC = V

, the two outermost boot sectors remain protected. If WP#/ACC = VIH, the two outermost boot sector protection

depends on whether they were last protected or unprotected using the method described in “Sector/Sector Block Protection and Unprotection”. If WP#/AC C = V

all sectors will be unprotected.

HH,

DS42546 11

Word/Byte Configuration

The CIOf pin controls whether the device data I/O pins operate in the byte or word conf iguratio n. If the CIOf pin is set at lo gic ‘1’, the device is in wor d configuration, DQ0–DQ15 are active and controlled by CE# and OE#.

If the CIOf pin is set at logic ‘0’, the device is in byte configuration, and o nly data I/O pi ns DQ0–DQ7 are active and control led by CE# and OE# . The data I/O pins DQ8–DQ14 are tri-stated, and the DQ15 pin is used as an input for the LSB (A-1) address function.

Requirements for Reading Array Data

To read array data from the outputs, the system must drive the CE#f and OE# pins to V

. CE#f is the power

control and sele cts the de vice. OE# is the outpu t control and gates array data to the output pins. WE# should remain at V

. The CIOf pin dete rmines

whether the de vice outputs a rray data in word s or bytes.

The internal state machine is set for reading array data upon device power-up, or af ter a har dware r eset. This ensures that no sp urious alteration of th e memory content occurs during the power transition. No command is necessary in this m ode to obtai n array data . Standard micropr ocess or read cyc les that asse rt vali d addresses on the de vice addre ss in puts produ ce vali d data on the device data outp uts. Each bank remai ns enabled for read access until the co mmand register contents are altered.

See “Requirements for Reading Array Data” for more information. Refer to the AC Flash Read-Only Operations table for timing specifications and to Figure 14 for the timing diagram. I

in the DC Char acteristics

CC1

table represents the active current specification for reading array data.

Writing Commands/Command Sequences

To write a command or command sequence (which includes programming data to the device and erasin g sectors of memory), th e system must driv e WE# an d CE#f to V

For program operation s, the CIOf pin determines whether the device accept s program data in by tes or words. Refer to “Word/Byte Configuration” for more information.

The device features an Unlock Bypas s mode to facilitate faster programming. Once a bank enters the Unlock Bypass mode, only two write cycles are required to program a word or byte, instead of four. The “Word/Byte Configuration” section has details on programming data to the device using both standard and Unlock Bypass command sequences.

, and OE# to VIH.

An erase operation can erase one sector, multiple sectors, or the entire device. Tables 5–6 indicate the address space that each sector occupies. The device address space is divided into two banks: Bank 1 contains the boot/parameter sec tor s, and Ban k 2 co ntai ns the larger, c ode sectors of uniform size. A “bank address” is the address b its r equ ir ed t o un iqu ely s el ect a bank. Similarly, a “sector address” is the address bits required to uniquely select a sector.

in the DC Characteristics table represents the ac-

CC2

tive current specification for the write mode. The AC Characteristics section contains timing specification tables and timing diagrams for write operations.

Accelerated Program Operation

The device offers accelerated p rogram oper ations through the ACC function. This is one of two functions provided by the WP#/ACC pin. This function is primarily intended to allow faster manufacturing throughput at the factory.

If the system asserts V

on this pin, the devic e auto-

matically enters th e aforemention ed Unlock B ypass mode, temporarily unprotects any protected sectors, and uses the h igher vo ltage on the pin to re duce th e time required for program operations. The system would use a two-cycle program command sequence as required by the Unloc k Bypass mo de. Removing

from the WP#/ACC pin returns the device to nor-

mal operation. Note that the WP#/ACC pin must not be at V

for operations other than accelerated pro-

gramming, or device damage may result. In ad dition, the WP#/ACC pin must not be left floating or unconnected; inconsistent behavior of the device may result.

Autoselect Functions

If the system writes the autoselect command sequence, the device enters the autoselect mode. The system can then read autosel ect co des from the internal register (which is separate from the memory array) on DQ7–DQ0. Standar d read cycle timings app ly in this mode. Refer to the Autoselect Mode and Autoselect Command Sequence sections for more information.

Simultaneous Read/Write Operations with Zero Latency

This device is capable of reading data from one bank of memory while programming or erasing in the other bank of memory. An erase operation may also be su spended to read from or program to another location within the same bank (except the sector being erased). Figu re 21 s hows how read and w rite cycles may be initiated for simultaneous operation with zero latency. I

CC6

and I represent the current specifications for read-while-program and read-while-erase, respectively.

in the DC Characterist ics table

CC7

12 DS42546

Standby Mode

When the system is not reading or writing to the device, it can place the device in the standby mode. In this mode, current consumption is greatly reduced, and the outputs are placed in the high impedance state, independent of the OE# input.

The device enters th e CMOS s tandby m ode when th e CE#f and RESET# pins are both held at V

± 0.3 V.

(Note that this is a more restricted voltage range than

.) If CE#f and RESET# are held at VIH, but not

within V

± 0.3 V, the device will be in the standby

mode, but the stan dby cur ren t will b e gr eater. The device requires standard access time (t

) for read

access when the devi ce is in either of these stand by modes, before it is ready to read data.

If the device is deselecte d during erasur e or programming, the device draws active current until the operation is completed.

in the DC Characteristics table represents the

CC3

standby current specif ic ati on.

Automatic Sleep Mode

The automatic sleep mode minimizes Flash device energy consumption. The device automati cally enables this mode w hen ad dresses remain s table for t

ACC

+ 30 ns. The aut omatic sle ep mode is in dependent o f the CE#f, WE#, and OE# control signals. Standard address access timi ngs provide new data when addresses are changed. While in sleep mode, o utput data is latc hed and always a vailable to the system.

in the DC Characteristics table represents the

CC4

automatic sleep mode current specification.

RESET#: Hardware Reset Pin

The RESET# pin provides a hardware method of resetting the device to reading array data. When th e

RESET# pin is driven low for at least a period of t

the device immediately terminates any operation in progress, tristates all output pins, and ignores all read/write commands for the duration of the RESET# pulse. The device al so resets the i nternal state machine to reading arra y data. The o peration that was interrupted should be reinitiated on ce the device is ready to accept another command sequence, to ensure data integrity.

Current is reduced for the duration of the RESET# pulse. When RESET# is held at V vice draws CMOS standby current (I held at V

but not within V

± 0.3 V, the standby cur-

± 0.3 V, the de-

). If RESET# is

CC4

rent will be greater. The RESET# pin may be tied to the system reset cir-

cuitry. A system reset would thus also reset the Flash memory, enabling the system to read the boot-up firmware from the Flash memory.

If RESET# is asserted during a program or erase operation, the RY/BY# pin remains a “0” (busy) until the internal reset operation is complete, which requires a time of t

(during Embed ded Algorithm s). The

READY

system can thus monitor RY/BY# to determine whether the reset ope ratio n is co mplete . If RES ET# is asserted when a program or erase operation is not executing (RY/ BY# pin is “1”), the reset operation is completed within a time of t ded Algorithms). The system can read data t the RESET# pin returns to V

(not during Embed-

READY

after

Refer to the AC Characteristics tables for RESET# parameters and to Figure 15 for the timing diagram.

Output Disable Mode

When the OE# input is at VIH, output from the device is disabled. The output pins are placed in the high impedance state.

Device

Part Number

Am29DL163D 4 Mbit

Megabits Sector Sizes Megabits Sector Sizes

T a ble 4. Device Bank Division

Bank 1 Bank 2

Eight 8 Kbyte/4 Kword,

seven 64 Kbyte/32 Kword

12 Mbit

64 Kbyte/32 Kword

DS42546 13

Twenty-four

Table 5. Sector Addresses for Top Boot Sector Devices

Sector

Am29DL163DT

SA0 00000xxx 64/32 000000h-00FFFFh 00000h–07FFFh SA1 00001xxx 64/32 010000h-01FFFFh 08000h–0FFFFh SA2 00010xxx 64/32 020000h-02FFFFh 10000h–17FFFh SA3 00011xxx 64/32 030000h-03FFFFh 18000h–1FFFFh SA4 00100xxx 64/32 040000h-04FFFFh 20000h–27FFFh SA5 00101xxx 64/32 050000h-05FFFFh 28000h–2FFFFh SA6 00110xxx 64/32 060000h-06FFFFh 30000h–37FFFh SA7 00111xxx 64/32 070000h-07FFFFh 38000h–3FFFFh SA8 01000xxx 64/32 080000h-08FFFFh 40000h–47FFFh

SA9 01001xxx 64/32 090000h-09FFFFh 48000h–4FFFFh SA10 01010xxx 64/32 0A0000h-0AFFFFh 50000h–57FFFh SA11 01011xxx 64/32 0B0000h-0BFFFFh 58000h–5FFFFh

Bank 2

Bank 1

Note: The address range is A19:A-1 in byte mode (CIOf=VIL) or A19:A0 in word mode (CIOf=VIH). The bank address bits is A19 and A18 for Am29DL163DT.

SA12 01100xxx 64/32 0C0000h-0CFFFFh 60000h–67FFFh SA13 01101xxx 64/32 0D0000h-0DFFFFh 68000h–6FFFFh SA14 01110xxx 64/32 0E0000h-0EFFFFh 70000h–77FFFh SA15 01111xxx 64/32 0F0000h-0FFFFFh 78000h–7FFFFh SA16 10000xxx 64/32 100000h-10FFFFh 80000h–8 7FFFh SA17 10001xxx 64/32 110000h-11FFFFh 88000h–8FFFFh SA18 10010xxx 64/32 120000h-12FFFFh 90000h–9 7FFFh SA19 10011xxx 64/32 130000h-13FFFFh 98000h–9FFFFh SA20 10100xxx 64/32 140000h-14FFFFh A0000h–A7FFFh SA21 10101xxx 64/32 150000h-15FFFFh A8000h–AFFFFh SA22 10110xxx 64/32 160000h-16FFFFh B0000h–B7FFFh SA23 10111xxx 64/32 170000h-17FFFFh B8000h–BFFFFh SA24 11000xxx 64/32 180000h-18FFFFh C0000h–C7FFFh SA25 11001xxx 64/32 190000h-19FFFFh C8000h–CFFFFh SA26 11010xxx 64/32 1A0000h-1AFFFFh D0000h–D7FFFh SA27 11011xxx 64/32 1B0000h-1BFFFFh D8000h–DFFFFh SA28 11100xxx 64/32 1C0000h-1CFFFFh E0000h–E7FFFh SA29 11101xxx 64/32 1D0000h-1DFFFFh E8000h–EFFFFh SA30 11110xxx 64/32 1E0000h-1EFFFFh F0000h–F7FFFh SA31 11111000 8/4 1F0000h-1F1FFFh F8000h–F8FFFh SA32 11111001 8/4 1F2000h-1F3FFFh F9000h–F9FFFh SA33 11111010 8/4 1F4000h-1F5FFFh FA000h–FAFFFh SA34 11111011 8/4 1F6000h-1F7FFFh FB000h–FBFFFh SA35 11111100 8/4 1F8000h-1F9FFFh FC000h–FCFFFh SA36 11111101 8/4 1FA000h-1FBFFFh FD000h–FDFFFh SA37 11111110 8/4 1FC000h-1FDFFFh FE000h–FEFFFh SA38 11111111 8/4 1FE000h-1FFFFFh FF000h–FFFFFh

Sector Address

A19–A12

Sector Size

(Kbytes/Kwords)

(x8)

Address Range

(x16)

Address Range

T able 6. SecSi Sector Addresses for Top Boot Devices

Device

Am29DL163DT 11111XXX 64/32 1F0000h-1FFFFFh F8000h–FFFFFh

Sector Address

A19–A12

14 DS42546

Sector

Size

(x8)

Address Range

(x16)

Address Range

Autoselect Mode

The autoselect mode prov ides manufactur er and device identification, and sector protection verification, through identifier codes output on DQ7–DQ0. This mode is primarily intended for programming equipment to automatically match a device to be programmed wi th its corres ponding pr ogrammin g algorithm. However, the autoselect codes can also be accessed in-system through the command register.

To access the autoselect codes in-system, the host system can issue the autoselect command via the command register, as shown in Table 12. This method does not require V

. Refer to the Autoselect Com-

mand Sequence section for more information.

Sector/Sector Block Protec ti on and Unprotection

(Note: For the following discussi on, the term “sector” applies to both sectors and sector blocks. A sector block consists of two or more adjacent sectors that are protected or unprotected at the s ame time (see Table

7).

T able 7. Top Boot S ector/Sector Block Addresses

for Protection/Unprotection

Sector / Sector

Block A19–A12 Sector / Sector Block Size

SA0 00000XXX 64 Kbytes

SA1-SA3

SA4-SA7 001XXXXX 256 (4x64) Kbytes

SA8-SA11 010XXXXX 256 (4x64) Kbytes SA12-SA15 011XXXXX 256 (4x64) Kbytes SA16-SA19 100XXXXX 256 (4x64) Kbytes SA20-SA23 101XXXXX 256 (4x64) Kbytes SA24-SA27 110XXXXX 256 (4x64) Kbytes

SA28-SA30

SA31 11111000 8 Kbytes SA32 11111001 8 Kbytes SA33 11111010 8 Kbytes SA34 11111011 8 Kbytes SA35 11111100 8 Kbytes SA36 11111101 8 Kbytes SA37 11111110 8 Kbytes SA38 11111111 8 Kbytes

The hardware sector protection feature disables both program and erase operations in any sector. The hardware sector unprotection fe ature re-enables both program and erase operations in previously protected sectors. Sector protection and unprotection can be implemented as follows.

00001XXX, 00010XXX,

00011XXX

11100XXX, 11101XXX,

11110XXX

192 (3x64) Kbytes

Sector protection/u nprotection requires V

on the RE-

SET# pin only, and can be implemented either in-system or via programming equipment. Figure 2 shows the algorithms and Figure 26 shows the timing diagram. This method uses standard m icroprocess or bus cycle timing. Fo r sector unpr otect, all unprotecte d sectors must first be protected prior to the first sector unprotect write cycle. Note that the sector unprotect algorithm unprotects all sectors in parallel. All previously protected sectors must be individually re-protected. To change data in protected sectors efficiently, the temporary sector un protect function is available. See “Temporary Sector/Sector Block Unprotect”.

The device is shipped with all sectors unprotected. It is possible to determine whether a secto r is pro-

tected or unprotected. See the Autoselect Mode section for details.

Write Protect (WP#)

The Write Protect function provides a hardware method of protecting certai n boot sectors without using V

. This function is one of two provided by the

WP#/ACC pin. If the system asserts V

on the WP#/ACC pin, the de-

vice disables program and erase functions in the two “outermost” 8 Kbyte b oot sectors indep endently of whether those sectors were protected or unprotected using the method described in “Sector/Sector Block Protection and Unprotection”. The two outermost 8 Kbyte boot sectors are the two sectors containing the lowest addresse s in a t op-boot- config ured devi ce, or the two sectors containing the highest addresses in a top-boot-configured device.

If the system asserts V

on the WP#/ACC pin, the de-

vice reverts to whether the two outermost 8 Kbyte boot sectors were last set to be protected or unp rotected. That is, sector protecti on or unprotection for these tw o sectors depends on whether they were last protected or unprotected using the method desc ribed in “Sec- tor/Sector Block Protection and Unprotection”.

Note that the WP#/ACC pin must not be left floating or unconnected; i ncons ist ent be havior of t he devi ce ma y result.

Temporary Sector/Sector Block Unprotect

(Note: For the foll owing disc ussion, the term “sector” applies to both sectors and sector blocks. A sector block consists of two or more adjacent sectors that are protected or unprotected at the same time (see Table

7). This feature allows temporary unprotection of previ-

ously protected sectors to change data in-system. The Sector Unprotect m ode is activa ted by setti ng the RE-

DS42546 15

SET# pin to V

(8.5 V – 12.5 V). During this mode,

formerly protected sectors can be programmed or erased by select ing t he se ctor addr esse s. Onc e V

removed from the RESET# pin, all the previously protected sectors are protected again. Figure 1 shows the algorithm, and Figure 25 shows the timin g diagrams, for this feature.

START

RESET# = V

(Note 1)

Perform Erase or

Program Operations

RESET# = V

Temporary Sector

Unprotect Completed

(Note 2)

Notes:

1. All protected sectors unprotected (If WP#/ACC = V outermost boot sectors will remain protected).

2. All previously protected sectors are prote cte d once again.

Figure 1. T emporary Sector Unprotect Operation

16 DS42546

Temporary Sector

Unprotect Mode

Increment

PLSCNT

= 25?

Yes

Device failed

Sector Protect

Algorithm

START

PLSCNT = 1

RESET# = V

Wait 1 µs

First Write

Cycle = 60h?

Set up sector

address

Sector Protect:

Write 60h to sector

address with

A6 = 0, A1 = 1,

A0 = 0

Wait 150 µs

Verify Sector

Protect: Write 40h

to sector address

with A6 = 0,

A1 = 1, A0 = 0

Read from

sector address

with A6 = 0,

A1 = 1, A0 = 0

Data = 01h?

Protect another

sector?

Remove V

from RESET#

Write reset

command

Sector Protect

complete

Yes

START

Protect all sectors:

The indicated portion

of the sector protect

Reset

PLSCNT = 1

Yes

algorithm must be

performed for all

unprotected sectors

prior to issuing the

first sector

unprotect address

Increment

PLSCNT

= 1000?

Yes

Device failed

Sector Unprotect

PLSCNT = 1

RESET# = V

Wait 1 µs

First Write

Cycle = 60h?

All sectors protected?

Set up first sector

address

Sector Unprotect:

Write 60h to sector

address with

A6 = 1, A1 = 1,

A0 = 0

Wait 15 ms

Verify Sector

Unprotect: Write

40h to sector address with

A6 = 1, A1 = 1,

A0 = 0

Read from

sector address

with A6 = 1,

A1 = 1, A0 = 0

Data = 00h?

Last sector

verified?

Remove V

from RESET#

Yes

Temporary Sector

Unprotect Mode

Set up

next sector

address

Algorithm

Write reset

command

Note: The term “sector” in the figure applies to both sectors and sector blocks.

Figure 2. In-System Sector/Sector Block Protect and Unprotect Algorithms

DS42546 17

Sector Unprotect

complete

SecSi (Secured Silicon) Sector Flash Memory R egion

The SecSi (Secured Silicon) Sector feature provides a Flash memory region that enables perm anent part identification through an Electronic Serial Number (ESN). The SecSi Sector is 64 Kbytes in length, and uses a SecSi Sector Indicator Bit to indicate whether or not the SecSi Sector is locked wh en shipped from the factory. This bit is permanently set at the factory and cannot be chan ged, whic h prevents cloning of a factory locked part. This ensures th e security of the ESN once the product is shipped to the field.

AMD offers the dev ice with the Sec Si Sector ei ther factory locked or customer lockable. The factory-locked versi on is al ways p rotec ted wh en shi pped from the factory, and has the SecSi Sector Indicator Bit permanently set to a “1.” The customer-lock able version is shipped with the unprotected, allowing customers to utilize the that sector in any manner they choose. The custom er-loc kable v ersion has th e Sec Si Sector Indicator Bit permanently set to a “0.” Thus, the SecSi Sector Indic ator Bit prev ents cus tomer-loc kable devices from being used to replace devices that are factory locked.

The system accesses the SecSi Sector through a command sequence (s ee “Enter SecSi Sector/Exit SecSi Sector Comman d Seq uence ”). Afte r the system has written the Enter SecSi Sector command sequence, it may read the SecSi Sector by using the addresses normally occupied by the boot sectors. This mode of operation continues until the system issues the Exit SecSi Sector command sequence, or until power is removed from the device. On power-up, or following a hardware reset, the device reverts to sending commands to the boot sectors.

Factory Locked: SecSi Sector Programmed and Protected At the Factory

In a factory locked device, the SecSi Sector is protected when the device is shipped from the factory. The SecSi Sector ca nnot b e mod ified in any w ay. The device is available preprogrammed with a random, secure ESN only

In devices that have an ESN, the Top Boot device will have the 16-byte ESN, with the starting address of the ESN will be at the bottom of the lowest 8 Kbyte boot sector at addresses F8000h–F8007h in word mode (or 1F0000h–1F000Fh in byte mode).

Customer Lockable: SecSi Sect or NOT Programmed or Protected At the Factory

If the security feature is not requ ired, the SecSi Sector can be treated as an additional F l a s h m e m o r y s p a c e , exp an d i ng t h e s iz e of the availabl e Flash ar ray by 64 Kbytes. The SecSi Sector can be read, programmed,

and erased as often as required. Note that the accelerated programming (ACC) and unlock bypass functions are not available wh en pro gram ming t he SecS i Se cto r.

The SecSi Sector area can be protect ed using o ne of the following procedures:

■ Write the three-cycle Enter SecSi Sector Region command sequence, and the n fol low th e in-s ys te m sector protect algorithm as sho wn in Figure 2, except that RESET# may be at eith er V

or VID. This

allows in-system protection of the without raising any device pin to a high voltage. Note that this method is only applicable to the SecSi Sector.

■ Write the three-cycle Enter SecSi Sector Region command sequence, and then use the alternate method of sector protection described in the “Sec- tor/Sector Block Protection and Unprotection”.

Once the SecSi Sec tor i s locke d and v erified, t he system must write the Exit SecSi Sector Region command sequence to return to reading and writing the remainder of the array.

The SecSi Sector protection must be used with caution since, once protected, there is no procedure available for unpro tecting the SecS i Sector area an d none of the bits in th e SecSi Sect or memory space can be modified in any way.

Hardware Data Protection

The command sequence r equ irement of unlock cycles for programming or erasing provides data protection against inadverten t writes ( refer to Table 12 for command definitions). In addition, the following hardware data protection measures prevent accidental erasure or programming , which might ot herwise be cause d by spurious system level signals during V and power-down transitions, or from system noise.

Low V

When V

Write Inhibit

is less than V

, the device d oes not ac-

LKO

cept any write cycles. This protects data during V power-up and power-down. The command register and all internal program/erase circuits are disabled, and the device resets to reading array data. Subsequent writes are ignored until V

is greater than V

The system must provide the proper signa ls to the control pins to prevent unintentional writes when V is greater than V

LKO

Write Pulse “Glitch” Prote c t io n

Noise pulses of less than 5 n s (typi cal) on OE#, CE #f or WE# do not initiate a write cycle.

Logical Inhibit

Write cycles are inhibited by holding any one of OE# =

, CE#f = VIH or WE# = VIH. To initiate a write cycle,

power-up

LKO

18 DS42546

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