AMD DS42516 Service Manual

查询DS42516供应商

DS42516

Stacked Multi-Chip Package (MCP) Flash Memory and SRAM

Am29DL324D Bottom Boot 32 Megabit (4 M x 8-Bit/2 M x 16-Bit) CMOS 3.0 V o lt-only, Simultaneous Operation Flash Memory and 4 Mbit (512 K x 8-Bit/ 256 K x 16-Bit) Static RAM

DISTINCTIVE CHARACTERISTICS MCP Features

■ Power supply voltage of 2.7 to 3.3 volt

■ High performance

— 90 ns maximum access time

■ Package

— 73-Ball FBGA

■ Operating Temperature

— –25°C to +85°C

Flash Memory Features

ARCHITECTURAL ADVANTAGES

■ Simultaneous Read/Write oper at io ns

— Data can be continuously read from one bank while

executing erase/program functions in other bank

— Zero latency between read and write operations

■ Secured Silicon (SecSi) Sector: Extra 64 KByte sector

— Factory locked and identifiable: 16 bytes available for

secure, random factory Electronic Serial Number; verifiable as factory locked through autoselect function.

— Customer lockable: Can be read, programmed, or erased

just like other sectors. Once locked, data cannot be changed

■ Zero Power Operation

— Sophisticated power management circuits reduce power

consumed during inactive periods to nearly zero

■ Bottom boot block

■ Manufactured on 0.23 µm process technology

■ Compatible with JEDEC standards

— Pinout and software compatible with single-power-supply

flash standard

PERFORMANCE CHARACTERISTICS

■ High performance

— Access time as fast 70 ns — Program time: 7 µs/word typical utilizing Accelerate function

■ Ultra low power consump tion (typical values)

— 2 mA active read current at 1 MHz — 10 mA active read current at 5 MHz — 200 nA in standby or automatic sleep mode

■ Minimum 1 mill i on write cycl es guaranteed per sector

■ 20 Year data retention at 125°C

— Reliable operation for the life of the system

SOFTWARE FEATURES

■ Data Management Software (DMS)

— AMD-supplied software manages data programming and

erasing, enabling EEPROM emulation

— Eases sector erase limitations

■ Supports Common Flash Memory Interface (CFI)

■ Erase Suspend/Erase Resume

— Suspends erase operations to allow programming in same

bank

■ Data# Polling and Toggle Bits

— Provides a software method of detecting the status of

program or erase cycles

■ Unlock Bypass Program command

— Reduces overall programming time when issuing multiple

program command sequences

HARDWARE FEATURES

■ Any combination of sectors can be erased

■ Ready/Busy# output (RY/BY#)

— Hardware method for detecting program or erase cycle

completion

■ Hardware reset pin (RESET#)

— Hardware method of resetting the internal state machine to

reading array data

■ WP#/ACC input pin

— Write protect (WP#) function allows protection of two outermost

boot sectors, regardless of sector protect status

— Acceleration (ACC) function accelerates program timing

■ Sector protection

— Hardware method of locking a sector, either in-system or

using programming equipment, to prevent any program or erase operation within that sector

— Temporary Sector Unprotect allows changing data in

protected sectors in-system

SRAM Features

■ Power dissipation

— Operating: 50 mA maximum — Standby: 7 µA maximum

■ CE1s# and CE2s Chip Select

■ Power down features us in g C E 1s # and CE2s

■ Data retention supply voltage: 1.5 to 3.3 volt

■ Byte data control: LB#s (DQ0–DQ7), UB#s (DQ8–DQ15)

This document contains information on a product under development at Advanced Micro Devices. The information is intended to help you evaluate thi s product. AMD reserves t he right to chan ge or discontinue work o n this proposed product without notice.

Refer to AMD’s Website (www.amd.com) for the latest information.

Publication# 23763 Rev: B Amendment/1 Issue Date: March 15, 2001

GENERAL DESCRIPTION Am29DL324 Features

The Am2 9DL324 is a 3 2 megabit, 3.0 volt-only flash memory devices, organiz ed as 2,097, 152 words of 16 bits each or 4,194,304 bytes of 8 bits each. Word mode data appears on DQ0–DQ15; byte mode data appears on DQ0–DQ7. The device is designed to be programmed in-system with the standard 3.0 volt V supply, and can also be progr ammed in standar d EPROM programmers.

The device is available with an access time of 90 ns. The device is offered in a 73-ball FBGA package. Standard con trol pins—chip enable (CE#f), write enable (WE#), and out put enab le (OE #)—c ontro l nor mal read and write operations, and avoid bus contention issues.

The device requires only a single 3.0 volt power sup- ply for both read and write functions. Internally generated and regulated voltag es are pr ovided for the program and erase operations.

Simultaneous Read/Write Ope rations with Zero Latency

The Simultaneous Read/Write architecture provides simultaneous operation by dividing the memory space into two banks. The device can improve overall system performance b y a llowi ng a hos t sy ste m to pr ogram or erase in one bank, then immediately and simultaneously read from the othe r bank, with zero latency. This releases the system from waiting for the completion of program or erase operations.

The Am29DL324D has 16 Mb in each bank. The Secured Silicon (SecSi) Sector is an extra 64

Kbit sector capable of being permanently lo cked by AMD or customers. The SecSi Sector Indicator Bit (DQ7) is permane ntly set to a 1 if the part is factory locked, and set to a 0 if c ustomer lockable. This way, customer lockable parts ca n nev er be us ed to re place a factory locked part.

Factory locked parts provide several options. The SecSi Sector may store a secu re, random 16 by te ESN (Electronic Serial Number). Customer Lockable parts may utilize the Sec Si Sector as bonus space , reading and writing like any other flash sector, or may permanently lock their own code there.

DMS (Data Management Software) allows systems to easily take ad vantag e of the adva nced ar chitec ture of the simultaneous read/write product line by allowing

removal of EEPROM devices. DMS will also allow the system software to be simplified, as it will p erform all functions necessary to modify data in file structures, as opposed to single-byte modi fications. To write or update a particular piece of data (a phone number or configuration data, for example), the user only needs to state which piece of data is to be updated, and where the updated data is located in the system. This is an advantage compared to systems where user-written software must keep tr ack of the old da ta location, status, logical to physical translation of the data onto the Flash memory device (or m emory devices), and more. Using DMS, user-written software does not need to interface with the Flash memory directly. Instead, the user's software accesses t he Fl ash memory by calling one of onl y six func tions . AMD provides this software to simplify system design and software integration efforts.

The device offers complete compatibility with the

JEDEC single-power-supply Flash command set standard. Commands ar e written to the comman d

register using standard microprocessor write timings. Reading data out of the device is similar to reading from other Flash or EPROM devices.

The host system can detect whether a program or erase operation is complete by using the device sta- tus bits: RY/BY# pin, DQ7 (D ata# Polling) and DQ6/DQ2 (toggle bits). After a program or erase cycle has been completed, the device automatically returns to reading array data.

The sector erase architecture allows memory sectors to be erased and reprogra mmed withou t affecting the data contents of other sectors. The device is fully erased when shipped from the factory.

Hardware data protection measures include a low

detector that automatically inhibits write opera-

tions during power transitions. The hardware secto r protection feature disables both program and erase operations in any combination of the sectors of memory. This can be achieved in-system or via programming equipment.

The device offers two power-saving features. Whe n addresses have been sta ble f or a spe cified am ount o f time, the device enters the automatic sleep mode. The system can also place the device into the standby mode. Power consumption is greatly reduced in both modes.

2 DS42516

TABLE OF CONTENTS

Distinctive Characteristics . . . . . . . . . . . . . . . . . . 1

MCP Features . . . . . . . . . . . . . . . . . . . . . . . . . . . .1

Flash Memory Features . . . . . . . . . . . . . . . . . . . . .1

Architectural Advantages . . . . . . . . . . . . . . . . . . .1

Performance Characteristics . . . . . . . . . . . . . . . .1

Software Features . . . . . . . . . . . . . . . . . . . . . . . .1

Hardware Features . . . . . . . . . . . . . . . . . . . . . . .1

SRAM Features . . . . . . . . . . . . . . . . . . . . . . . . . . .1

General Description. . . . . . . . . . . . . . . . . . . . . . . . 2

Am29DL324 Features . . . . . . . . . . . . . . . . . . . . . .2

Simultaneous Read/Write Operations with

Zero Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2

Product Selector Guide . . . . . . . . . . . . . . . . . . . . . 5

MCP Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . 5

Flash Memory Block Diagram. . . . . . . . . . . . . . . . 6

Connection Diagram . . . . . . . . . . . . . . . . . . . . . . . 7

Special Handling Instructions for FBGA Package .7

Pin Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Ordering Information. . . . . . . . . . . . . . . . . . . . . . . 8

Device Bus Operations . . . . . . . . . . . . . . . . . . . . . 8

Table 1. Device Bus Operations—Flash Word Mode, CIOf = V CIOs = V

Table 2. Device Bus Operations—Flash Word Mode, CIOf = V CIOs = V

Table 3. Device Bus Operations—Flash Byte Mode, CIOf = V CIOs = V

Word/Byte Configuration . . . . . . . . . . . . . . . . . . . 12

Requirements for Reading Array Data . . . . . . . . .12

Writing Commands/Command Sequences . . . . .12

Accelerated Program Operation . . . . . . . . . . . .12

Autoselect Functions . . . . . . . . . . . . . . . . . . . . .12

Simultaneous Read/Write Operations with Zero

Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12

Standby Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Automatic Sleep Mode . . . . . . . . . . . . . . . . . . . . .13

RESET#: Hardware Reset Pin . . . . . . . . . . . . . . .13

Output Disable Mode . . . . . . . . . . . . . . . . . . . . . .13

Table 4. Device Bank Division . . . . . . . . . . . . . .13

Table 5. Sector Addresses for Bottom Boot

Sector Devices . . . . . . . . . . . . . . . . . . . . . . . . . .14

Table 6. SecSi Sector Addresses for Bottom

Boot Devices . . . . . . . . . . . . . . . . . . . . . . . . . . .15

Autoselect Mode . . . . . . . . . . . . . . . . . . . . . . . . . 16

Sector/Sector Block Protection and Unprotection 16

Table 7. Bottom Boot Sector/Sector Block

Addresses for Protection/Unprotection . . . . . . .16

Write Protect (WP#) . . . . . . . . . . . . . . . . . . . . . . .16

Temporary Sector/Sector Block Unprotect . . . . . .17

Figure 1. Temporary Sector Unprotect

Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Figure 2. In-System Sector/Sec tor Blo ck

Protect and Unprotect Algorithms. . . . . . . . . . . 18

; SRAM Word Mode,

. . . . . . . . . . . . . . . . . . . . . . . . . . . . .9

; SRAM Byte Mode,

. . . . . . . . . . . . . . . . . . . . . . . . . . . .10

; SRAM Byte Mode,

. . . . . . . . . . . . . . . . . . . . . . . . . . . .11

SecSi (Secured Silicon) Sector Flash Memory

Region . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Factory Locked: SecSi Sector Programmed

and Protected At the Factory . . . . . . . . . . . . . . 19

Customer Lockable: SecSi Sector NOT

Programmed or Protected At the Factory . . . . . 19

Hardware Data Protection . . . . . . . . . . . . . . . . . . 19

Low V

Write Inhibit . . . . . . . . . . . . . . . . . . . . 19

Write Pulse “Glitch” Protection . . . . . . . . . . . . . 19

Logical Inhibit . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Power-Up Write Inhibit . . . . . . . . . . . . . . . . . . . 20

Common Flash Memory Interface (CFI) . . . . . . . 20

Table 8. CFI Query Identification String . . . . . . 20

Table 9. System Interface String . . . . . . . . . . . 21

Table 10. Device Geometry Definition . . . . . . . 21

Table 11. Primary Vendor-Specific Extended

Query . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Command Definitions. . . . . . . . . . . . . . . . . . . . . . 23

Reading Array Data . . . . . . . . . . . . . . . . . . . . . . . 23

Reset Command . . . . . . . . . . . . . . . . . . . . . . . . . 23

Autoselect Command Sequence . . . . . . . . . . . . . 23

Enter SecSi Sector/Exit SecSi Sector

Command Sequence . . . . . . . . . . . . . . . . . . . . . . 24

Byte/Word Program Command Sequence . . . . . 24

Unlock Bypass Command Sequence . . . . . . . . 24

Figure 3. Program Operation. . . . . . . . . . . . . . . 25

Chip Erase Command Sequence . . . . . . . . . . . . 25

Sector Erase Command Sequence . . . . . . . . . . . 25

Erase Suspend/Erase Resume Commands . . . . 26

Figure 4. Erase Operation . . . . . . . . . . . . . . . . . 26

Table 12. DS42516 Command Definitions . . . . 27

Write Operation Status. . . . . . . . . . . . . . . . . . . . . 28

DQ7: Data# Polling . . . . . . . . . . . . . . . . . . . . . . . 28

Figure 5. Data# Polling Algorithm . . . . . . . . . . . 28

RY/BY#: Ready/Busy# . . . . . . . . . . . . . . . . . . . . . 29

DQ6: Toggle Bit I . . . . . . . . . . . . . . . . . . . . . . . . . 29

Figure 6. Toggle Bit Algorithm. . . . . . . . . . . . . . 29

DQ2: Toggle Bit II . . . . . . . . . . . . . . . . . . . . . . . . 30

Reading Toggle Bits DQ6/DQ2 . . . . . . . . . . . . . . 30

DQ5: Exceeded Timing Limits . . . . . . . . . . . . . . . 30

DQ3: Sector Erase Timer . . . . . . . . . . . . . . . . . . 30

Table 13. Write Operation Status . . . . . . . . . . . 31

Absolute Maximum Ratings. . . . . . . . . . . . . . . . . 32

Operating Ranges. . . . . . . . . . . . . . . . . . . . . . . . . 32

Industrial (I) Devices . . . . . . . . . . . . . . . . . . . . . 32

f/VCCs Supply Voltage . . . . . . . . . . . . . . . . . 32

DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 33

CMOS Compatible . . . . . . . . . . . . . . . . . . . . . . . 33

SRAM DC and Operating Characteristics. . . . . . 34

Zero-Power Flash . . . . . . . . . . . . . . . . . . . . . . . 35

Figure 9. I

Current vs. Time (Showing

CC1

Active and Automatic Sleep Currents). . . . . . . . 35

Figure 10. Typical I

vs. Frequency . . . . . . . . 35

CC1

Test Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Figure 11. Test Setup . . . . . . . . . . . . . . . . . . . . 36

Table 14. Test Specifications . . . . . . . . . . . . . . 36

DS42516 3

Key To Switching Waveforms. . . . . . . . . . . . . . . 36

Figure 12. Input Waveforms and

Measurement Levels . . . . . . . . . . . . . . . . . . . . 36

AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . 37

SRAM CE#s Timing . . . . . . . . . . . . . . . . . . . . . . .37

Figure 13. Timing Diagram for Alternating

Between SRAM to Flash. . . . . . . . . . . . . . . . . . 37

Flash Read-Only Operations . . . . . . . . . . . . . . . .38

Figure 14. Read Operation Timings . . . . . . . . . 38

Hardware Reset (RESET#) . . . . . . . . . . . . . . . . .39

Figure 15. Reset Timings . . . . . . . . . . . . . . . . . 39

Flash Word/Byte Configuration (CIOf) . . . . . . . . .40

Figure 16. CIOf Timings for Read Operations . 40 Figure 17. CIOf Timings for Write Operations. . 40

Flash Erase and Program Operations . . . . . . . . .41

Figure 18. Program Operation Timings. . . . . . . 42

Figure 19. Accelerated Program Timing

Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Figure 20. Chip/Sector Erase Operation

Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Figure 21. Back-to-back Read/Write Cycle

Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Figure 22. Data# Polling Timings (During

Embedded Algorithms) . . . . . . . . . . . . . . . . . . . 44

Figure 23. Toggle Bit Timings (During

Embedded Algorithms) . . . . . . . . . . . . . . . . . . . 45

Figure 24. DQ2 vs. DQ6 . . . . . . . . . . . . . . . . . . 45

Temporary Sector/Sector Block Unprotect . . . . . .46

Figure 25. Temporary Sector/Sector Block

Unprotect Timing Diagram . . . . . . . . . . . . . . . . 46

Figure 26. Sector/Sector Block Protect and

Unprotect Timing Diagram . . . . . . . . . . . . . . . . 47

Alternate CE#f Controlled Erase and Program

Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48

Figure 27. Flash Alternate CE#f Controlled

Write (Erase/Program) Operation Timings . . . . 49

SRAM Read Cycle . . . . . . . . . . . . . . . . . . . . . . . 50

Figure 28. SRAM Read Cycle—Address

Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Figure 29. SRAM Read Cycle . . . . . . . . . . . . . . 51

SRAM Write Cycle . . . . . . . . . . . . . . . . . . . . . . . . 52

Figure 30. SRAM Write Cycle—WE# Control . . 52 Figure 31. SRAM Write Cycle—CE1#s Control. 53 Figure 32. SRAM Write Cycle—UB#s and

LB#s Control . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Flash Erase And Programming Performance . . . 55

Flash Latchup Characteristics. . . . . . . . . . . . . . . 55

Package Pin Capacitance . . . . . . . . . . . . . . . . . . 55

Flash Data Retention . . . . . . . . . . . . . . . . . . . . . . 55

SRAM Data Retention. . . . . . . . . . . . . . . . . . . . . . 56

Figure 33. CE1#s Controlled Data Retention

Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Figure 34. CE2s Controlled Data Retention

Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . 57

FLB073—73-Ball Fine-Pitch Grid Array

8 x 11 mm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 58

Revision A (October 9, 2000) . . . . . . . . . . . . . . . 58

Revision B (March 8, 2001) . . . . . . . . . . . . . . . . . 58

Global . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

Flash Memory Block Diagram . . . . . . . . . . . . . . 58

Sector/Sector Block Protection/Unprotection . . 58 Customer Lockable: SecSi Sector NOT

Programmed or Protected At the Factory . . . . . 58

Common Flash Memory Interface (CFI) . . . . . . 58

Command Definitions . . . . . . . . . . . . . . . . . . . . 58

Revision B+1 (March 15, 2001) . . . . . . . . . . . . . . 58

4 DS42516

PRODUCT SELECTOR GUIDE

Part Number DS42516

Standard Voltage Range: VCC = 2.7–3.3 V Flash Memory SRAM Max Access Time (ns) 90 85 CE# Access (ns) 90 85 OE# Access (ns) 40 45

MCP BLOCK DIAGRAM

A0 to A20

–

WP#/ACC

RESET#

CE#f

CIOf

LB#s

UB#s

WE#

OE#

CE1#s

CE2s

CIOs

A0 to A20

A0 to A19

A0 to A17

VCCf

32 M Bit

Flash Memory

VCCs/V

CCQ

4 M Bit

Static RAM

VSS/V

DQ0 to DQ15/A

SSQ

DQ0 to DQ15/A

RY/BY#

–

DQ0 to DQ15/A

–

DS42516 5

FLASH MEMORY BLOCK DIAGRAM

A0–A20

Upper Bank Address

Upper Bank

OE# BYTE#

Y-Decoder

A0–A20

RESET#

WE#

CE#

BYTE#

WP#/ACC

DQ0–DQ15

RY/BY#

A0–A20A0–A20

STATE

CONTROL

& COMMAND REGISTER

X-Decoder

Status

Control

X-Decoder

Latches and Control Logic

DQ0–DQ15

DQ0–DQ15 DQ0–DQ15

A0–A20

Lower Bank Address

Lower Bank

Y-Decoder

Latches and

Control Logic

OE# BYTE#

6 DS42516

CONNECTION DIAGRAM

73-Ball FBGA

Top View

CE#f

OE#

LB#

UB#

A18

A17

DQ1

DQ9

WP#/ACC

RESET#

RY/BY#

DQ3

WE#

CE2s

A20

DQ4

A19

A10

DQ6

DQ13

A11

A12

A13

A14

DQ15/A-1

A15

A16

CIOf

A10

B10

F10

G10

Flash only

SRAM only

Shared

CE1#s

DQ0

DQ8

DQ10

DQ2

DQ11

CIOs

Special Handling Instructions for FBGA Package

Special handling is required for Flash Memory products in FBGA packages.

DQ12

DQ5

DQ7

DQ14

L10

M10

Flash memory dev ices in FBGA pa ckages may be damaged if exposed to ultrasonic cleaning methods. The package and/or data integrity may be compromised if the package body is exposed to temperatures above 150

°C for prolonged periods of time.

DS42516 7

PIN DESCRIPTION

A0–A17 = 18 Address Inputs (Common) A-1, A18–A20 = 4 Address Inputs (Flash) SA = Highest Order Address Pin (SRAM)

Byte mode DQ0–DQ15 = 16 Data Inpu ts /Outpu ts (Co mmo n) CE#f = Chip Enable (Flash) CE#s = Chip Enable (SRAM) OE# = Output Enable (Common) WE# = Write Enable (Common) RY/BY# = Ready/Busy Output UB#s = Upper Byte Control (SRAM) LB#s = Lower Byte Control (SRAM) CIOf = I/O Configuration (Flash)

CIOf = V

CIOf = V CIOs = I/O Configuration (SRAM)

CIOs = V

CIOs = V RESET# = Hardware Reset Pin, Active Low

= Word mode (x16),

= Byte mode (x8)

= Word mode (x16),

= Byte mode (x8)

LOGIC SYMBOL

A0–A17

A-1, A18–A20 SA

CE#f CE1#s

CE2s OE# WE# WP#/ACC RESET# UB#s LB#s CIOf CIOs

16 or 8

DQ0–DQ15

RY/BY#

WP#/ACC = Hardware Write Protect/

Acceleration Pin (Flash) V

f = Flash 3.0 volt-only single power sup-

ply (see Product Selector Guide for

speed options and voltage sup p ly

tolerances)

s = SRAM Power Supply

= Device Ground (Common)

NC = Pin Not Connected Internally

ORDERING INFORMATION

Valid Combination

Order Number Package Marking

DS42516 DS42516

DEVICE BUS OPERATIONS

This section describe s the requirements and use of the device bus operations, which are initiated through the internal co mmand reg ister. The comma nd regist er itself does not occupy any addressable memory location. The register is a latch used to store the commands, along with the address and data information needed to execu te th e c omm and . The c on ten ts of

the register serve as inputs to the internal state machine. The state machine outputs dictate the function of the device. Tables 1 through 3 lists the de vice bus operations, the inputs and control levels they require, and the resulting output. The following subsections describe each of these operations in further detail.

8 DS42516

Table 1. Device Bus Operations—Flash Word Mode, CIOf = VIH; SRAM Word Mode, CIOs = VCC

Operation (Notes 1, 2)

CE#f CE1#s CE2s OE# WE# SA LB#s UB#s RESET#

Read from Flash L

Write to Flash L

Standby

0.3 V

Output Disable

Flash Hardware Reset

Sector Protect (Note 4)

Sector Unprotect (Note 4)

HX XL HX XL HX

HLH

XL HX

WP#/ACC

(Note 3)

LH X X X H L/H D

H L X X X H ( No te 3) D

XX X X X

0.3 V

DQ0– DQ7 DQ8–DQ15

OUT

HHigh-ZHigh-Z

HH X L X HH X X L

H L/H High-Z High-Z

HH X X X

X X X X X L L/H High-Z High-Z

HL X X X V

L/H D

(Note 5) D

Temporary Sector Unprotect

Read from SRAM H L H L H X

Write to SRAM H L H X L X

HX XL

XX X X X V

HL High-Z D

HX LH D LL

HL High-Z D

(Note 5) D

OUT

High-Z

OUT

High-Z

LH DINHigh-Z

Legend: L = Logic Low = VIL, H = Logic High = VIH, VID = 8.5–12.5 V, VHH = 9.0 ± 0.5 V, X = Don’t Care, SA = Sector Address,

= Address In, DIN = Data In, D

= Data Out

OUT

Notes:

1. Other operations except for those indicated in this column are inhibited.

2. Do not apply CE#f = V

3. If WP#/ACC = V If WP#/ACC = V

, CE1#s = VIL and CE2s = VIH at the same time.

, the boot sectors will be protected. If WP#/ACC = VIH the boot sectors protection will be removed.

(9V), the program time will be reduced by 40%.

ACC

4. The sector protect and sector unprotect functions may also be implemented via programming equipment. See the “Sector/Sector Block Protection and Unprotection” section.

5. If WP#/ACC = V

, the two outermost boot sectors remain protected. If WP#/ACC = VIH, the two outermost boot sector protection

depends on whether they were last protected or unprotected using the method described in “Sector/Sector Block Protection and Unprotection”. If WP#/ACC = V

all sectors will be unprotected.

HH,

DS42516 9

Table 2. Device Bus Operations—Flash Word Mode, CIOf = V

Operation (Notes 1, 2)

CE#f CE1#s CE2s OE# WE# SA

Read from Flash L

Write to Flash L

Standby

0.3 V

Output Disable

Flash Hardware Reset

Sector Protect (Note 5)

HLH

LH X X X H L/H D

H L L X X H (Note 3) D

XX X X X

HH X L X HH X X L

HH X X X

X X X X X L L/H High-Z High-Z

HL X X X V

LB#s

(Note 3)

UB#s

(Note 3)

; SRAM Byte Mode, CIOs = VSS

WP#/ACC

(Note 4)

DQ0–DQ7 DQ8–DQ15

OUT

H High-Z High-Z

RESET#

0.3 V

H L/H High-Z High-Z

L/H D

OUT

Sector Unprotect (Note 5)

Temporary Sector Unprotect

Read from SRAM H L H L H SA X X H X D Write to SRAM H L H X L SA X X H X D

HL X X X V

XX X X X V

(Note 6) D

OUT

High-Z

High-Z High-Z

Legend: L = Logic Low = VIL, H = Logic High = VIH, VID = 8.5–12.5 V, VHH = 9.0 ± 0.5 V, X = Don’t Care, SA = Sector Address,

= Address In, DIN = Data In, D

= Data Out

OUT

Notes:

1. Other operations except for those indicated in this column are inhibited.

2. Do not apply CE#f = V

, CE1#s = VIL and CE2s = VIH at the same time.

3. Don’t care or open LB#s or UB#s.

4. If WP#/ACC = V If WP#/ACC = V

, the boot sectors will be protected. If WP#/ACC = VIH the boot sectors protection will be removed.

(9V), the program time will be reduced by 40%.

ACC

5. The sector protect and sector unprotect functions may also be implemented via programming equipment. See the “Sector/Sector Block Protection and Unprotection” section.

6. If WP#/ACC = V

, the two outermost boot sectors remain protected. If WP#/ACC = VIH, the two outermost boot sector protection

depends on whether they were last protected or unprotected using the method described in “Sector/Sector Block Protection and Unprotection”. If WP#/AC C = V

all sectors will be unprotected.

HH,

10 DS42516

T a ble 3. Device Bus Operations—Flash Byte Mode, CIOf = VIL; SRAM Byte Mode, CIOs = VSS

Operation (Notes 1, 2 )

CE#f CE1#s CE2s

Read from Flash L

Write to Flash L

Standby

0.3 V

Output Disable

Flash Hardware Reset

Sector Protect (Note 5)

Sector Unprotect (Note 5)

DQ15/

HX XL HX XL HX

HLH

XL HX

LB#s

(Note 3)

A–1

OE#

WE# SA

A–1LH X X X H L/H D

A–1HL X X X H

XX X X X

UB#s

(Note 3)

RESET#

0.3 V

WP#/ACC

(Note 4)

(Note 3)

DQ0–DQ7 DQ8–DQ15

OUT

H High-Z High-Z

High-Z

XHHX L X HHXX X L

H L/H High-Z High-Z

A–1HH X X X

X X X X X X L L/H High-Z High-Z

HL X X X V

L/H D

(Note 6) D

Temporary Sector Unprotect

Read from SRAM

HLHXLHSAX X H X D

Write to SRAM H L H X X L SA X X H X D

Hx XL

XX X X X V

(Note 6) D

OUT

High-Z

Legend: L = Logic Low = VIL, H = Logic High = VIH, VID = 8.5–12.5 V, VHH = 9.0 ± 0.5 V, X = Don’t Care, SA = Sector Address, A

= Address In, DIN = Data In, D

= Data Out

OUT

Notes:

1. Other operations except for those indicated in this column are inhibited.

2. Do not apply CE#f = V

, CE1#s = VIL and CE2s = VIH at the same time.

3. Don’t care or open LB#s or UB#s.

4. If WP#/ACC = V If WP#/ACC = V

, the boot sectors will be protected. If WP#/ACC = VIH the boot sectors protection will be removed.

(9V), the program time will be reduced by 40%.

ACC

5. The sector protect and sector unprotect functions may also be implemented via programming equipment. See the “Sector/Sector Block Protection and Unprotection” section.

6. If WP#/ACC = V

, the two outermost boot sectors remain protected. If WP#/ACC = VIH, the two outermost boot sector protection

depends on whether they were last protected or unprotected using the method described in “Sector/Sector Block Protection and Unprotection”. If WP#/AC C = V

all sectors will be unprotected.

HH,

DS42516 11

Word/Byte Configuration

The CIOf pin controls whether the device data I/O pins operate in the byte or word conf iguratio n. If the CIOf pin is set at lo gic ‘1’, the device is in wor d configuration, DQ0–DQ15 are active and controlled by CE# and OE#.

If the CIOf pin is set at logic ‘0’, the device is in byte configuration, and o nly data I/O pi ns DQ0–DQ7 are active and control led by CE# and OE# . The data I/O pins DQ8–DQ14 are tri-stated, and the DQ15 pin is used as an input for the LSB (A-1) address function.

Requirements for Reading Array Data

To read array data from the outputs, the system must drive the CE#f and OE# pins to V

. CE#f is the power

control and sele cts the de vice. OE# is the outpu t control and gates array data to the output pins. WE# should remain at V

. The CIOf pin dete rmines

whether the de vice outputs a rray data in word s or bytes.

The internal state machine is set for reading array data upon device power-up, or af ter a har dware r eset. This ensures that no sp urious alteration of th e memory content occurs during the power transition. No command is necessary in this m ode to obtai n array data . Standard micropr ocess or read cyc les that asse rt vali d addresses on the de vice addre ss in puts produ ce vali d data on the device data outp uts. Each bank remai ns enabled for read access until the co mmand register contents are altered.

See “Requirements for Reading Array Data” for more information. Refer to the AC Flash Read-Only Operations table for timing specifications and to Figure 14 for the timing diagram. I

in the DC Char acteristics

CC1

table represents the active current specification for reading array data.

Writing Commands/Command Sequences

To write a command or command sequence (which includes programming data to the device and erasin g sectors of memory), th e system must driv e WE# an d CE#f to V

For program operation s, the CIOf pin determines whether the device accept s program data in by tes or words. Refer to “Word/Byte Configuration” for more information.

The device features an Unlock Bypas s mode to facilitate faster programming. Once a bank enters the Unlock Bypass mode, only two write cycles are required to program a word or byte, instead of four. The “Word/Byte Configuration” section has details on programming data to the device using both standard and Unlock Bypass command sequences.

, and OE# to VIH.

An erase operation can erase one sector, multiple sectors, or the entire device. Tables 5–6 indicate the address space that each sector occupies. The device address space is divided into two banks: Bank 1 contains the boot/parameter sec tor s, and Ban k 2 co ntai ns the larger, c ode sectors of uniform size. A “bank address” is the address b its r equ ir ed t o un iqu ely s el ect a bank. Similarly, a “sector address” is the address bits required to uniquely select a sector.

in the DC Characteristics table represents the ac-

CC2

tive current specification for the write mode. The AC Characteristics section contains timing specification tables and timing diagrams for write operations.

Accelerated Program Operation

The device offers accelerated p rogram oper ations through the ACC function. This is one of two functions provided by the WP#/ACC pin. This function is primarily intended to allow faster manufacturing throughput at the factory.

If the system asserts V

on this pin, the devic e auto-

matically enters th e aforemention ed Unlock B ypass mode, temporarily unprotects any protected sectors, and uses the h igher vo ltage on the pin to re duce th e time required for program operations. The system would use a two-cycle program command sequence as required by the Unloc k Bypass mo de. Removing

from the WP#/ACC pin returns the device to nor-

mal operation. Note that the WP#/ACC pin must not be at V

for operations other than accelerated pro-

gramming, or device damage may result. In ad dition, the WP#/ACC pin must not be left floating or unconnected; inconsistent behavior of the device may result.

Autoselect Functions

If the system writes the autoselect command sequence, the device enters the autoselect mode. The system can then read autosel ect co des from the internal register (which is separate from the memory array) on DQ7–DQ0. Standar d read cycle timings app ly in this mode. Refer to the Autoselect Mode and Autoselect Command Sequence sections for more information.

Simultaneous Read/Write Operations with Zero Latency

This device is capable of reading data from one bank of memory while programming or erasing in the other bank of memory. An erase operation may also be su spended to read from or program to another location within the same bank (except the sector being erased). Figu re 21 s hows how read and w rite cycles may be initiated for simultaneous operation with zero latency. I

CC6

and I represent the current specifications for read-while-program and read-while-erase, respectively.

in the DC Characterist ics table

CC7

12 DS42516

Standby Mode

When the system is not reading or writing to the device, it can place the device in the standby mode. In this mode, current consumption is greatly reduced, and the outputs are placed in the high impedance state, independent of the OE# input.

The device enters th e CMOS s tandby m ode when th e CE#f and RESET# pins are both held at V

± 0.3 V.

(Note that this is a more restricted voltage range than

.) If CE#f and RESET# are held at VIH, but not

within V

± 0.3 V, the device will be in the standby

mode, but the stan dby cur ren t will b e gr eater. The device requires standard access time (t

) for read

access when the devi ce is in either of these stand by modes, before it is ready to read data.

If the device is deselecte d during erasur e or programming, the device draws active current until the operation is completed.

in the DC Characteristics table represents the

CC3

standby current specif ic ati on.

Automatic Sleep Mode

The automatic sleep mode minimizes Flash device energy consumption. The device automati cally enables this mode w hen ad dresses remain s table for t

ACC

+ 30 ns. The aut omatic sle ep mode is in dependent o f the CE#f, WE#, and OE# control signals. Standard address access timi ngs provide new data when addresses are changed. While in sleep mode, o utput data is latc hed and always a vailable to the system.

in the DC Characteristics table represents the

CC4

automatic sleep mode current specification.

RESET#: Hardware Reset Pin

The RESET# pin provides a hardware method of resetting the device to reading array data. When th e

RESET# pin is driven low for at least a period of t

the device immediately terminates any operation in progress, tristates all output pins, and ignores all read/write commands for the duration of the RESET# pulse. The device al so resets the i nternal state machine to reading arra y data. The o peration that was interrupted should be reinitiated once the device is ready to accept another command sequence, to ensure data integrity.

Current is reduced for the duration of the RESET# pulse. When RESET# is held at V vice draws CMOS standby current (I held at V

but not within V

± 0.3 V, the standby cur-

± 0.3 V, the de-

). If RESET# is

CC4

rent will be greater. The RESET# pin may be tied to the system reset cir-

cuitry. A system reset would thus also reset the Flash memory, enabling the system to read the boot-up firmware from the Flash memory.

If RESET# is asserted during a program or erase operation, the RY/BY# pin remains a “0” (busy) until the internal reset operation is complete, which requires a time of t

(during Embed ded Algorithm s). The

READY

system can thus monitor RY/BY# to determine whether the reset ope ratio n is co mplete . If RES ET# is asserted when a program or erase operation is not executing (RY/ BY# pin is “1”), the reset operation is completed within a time of t ded Algorithms). The system can read data t the RESET# pin returns to V

(not during Embed-

READY

after

Refer to the AC Characteristics tables for RESET# parameters and to Figure 15 for the timing diagram.

Output Disable Mode

When the OE# input is at VIH, output from the device is disabled. The output pins are placed in the high impedance state.

Device

Part Number

Am29DL324D 16 Mbit

Megabits Sector Sizes Megabits Sector Sizes

T a ble 4. Device Bank Division

Bank 1 Bank 2

Eight 8 Kbyte/4 Kword,

thirty-one 64 Kbyte/32 Kword

16 Mbit

DS42516 13

Thirty-two

64 Kbyte/32 Kword

Table 5. Sector Addresses for Bottom Boot Sector Devices

Am29DL324DB

Bank 1

Sector

SA0 000000000 8/4 000000h–001FFFh SA1 000000001 8/4 002000h–003FFFh SA2 000000010 8/4 004000h–005FFFh SA3 000000011 8/4 006000h–007FFFh SA4 000000100 8/4 008000h–009FFFh SA5 000000101 8/4 00A000h–00BFFFh SA6 000000110 8/4 00C000h–00DFFFh SA7 000000111 8/4 00E000h–00FFFFh SA8 000001XXX 64/32 010000h–01FFFFh

SA9 000010XXX 64/32 020000h–02FFFFh SA10 000011XXX 64/32 030000h–03FFFFh SA11 000100XXX 64/32 040000h–04FFFFh SA12 000101XXX 64/32 050000h–05FFFFh SA13 000110XXX 64/32 060000h–06FFFFh SA14 000111XXX 64/32 070000h–07FFFFh SA15 001000XXX 64/32 080000h–08FFFFh SA16 001001XXX 64/32 090000h–09FFFFh SA17 001010XXX 64/32 0A0000h–0AFFFFh SA18 001011XXX 64/32 0B0000h–0BFFFFh SA19 001100XXX 64/32 0C0000h–0CFFFFh SA20 001101XXX 64/32 0D0000h–0DFFFFh SA21 001110XXX 64/32 0E0000h–0EFFFFh SA22 001111XXX 64/32 0F0000h–0FFFFFh SA23 010000XXX 64/32 100000h–10FFFFh SA24 010001XXX 64/32 110000h–11FFFFh SA25 010010XXX 64/32 120000h–12FFFFh SA26 010011XXX 64/32 130000h–13FFFFh SA27 010100XXX 64/32 140000h–14FFFFh SA28 010101XXX 64/32 150000h–15FFFFh SA29 010110XXX 64/32 160000h–16FFFFh SA30 010111XXX 64/32 170000h–17FFFFh SA31 011000XXX 64/32 180000h–18FFFFh SA32 011001XXX 64/32 190000h–19FFFFh SA33 011010XXX 64/32 1A0000h–1AFFFFh SA34 011011XXX 64/32 1B0000h–1BFFFFh SA35 011100XXX 64/32 1C0000h–1CFFFFh SA36 011101XXX 64/32 1D0000h–1DFFFFh SA37 011110XXX 64/32 1E0000h–1EFFFFh SA38 011111XXX 64/32 1F0000h–1FFFFFh

Sector Address

A20–A12

Sector Size

(Kbytes/Kwords)

(x8)

Address Range

(x16)

Address Range

000000h–000FFFh 001000h–001FFFh 002000h–002FFFh 003000h–003FFFh 004000h–004FFFh 005000h–005FFFh 006000h–006FFFh 007000h–007FFFh 008000h–00FFFFh 010000h–017FFFh 018000h–01FFFFh 020000h–027FFFh 028000h–02FFFFh 030000h–037FFFh 038000h–03FFFFh 040000h–047FFFh 048000h–04FFFFh 050000h–057FFFh 058000h–05FFFFh 060000h–067FFFh 068000h–06FFFFh 070000h–077FFFh 078000h–07FFFFh 080000h–087FFFh 088000h–08FFFFh 090000h–097FFFh

098000h–09FFFFh 0A0000h–0A7FFFh 0A8000h–0AFFFFh 0B0000h–0B7FFFh 0B8000h–0BFFFFh 0C0000h–0C7FFFh 0C8000h–0CFFFFh 0D0000h–0D7FFFh 0D8000h–0DFFFFh 0E0000h–0E7FFFh 0E8000h–0EFFFFh 0F0000h–0F7FFFh 0F8000h–0FFFFFh

14 DS42516

T a ble 5. Sector Addresses for Bottom Boot Sector Devices (Continued)

Am29DL324DB

Bank 2

Sector

SA39 100000XXX 64/32 200000h–20FFFFh 100000h–107FFFh SA40 100001XXX 64/32 210000h–21FFFFh 108000h–10FFFFh SA41 100010XXX 64/32 220000h–22FFFFh 110000h–117FFFh SA42 100011XXX 64/32 230000h–23FFFFh 118000h–11FFFFh SA43 100100XXX 64/32 240000h–24FFFFh 120000h–127FFFh SA44 100101XXX 64/32 250000h–25FFFFh 128000h–12FFFFh SA45 100110XXX 64/32 260000h–26FFFFh 130000h–137FFFh SA46 100111XXX 64/32 270000h–27FFFFh 138000h–13FFFFh SA47 101000XXX 64/32 280000h–28FFFFh 140000h–147FFFh SA48 101001XXX 64/32 290000h–29FFFFh 148000h–14FFFFh SA49 101010XXX 64/32 2A0000h–2AFFFFh 150000h–157FFFh SA50 101011XXX 64/32 2B0000h–2BFFFFh 158000h–15FFFFh SA51 101100XXX 64/32 2C0000h–2CFFFFh 160000h–167FFFh SA52 101101XXX 64/32 2D0000h–2DFFFFh 168000h–16FFFFh SA53 101110XXX 64/32 2E0000h–2EFFFFh 170000h–177FFFh SA54 101111XXX 64/32 2F0000h–2FFFFFh 178000h–17FFFFh SA55 111000XXX 64/32 300000h–30FFFFh 180000h–187FFFh SA56 110001XXX 64/32 310000h–31FFFFh 188000h–18FFFFh SA57 110010XXX 64/32 320000h–32FFFFh 190000h–197FFFh SA58 110011XXX 64/32 330000h–33FFFFh 198000h–19FFFFh SA59 110100XXX 64/32 340000h–34FFFFh 1A0000h–1A7FFFh SA60 110101XXX 64/32 350000h–35FFFFh 1A8000h–1AFFFFh SA61 110110XXX 64/32 360000h–36FFFFh 1B0000h–1B7FFFh SA62 110111XXX 64/32 370000h–37FFFFh 1B8000h–1BFFFFh SA63 111000XXX 64/32 380000h–38FFFFh 1C0000h–1C7FFFh SA64 111001XXX 64/32 390000h–39FFFFh 1C8000h–1CFFFFh SA65 111010XXX 64/32 3A0000h–3AFFFFh 1D0000h–1D7FFFh SA66 111011XXX 64/32 3B0000h–3BFFFFh 1D8000h–1DFFFFh SA67 111100XXX 64/32 3C0000h–3CF FFFh 1E0000h–1E7FFFh SA68 111101XXX 64/32 3D0000h–3DF FFFh 1E8000h–1EFFFFh SA69 111110XXX 64/32 3E0000h–3EFFFFh 1F0000h–1F7FFFh SA70 111111XXX 64/32 3F0000h–3FFFFFh 1F8000h–1FFFFFh

Sector Address

A20–A12

Sector Size

(Kbytes/Kwords)

(x8)

Address Range

(x16)

Address Range

Note: The address range is A20:A-1 in byte mode (CIOf=VIL) or A20:A0 in word mode (CIOf=VIH). The bank address bit is A20 for Am29DL324DB.

Table 6. SecSi Sector Addresses for Bottom Boot Devices

Sector Address

Device

Am29DL324DB 000000XXX 64/32 000000h–00FFFFh 00000h–07FFFh

A20–A12

Sector

Size

(x8)

Address Range

(x16)

Address Range

DS42516 15

Autoselect Mode

The autoselect mode prov ides manufactur er and device identification, and sector protection verification, through identifier codes output on DQ7–DQ0. This mode is primarily intended for programming equipment to automatically match a device to be programmed wi th its corres ponding pr ogrammin g algorithm. However, the autoselect codes can also be accessed in-system through the command register.

To access the autoselect codes in-system, the host system can issue the autoselect command via the command register, as shown in Table 12. This method does not require V

. Refer to the Autoselect Com-

mand Sequence section for more information.

Sector/Sector Block Protec ti on and Unprotection

(Note: For the following discussi on, the term “sector” applies to both sectors and sector blocks. A sector block consists of two or more adjacent sectors that are protected or unprotected at the same time (see Table

7).

Table 7. Bottom Boot Sector/Sector Block

Addresses for Protection/Unpro tect ion

Sector A20–A12

SA70

SA69–SA67

SA66–SA63 SA62–SA59 SA58–SA55 SA54–SA51 SA50–SA47 SA46–SA43 SA42–SA39 SA38–SA35 SA34–SA31 SA30–SA27 SA26–SA23 SA22–SA19 SA18–SA15 SA14–SA11

SA10–SA8

SA7 SA6 SA5 SA4

111111XXX 64 Kbytes

111110XXX,

111101XXX,

111100XXX 1110XXXXX 256 (4x64) Kbytes 1101XXXXX 256 (4x64) Kbytes 1100XXXXX 256 (4x64) Kbytes 1011XXXXX 256 (4x64) Kbytes 1010XXXXX 256 (4x64) Kbytes 1001XXXXX 256 (4x64) Kbytes 1000XXXXX 256 (4x64) Kbytes 0111XXXXX 256 (4x64) Kbytes 0110XXXXX 256 (4x64) Kbytes 0101XXXXX 256 (4x64) Kbytes 0100XXXXX 256 (4x64) Kbytes 0011XXXXX 256 (4x64) Kbytes 0010XXXXX 256 (4x64) Kbytes 0001XXXXX 256 (4x64) Kbytes 000011XXX,

000010XXX,

000001XXX

000000111 8 Kbytes

000000110 8 Kbytes 000000101 8 Kbytes 000000100 8 Kbytes

Sector/Sector Block

Size

192 (3x64) Kbytes

Sector

SA3 000000011 8 Kbytes SA2 000000010 8 Kbytes SA1 SA0

A20–A12

000000001 8 Kbytes 000000000 8 Kbytes

Sector/Sector Block

Size

The hardware sector protection feature disables both program and erase operations in any sector. The hardware sector unpr otection feature re- enables both program and erase operations in previously protected sectors. Note th at the sect or unprote ct algorit hm unprotects all sectors in par allel. All previously protected sectors must be individually re-protected. To change data in protected sect ors efficiently, the temporary sector un protect function is available. See “Temporary Sector/Sector Bloc k Unpr ote ct ”.

Sector protectio n and unprotection ca n be implemented as follows.

Sector protection and unprotection r e qui res V

on the

RESET# pin only, and can be implemented either in-system or via programming equipment. Figure 2 shows the algorithms and Figure 26 shows the timing diagram. This method uses standard m icroprocess or bus cycle timing. Fo r sector unpr otect, all unprotecte d sectors must first be protected prior to the first sector unprotect write cycle.

The device is shipped with all sectors unprotected. It is possible to determine whether a secto r is pro-

tected or unprotected. See the Autoselect Mode section for details.

Write Protect (WP#)

The Write Protect function provides a hardware method of protecting certai n boot sectors without using V WP#/ACC pin.

If the system asserts V vice disables program and erase functions in the two “outermost” 8 Kbyte b oot sectors indep endently of whether those sectors were protected or unprotected using the method described in “Sector/Sector Block Protection and Unprotection”. The two outermost 8 Kbyte boot sectors are the two sectors containing the lowest addresses in the bottom-boot-configured device.

If the system asserts V vice reverts to whether the two outermost 8 Kbyte boot sectors were last set to be protected or unp rotected. That is, sector protecti on or unprotection for these tw o sectors depends on whether they were last protected or unprotected using the method desc ribed in “Sec- tor/Sector Block Protection and Unprotection”.

. This function is one of two provided by the

on the WP#/ACC pin, the de-

16 DS42516

Note that the WP#/ACC pin must not be left floating or unconnected; incons istent be havior of the de vice may result.

Temporary Sector/Sector Block Unprotect

7). This feature allows temporary unprotection of previ-

ously protected sectors to change data in-system. The Sector Unprotect mo de is activa ted by setti ng the R ESET# pin to V formerly protected sectors can be programmed or erased by select ing t he se ctor addr esse s. Onc e V removed from the RESET# pin, all the previously protected sectors are protected again. Figure 1 shows the algorithm, and Figure 25 shows the timin g diagrams, for this feature.

(8.5 V – 12.5 V). During this mode,

START

RESET# = V

(Note 1)

Perform Erase or

Program Operations

RESET# = V

Temporary Sector

Unprotect Completed

(Note 2)

Notes:

1. All protected sectors unprotected (If WP#/ACC = V outermost boot sectors will remain protected).

2. All previously protected sectors are prote cte d once again.

Figure 1. Temporary Sector Unprotect Operation

DS42516 17

Temporary Sector

Unprotect Mode

Increment

PLSCNT

= 25?

Yes

Device failed

Sector Protect

Algorithm

START

PLSCNT = 1

RESET# = V

Wait 1 µs

First Write

Cycle = 60h?

Set up sector

address

Sector Protect:

Write 60h to sector

address with

A6 = 0, A1 = 1,

A0 = 0

Wait 150 µs

Verify Sector

Protect: Write 40h

to sector address

with A6 = 0,

A1 = 1, A0 = 0

Read from

sector address

with A6 = 0,

A1 = 1, A0 = 0

Data = 01h?

Protect another

sector?

Remove V

from RESET#

Write reset

command

Sector Protect

complete

Yes

START

Protect all sectors:

The indicated portion

of the sector protect

Reset

PLSCNT = 1

Yes

algorithm must be

performed for all

unprotected sectors

prior to issuing the

first sector

unprotect address

Increment

PLSCNT

= 1000?

Yes

Device failed

Sector Unprotect

PLSCNT = 1

RESET# = V

Wait 1 µs

First Write

Cycle = 60h?

All sectors protected?

Set up first sector

address

Sector Unprotect:

Write 60h to sector

address with

A6 = 1, A1 = 1,

A0 = 0

Wait 15 ms

Verify Sector

Unprotect: Write

40h to sector address with

A6 = 1, A1 = 1,

A0 = 0

Read from

sector address

with A6 = 1,

A1 = 1, A0 = 0

Data = 00h?

Last sector

verified?

Remove V

from RESET#

Yes

Temporary Sector

Unprotect Mode

Set up

next sector

address

Algorithm

Write reset

command

Note: The term “sector” in the figure applies to both sectors and sector blocks.

Figure 2. In-System Sector/Sector Block Protect and Unprotect Algorithms

18 DS42516

Sector Unprotect

complete

SecSi (Secured Silicon) Sector Flash Memory R egion

The SecSi (Secured Silicon) Sector feature provides a Flash memory region that enables perm anent part identification through an Electronic Serial Number (ESN). The SecSi Sector is 64 Kbytes in length, and uses a SecSi Sector Indicator Bit to indicate whether or not the SecSi Sector is locked wh en shipped from the factory. This bit is permanently set at the factory and cannot be chan ged, whic h prevents cloning of a factory locked part. This ensures th e security of the ESN once the product is shipped to the field.

AMD offers the dev ice with the Sec Si Sector ei ther factory locked or customer lockable. The factory-locked versi on is al ways p rotec ted wh en shi pped from the factory, and has the SecSi Sector Indicator Bit permanently set to a “1.” The customer-lock able version is shipped with the unprotected, allowing customers to utilize the that sector in any manner they choose. The custom er-loc kable v ersion has th e Sec Si Sector Indicator Bit permanently set to a “0.” Thus, the SecSi Sector Indic ator Bit prev ents cus tomer-loc kable devices from being used to replace devices that are factory locked.

The system accesses the SecSi Sector through a command sequence (s ee “Enter SecSi Sector/Exit SecSi Sector Comman d Seq uence ”). Afte r the system has written the Enter SecSi Sector command sequence, it may read the SecSi Sector by using the addresses normally occupied by the boot sectors. This mode of operation continues until the system issues the Exit SecSi Sector command sequence, or until power is removed from the device. On power-up, or following a hardware reset, the device reverts to sending commands to the boot sectors.

ated programming (ACC) and unlock bypass functions are not available wh en pro gram ming t he SecS i Se cto r.

The SecSi Sector area can be protected using one of the following procedures:

■ Write the three-cycle Enter SecSi Sector Region command sequence, and the n fol low th e in-s ys te m sector protect algorithm as sho wn in Figure 2, except that RESET# may be at eith er V

or VID. This

allows in-system protection of the without raising any device pin to a high voltage. Note that this method is only applicable to the SecSi Sector.

■ Write the three-cycle Enter SecSi Sector Region command sequence, and then use the alternate method of sector protection desc ribed in the “Sec- tor/Sector Block Protection and Unprotection”.

Once the SecSi Sec tor i s locke d and v erified, t he system must write the Exit SecSi Sector Region command sequence to return to reading and writing the remainder of the array.

The SecSi Sector protection must be used with caution since, once protected, there is no procedure available for unpro tecting the SecS i Sector area an d none of the bits in th e SecSi Sect or memory space can be modified in any way.

Hardware Data Protection

The command sequence r equ irement of unlock cycles for programming or erasing provides data protection against inadverten t writes ( refer to Table 12 for command definitions). In addition, the following hardware data protection measures prevent accidental erasure or programming , which might ot herwise be cause d by spurious system level signals during V and power-down transitions, or from system noise.

power-up

Factory Locked: SecSi Sector Programmed and Protected At the Factory

In a factory locked device, the SecSi Sector is protected when the device is shipped from the factory. The SecSi Sector ca nnot b e mod ified in any w ay. The device is available preprogrammed with a random, secure ESN only

In devices that have an ESN, the Bottom Boot device will have the 16 -byte ES N in the lowe st addre ssable memory area at addresses 00000h–00007h in word mode (or 000000h–000 00Fh in byt e mo de).

Customer Lockable: SecSi Sect or NOT Programmed or Protected At the Factory

If the security feature is not requi red, the Sec Si Sec tor can be treated as an additional Flash memory space, expanding the size of the available Flash array by 64 Kbytes. The SecSi Sector can be read, programmed, and erased as often as required. Note that the acceler-

DS42516 19

Low V

When V cept any write cycles. This protects data during V

Write Inhibit

is less than V

, the device d oes not ac-

LKO

power-up and power-down. The command register and all internal program/erase circuits are disabled, and the device resets to reading array data. Subsequent writes are ignored until V

is greater than V

LKO

The system must provide the proper signa ls to the control pins to prevent unintentional writes when V is greater than V

LKO

Write Pulse “Glitch” Prote c t io n

Noise pulses of less than 5 n s (typi cal) on OE#, CE #f or WE# do not initiate a write cycle.

Logical Inhibit

Write cycles are inhibited by holding any one of OE# =

, CE#f = VIH or WE# = VIH. To initiate a write cycle,

CE#f and WE# must be a logical zero while OE# is a logical one.

Power-Up Write Inhibit

If WE# = CE#f = V

and OE# = VIH during power up,

the device does not accept commands on the rising edge of WE#. The internal state machine is automatically reset to reading array data on power-up.

COMMON FLASH MEMORY INTERFACE (CFI)

The Common Flash Interface ( CFI) specific ation outlines device and hos t system software interrogation handshake, which allows specific vendor-spe cified software algorithms to be used for entire families of devices. Software support can then be device-in dependent, JEDEC ID-i ndependent, an d forward- and backward-compatible for the specified flash device families. Flash vendors can standardize their existing interfaces for long-term compatibility.

This device enters th e CF I Query mode when the system writes the CFI Query c ommand, 98 h, to address

Table 8. CFI Query Identification String

Addresses

(Word Mode)

Addresses

(Byte Mode)

Data Description

55h in word mode (or address AAh in byte mode), any time the device is ready to read array data. The system can read CFI information at the addresses given in Tables 8–11. To terminate reading CFI data, the system must write the reset command. The CFI Query mode is not acces sible wh en the de vice i s executin g an Embedded Program or embedded erase algorithm.

The system can also write the CFI query command when the device is in the autoselect mode. The device enters the CFI query mode, and the system can read CFI data at the addresses given in Tables 8–11. T he system must write the reset command to return the device to the autoselect mode.

For further information, please refer to the CFI Specification and CFI Publication 100, available via the World Wide Web at http://www.amd.com/products/nvd/overview/cfi.html. Alternatively, contact an AMD representative for copies of these documents.

10h 11h 12h

13h 14h

15h 16h

17h 18h

19h

1Ah

20h 22h 24h

26h 28h

2Ah 2Ch

2Eh 30h

32h 34h

0051h 0052h 0059h

0002h 0000h

0040h 0000h

0000h 0000h

Query Unique ASCII string “QRY”

Primary OEM Command Set

Address for Primary Extended Table

Alternate OEM Command Set (00h = none exists)

Address for Alternate OEM Extended Table (00h = none exists)

20 DS42516

T able 9. System Interface String

Addresses

(Word Mode)

1Bh 36h 0027h

1Ch 38h 0036h

1Dh 3Ah 0000h V

Addresses

(Byte Mode)

Data Description

Min. (write/erase)

D7–D4: volt, D3–D0: 100 millivolt

Max. (write/erase)

D7–D4: volt, D3–D0: 100 millivolt

Min. voltage (00h = no VPP pin present)

1Eh 3Ch 0000h VPP Max. voltage (00h = no VPP pin present) 1Fh 3Eh 0004h Typical timeout per single byte/word write 2N µs

20h 40h 0000h Typic al timeout for Min. size buffer write 2N µs (00h = not supported) 21h 42h 000Ah Typical timeout per individual block erase 2N ms 22h 44h 0000h Typical timeout for full chip erase 2N ms (00h = not supported) 23h 46h 0005h Max. timeout for byte/word write 2N times typical 24h 48h 0000h Max. timeout for buffer write 2N times typical 25h 4Ah 0004h Max. timeout per individual block erase 2N times typical 26h 4Ch 0000h Max. timeout for full chip erase 2N times typical (00h = not supported)

T able 10. Device Geometry Definition

Addresses

(Word Mode)

27h 4Eh 0015h Device Size = 2 28h

29h

2Ah 2Bh

Addresses

(Byte Mode)

50h 52h

54h 56h

Data Description

byte

0002h 0000h

0000h 0000h

Flash Device Interface des cri pti on (refe r to CFI publica t io n 100)

Max. number of byte in multi-byte write = 2

(00h = not supported) 2Ch 58h 0002h Number of Erase Block Regions within device 2Dh

2Eh 2Fh

30h 31h

32h 33h 34h

35h 36h 37h 38h

39h 3Ah 3Bh 3Ch

5Ah 5Ch 5Eh 60h

62h 64h 66h 68h

6Ah 6Ch 6Eh 70h

72h 74h 76h 78h

0007h 0000h 0020h 0000h

001Eh 0000h 0000h 0001h

0000h 0000h 0000h 0000h

Erase Block Region 1 Information (refer to the CFI specification or CFI publication 100)

Erase Block Region 2 Information

Erase Block Region 3 Information

Erase Block Region 4 Information

DS42516 21

Table 11. Primary Vendor-Specific Extended Query

Addresses

(Word Mode)

40h

41h

42h

43h 86h 0031h Major version number, ASCII

44h 88h 0031h Minor version number, ASCII

45h 8Ah 0000h

46h 8Ch 0002h

47h 8Eh 0001h

48h 90h 0001h

49h 92h 0004h

4Ah 94h

Addresses

(Byte Mode)

80h 82h 84h

Data Description

0050h 0052h 0049h

00XXh

(See Note)

Query-unique ASCII string “PRI”

Address Sensitive Unlock (Bits 1-0) 0 = Required, 1 = Not Required

Silicon Revision Number (Bits 7-2) Erase Suspend

0 = Not Supported, 1 = To Read Only, 2 = To Read & Write Sector Protect

0 = Not Supported, X = Number of sectors in per group Sector Temporary Unprotect

00 = Not Supported, 01 = Supported Sector Protect/Unprotect scheme

04 = 29LV800 mode Simultaneous Operation

00 = Not Supported, X= Number of Sectors in Bank 2 (Uniform Bank)

4Bh 96h 0000h

4Ch 98h 0000h

4Dh 9Ah 0085h

4Eh 9Ch 0095h

4Fh 9Eh 000Xh

Note: The number of sectors in Bank 2 is device dependent, Am29DL324 = 20h.

Burst Mode Type 00 = Not Supported, 01 = Supported

Page Mode Type 00 = Not Supported, 01 = 4 Word Page, 02 = 8 Word Page

ACC (Acceleration) Supply Minimum 00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV

ACC (Acceleration) Supply Maxim um 00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV

Top/Bottom Boot Sector Flag 02h = Bottom Boot Device, 03h = Top Boot Device

22 DS42516

COMMAND DEFINITIO N S

Writing specific address and data commands or sequences into the command register initiates device operations. Ta ble 12 defines th e valid register command sequences. Writing incorrect address and

data values or writing them in the improper sequence resets the device to reading array data.

All addresses are latched on the falling edge of WE# or CE#f, whiche ver ha ppens late r. All data is latc hed on the rising edge of W E# or CE#f, whiche ver happens first. Refer to the AC Characteristics section for timing diagrams.

Reading Array Data

The device is automati cally set to re ading array dat a after device power-up. No commands are required to retrieve data. Each bank is ready to read array data after completing an Embedded Program or Embedded Erase algorithm.

After the device accepts an Erase Suspend command, the corresponding bank enters the erase-suspend-read mode, after which the system can read data from any non-erase-suspended sector within the same bank. After completing a programming operation in the Erase Suspend mode, the system may once again read array data with the same exception. See the Erase Suspend/Erase Resume Commands section for more information.

The system must issu e the re set c omm and to r eturn a bank to the read (or erase-suspend-read) mode if DQ5 goes high during an active program or erase operation, or if the bank is in the autoselect mode. See the next section, Reset Command, for more information.

See also Requirements for Reading Array Data in the Device Bus Operations section for more information. The Flash Read-Only Operations table provides the read parameters, and Figure 14 shows the timing diagram.

Reset Command

Writing the reset command resets the banks to the read or erase-suspend-read mode. Address bits are don’t cares for this command.

The reset command may be written between the sequence cycles in an erase co mm and s equ enc e befo re erasing begins. Th is rese ts the b ank to w hich t he system was writing to reading a rray data . Once eras ure begins, however, the device ignores reset commands until the operation is complete.

The reset command may be written between the sequence cycles in a program command sequence before programming begins. This resets the bank to

which the system was writing to reading array data. If the program command sequence is written to a bank that is in the Erase Suspend mode, writing the reset command returns that ban k to the erase-suspend-read mode. Once programming begins, however, the device ignores reset comman ds unti l the operation is complete.

The reset command may be written between the sequence cycles in an autosel ect comm and sequen ce. Once in the autoselect mode, the reset command must be written to return to reading array data. If a bank entered the autoselect mode while in the Erase Suspend mode, writing the reset command returns that bank to the erase-suspend-read mode.

If DQ5 goes high during a program or erase operation, writing the reset command returns the banks to reading array data (or erase-suspend-read mode if that bank was in Erase Suspend).

Autoselect Command Sequence

The autoselect command sequenc e allows the host system to access the manufac ture r and de vice codes , and determine whether or not a sector is p rotected. Table 12 shows the address and data requirements. The autoselect command sequence may be written to an address within a ba nk that is ei ther in the rea d or erase-suspend-read mode. The autoselect command may not be written while the device is actively programming or erasing in the other bank.

The autoselect comm and s equen ce i s init iated by first writing two unlock cycles. This is followed by a third write cycle that con tain s t he ba nk add ress an d the autoselect comman d. The bank then enters the autoselect mode. The system may read at any address within the same bank any number of times without initiating another autoselect command sequence:

■ A read cycle at addres s (BA)XX00h (where BA is the bank address) returns the manufacturer code.

■ A read cy cle at address (BA)X X01h in word mode (or (BA)XX02h in byte mode) returns the dev ice code.

■ A read cy cle to an a ddress co ntaining a sector address (SA) within the same bank , and the address 02h on A7–A0 in word mode (or the address 04h on A6–A-1 in byte mode) returns 01h if the sector is protected, or 00h if it is unprotected. (Refer to Tables 5–6 for valid sector addre sses ) .

The system must write the reset command to return to reading array data (or erase-suspend-read mode if the bank was previously in Erase Suspend).

DS42516 23

Enter SecSi Sector/Exit SecSi Sector Command Sequence

The system can acces s the S ec Si Se ct or re gio n by issuing the thre e-cycle Ente r SecSi S ector co mmand sequence. The device continues to access the SecSi Sector region until the sy stem issues the four-cyc le Exit SecSi Sector command sequence. The Exit SecSi Sector command sequence returns the device to normal operation. Table 12 shows th e address and data requirements for bot h com ma nd seq ue nces. Se e also “SecSi (Secured Silicon) Sector Flash Memory Region” for fu rther information. Note that a har dware reset (RESET# =V

) will reset the device to reading

array data.

Byte/Word Program Command Sequence

The system may program the device by word or byte, depending on the state of the CIOf pin. Programming is a four-bus-cycle operation. The program command sequence is initiated by writi ng two unlock write cycles, follo wed by th e progr am set-up command . The program address and data are written next, which in turn initiate the Embedded Program algorithm. The system is not required to provide fur ther controls or timings. The device automatically provides internally generated program pulses and verifies the programmed cell margin. Table 12 shows the address and data requirements for the byte program command sequence.

When the Embedded Program algorithm is complete, that bank then returns to reading array data and addresses are no longer latched. The system can determine the status of the prog ram operation by using DQ7, DQ6, or RY/BY#. Refer to the Write O peration Status se ction for info rmation on the se status bits.

Any commands written to the device during the Embedded Program Algorithm are i gnored. Note that a hardware reset immediately terminates the p rogram operation. The program command sequence should be reinitiated once th at bank ha s retur ned to readin g array data, to ensure data integrity.

Programming is allowed in any sequence and across sector bounda ries. A bit cannot be programmed from “0” back to a “1.” Attempting to do so may cause that bank to set DQ5 = 1, or cause the DQ7 and DQ6 status bits to indicate the operation was success-

ful. However, a succeeding read will show that the data is still “0.” Only erase operations can convert a “0” to a “1.”

Unlock Bypass Command Sequence

The unlock bypass feature allows the system to program bytes or words to a bank faster than using the standard program command sequence. The unlock bypass command sequence is initiated by first writing two unlock cycles. Th is is followed by a third write cycle containing the unlock bypass command, 20h. That bank then enters the unlock bypass mode. A two-cycle unlock bypass program command sequence is all that is requi re d to pr og ram i n t his m ode . T he fir st cycle in this sequence contains the unlock bypass program command, A0h; the second cycle contains the program address and data. Additional data is programmed in the same ma nner. This mode dispenses with the initial two unlock cycles r equired in the standard program command sequence, resulting in faster total programming time. Table 12 shows the requirements for the command sequence.

During the unlock bypas s mode, on ly the Unlock Bypass Program and Unlock Bypass Reset commands are valid. To exit the unl ock bypas s mode, th e system must issue the two-cycle unlock bypass reset command sequence. The fi rst cy cl e m us t c onta in the bank address and the data 90h. T he second cycle nee d only contain the data 00h. The bank then returns to the reading array data.

The device offers accelerated p rogram oper ations through the WP#/ACC pin. W hen the system asserts

on the WP#/ACC pin, the device automatically en-

ters the Unlock Bypass mode. The system may then write the two-cycle Un lock Bypa ss progr am comman d sequence. The device uses the higher voltage on the WP#/ACC pin to accelerate the operation. Note that the WP#/ACC pin must not be at V

any operation

other than accelerated programmin g, or dev ice damage may result. In addition, the WP#/ACC pin must not be left floating or unconnected; inconsistent behavior of the device may result.

Figure 3 illustrates the algorit hm for the prog ra m operation. Refer to the Flash Erase and Program Operations table in the AC Characteristics section for parameters, and Figure 18 for timing diagrams.

24 DS42516

START

Note: See Table 12 for program command sequence.

Any commands written during the chip erase operation are ignored. However, note that a hardware res et immediately terminates the erase operation. If that occurs, the chip erase command sequence should be reinitiated once that bank has returned to reading array data, to ensure data integrity.

Write Program

Command Sequence

Data Poll

Embedded

Program

algorithm

in progress

Increment Address

from System

Verify Data?

Yes

Last Address?

Yes

Programming

Completed

Figure 3. Program Operation

Chip Erase Command Sequence

Chip erase is a six bus cycle operation. The chip erase command sequence is initiated by writing two unlock cycles, followed by a se t-up c ommand . Two additional unlock write cycles are then followed by the chip erase command, which in turn inv ok es th e E mb edde d E ras e algorithm. The device does not require the system to preprogram prior to erase. The Embedded Erase algorithm automatically preprograms and verifies the entire memory for an all zero data patter n prior to e lectrical erase. The syst em is not r equired to prov ide any co ntrols or timings during these operations. Table 12 shows the address and data r equir ement s for the c hip erase command sequence.

When the Embedded Erase algor ithm is complete, that bank returns to reading arr ay data an d address es are no longer latched. The system can determine the status of the erase operation by using DQ7, DQ6, DQ2, or RY/BY#. Refer to the Write Operation Status section for information on these status bits.

Figure 4 illustrates the algorithm for the erase operation. Refer to the Flash Erase and Program Operations tables in the AC Characteristics section for parameters, and Figure 20 section for timing diagrams.

Sector Erase Command Sequence

Sector erase is a s ix bus cycle op eration. The sector erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. Two additional unlock cycles are wr itten, and are then followed by the address of the sector to be erased, and the sector erase command. Table 12 shows the address and data requirements for the sec tor erase command sequence.

The device does not require the system to preprogram prior to erase. The E mbedded E rase algori thm automatically programs and verifies the entire memory for an all zero da ta patter n prior to electri cal eras e. The system is not required to provi de any controls or timings during these operations.

After the command sequence is written, a sector erase time-out of 50 µs occurs. During the time-out period, additional sector addresses and sector erase commands may be written. Loading the sector erase buffer may be done in any sequence, and the number of sectors may be from one sector to all sectors. The time between these additional cycles must be less than 50 µs, other wis e eras ur e m ay beg in. An y sector erase address and command following the exceeded time-out may or may not be accepted. It is recommended that proce ssor i nterru pts be disa bled durin g this time to ensure all commands are accepted. The interrupts can be re-enabled after the last Sector Erase command is written. Any command other than

Sector Erase or Erase Suspend during the time-out period resets that bank to reading array data. The system must rewrite the command se-

quence and any additional addresses and commands. The system can monitor DQ3 to determine if the sec-

tor erase timer has timed out (See the section on DQ3: Sector Erase Timer.). The time-out begins from the rising edge of the final WE# pulse in the command sequence.

When the Embedded Erase al gor it hm is com pl ete, the bank returns to readi ng array data an d addr esses a re no longer latched. Note that while the Embedded Erase operation is in progress, the system can read data from the non-erasing bank. T he system can de-

DS42516 25

termine the status of the erase operation by reading DQ7, DQ6, DQ2, or RY/BY# in the erasing bank. Refer to the Write Oper ation Status section for i nformation on these status bits.

Once the sector erase operation has begun, on ly the Erase Suspen d command is valid . All other commands are ignored. However, note that a hardware reset immediately terminates the erase operation. If that occurs, the sector erase command sequence should be reinitiated once that bank has returned to reading array data, to ensure data integrity.

Erase Suspend/Erase Resume Commands

The Erase Suspend command, B0h, allows the system to interrupt a sector erase operation and then read data from, or prog ram data to , a ny s ec tor n ot se lec te d for erasure. The bank address is required when writing this command. This command is valid only during the sector erase operation, including the 50 µs time-out period during the sector erase command sequence. The Erase Suspend command is ignored if written during the chip erase oper ation or Embedded P rogram algorithm.

When the Erase Suspend command is written during the sector erase operation, the device requires a maximum of 20 µs to sus pend the erase operation. However, when the Erase Suspend command is written during the s ector erase time-out, the device immediately terminates the time-out period and suspends the erase operation.

mode. The system can determine the status of the program operation using the DQ7 or DQ6 status bits, just as in the standard Byte Program operation. Refer to the Write Operatio n Status s ection for mor e information.

In the erase-suspend-rea d mode, the sys tem can als o issue the autoselec t c om man d s equ ence. Refer to the Autoselect Mode and Autoselect Command Sequence sections for details.

To resume the sector erase operation, the system must write the Erase Resume command. The bank address of the erase-suspended bank is re quired when writing this command. Further writes of the Resume comma nd ar e igno red. A nothe r Eras e Su spend command can be written after the chip has resumed erasing.

START

Write Erase

Command Sequence

(Notes 1, 2)

Data Poll to Erasing

Bank from System

Data = FFh?

Embedded Erase algorithm in progress

After the erase operation has been suspended, the bank enters the erase-susp end-read mode. The system can read data fr om or pr ogram d ata to a ny s ector not selected for erasure. (The devic e “erase suspends” all sectors s elected for erasure.) Rea ding at any address within erase-suspended sectors produces status information on DQ7–DQ0. The system can use DQ7, or DQ6 and DQ 2 tog eth er, to determine if a sector is actively erasing or is erase-suspended. Refer to the Write Oper ation Status section for i nformation on these status bits.

After an erase-suspended program operation is complete, the bank r eturns to the era se-suspend-r ead

26 DS42516

Yes

Erasure Completed

Notes:

1. See Table 12 for erase command sequence.

2. See the section on DQ3 for information on the sector erase timer.

Figure 4. Erase Operation

T able 12. DS42516 Command Definitions

Command Sequence

(Note 1)

Read (Note 6) 1 RA RD Reset (Note 7) 1 XXX F0

Manufacturer ID

Device ID SecSi Sector Factory

Protect (Note 9) Sector Protect Verify

Autoselect (Note 8)

(Note 10)

Enter SecSi Sector Region

Exit SecSi Sector Region

Program

Unlock Bypass Unlock Bypass Program (Note 11) 2 XXX A0 PA PD

Unlock Bypass Reset (Note 12) 2 BA 90 XXX 00 Chip Erase

Sector Er ase Erase Suspend (Note 13) 1 BA B0

Erase Resume (Note 14) 1 BA 30 CFI Query (Note 15)

Legend:

X = Don’t care RA = Address of th e me mo ry location to be read. RD = Data read from location RA during read operation. PA = Address of the memory location to be programmed. Addresses latch on the fa llin g ed ge of t he WE # o r C E# f pul s e, w hi che ver ha pp ens

later.

Word

Byte AAA 555 (BA)AAA

Word

Byte AAA 555 (BA)AAA (BA)X02

Word

Byte AAA 555 (BA)AAA (BA)X06

Word

Byte AAA 555 (BA)AAA (SA)X04

Word

Byte AAA 555 AAA

Word

Byte AAA 555 AAA

Word

Byte AAA 555 AAA

Word

Byte AAA 555 AAA

Word

Byte AAA 555 AAA AAA 555 AAA

Word

Byte AAA 555 AAA AAA 555

Word

Byte AA

First Second Third Fourth Fifth Sixth

Cycles

Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data

555

2AA

Bus Cycles (Notes 2–5)

(BA)555

555

PD = Data to be programmed at location PA. Data latches on the rising edge of WE# or CE#f pulse, whichever happens first. SA = Address of the sect or to be veri fi ed (in au t ose lec t mo de ) or erased. Address bits A20–A12 uniquely select any sector. BA = Address of th e b an k th at is be ing swi tc h ed to au to s el ect mo de , is in bypass mode, or is being erased.

90 (BA)X00 01

(BA)X01

(BA)X03

(SA)X02

90 XXX 00

A0 PA PD

555

81/01

00/01

2AA

55 SA 30

555

Notes:

1. See T ables 1 through 3 for description of bus operations.

2. All values are in hexadecimal.

3. Except for the read cycle and the fourth cycle of the autoselect command sequence, all bus cycles are write cycles.

4. Data bits DQ15–DQ8 are don’t care in command sequences, except for RD and PD.

5. Unless otherwise noted, address bits A20–A11 are don’t cares.

6. No unlock or command cycles required when bank is in read mode.

7. The Reset command is required to return to reading array data (or to the erase-suspend-read mode if previously in Erase Suspend) when a bank is in the autoselect mode, or if DQ5 goes high (while the bank is providing status information).

8. The fourth cycle of the autoselect command sequence is a read cycle. The system must provide the bank address to obtain the manufacturer ID, device ID, or SecSi Sector factory protect information. Data bits DQ15–DQ8 are don’t care. See the

Autoselect Command Sequence section for more information.

9. The data is 80h for factory locked and 00h for not factory locked.

10. The data is 00h for an unprotected sector/sector block and 01h for a protected sector/sector block.

11. The Unlock Bypass command is required prior to the Unlock Bypass Program command.

12. The Unlock Bypass Reset command is required to return to reading array data when the bank is in the unlock bypass mode.

13. The system may read and program in non-erasing sectors, or enter the autoselect mode, when in the Erase Suspend mode. The Erase Suspend command is valid only during a sector erase operation, and requires the bank address.

14. The Erase Resume command is valid only during the Erase

DS42516 27

WRITE OPERATION STATUS

The device provides several bi ts to determ ine the status of a program or erase o peration: DQ2, DQ3, D Q5, DQ6, and DQ7. Table 13 and the following subs ections describe the function of these bits. DQ7 and DQ6 each offer a method for deter mining wheth er a program or erase operation is comp lete or in progress . The device also provides a hardware-based output signal, RY/BY#, to determine whether an Embedded Program or Erase operation is in progress or has been completed.

DQ7: Data# Polling

The Data# Polling bit, DQ7, indicates to the host system whether an Embedded Program or Erase algorithm is in progr ess or completed, or whether a bank is in Erase Suspend. Data# Polling is valid after the rising edge of the final WE# pulse in the command sequence.

During the Embedded Program algorit hm, the device outputs on DQ7 the complement of the datum programmed to DQ7. This DQ7 s tatus also a pplies to programming during Erase Suspend. When the Embedded Program algorithm is complete, the device outputs the datum programmed to DQ7. The system must provide the progr am add re ss to read v al id sta tus information on DQ7. If a program address falls within a protected sector, Data# Polling on DQ7 is active for approximately 1 µs, then that bank returns to reading array data.

During the Embedded Erase algorithm, Data# Polling produces a “0” on DQ7. When the Embedded Erase algorithm is complete, or if the bank enters the Erase Suspend mode, Data# Polling produces a “1” on DQ7. The system must prov ide an a ddr es s w ith in a ny of th e sectors selected for erasure to read valid status information on DQ7.

After an erase command sequence i s written, if all sectors selected for e ra sing ar e p ro tected, Data# Polling on DQ7 is active for approximately 100 µs, then the bank returns to reading a rray data. If no t all selected sectors are protected, the Embedded Erase algorithm erases the un pr ote cte d sec tor s , a nd ig nor es the selected sectors that are protected. However, if the system reads DQ7 at an address within a protected sector, the status may not be valid.

Just prior to the com pleti on of an E mbed ded P rogram or Erase operati on, DQ7 may cha nge a syn chro nous ly with DQ0–DQ6 while Output Enable (OE#) is asserted low. That is, the device may change from providing status information to valid data on DQ7. Depending on when the system samples the DQ7 output, it may read the status or valid data. Even if the device has com-

pleted the program or erase operation and DQ7 has valid data, the da ta outputs on DQ0–DQ6 may be still invalid. Valid data on DQ0–DQ7 will appear on successive read cycles.

Table 13 sho ws the o utput s for Data # Pollin g on DQ7 . Figure 5 shows the Data# Po lling algorithm . Figure 22 in the AC Characteristics section shows the Data# Polling timing diagram.

START

Read DQ7–DQ0

Addr = VA

DQ7 = Data?

Notes:

1. VA = Valid address for programming. During a sector erase operation, a valid address is any sector address within the sector being erased. During chip erase, a valid address is any non-protected sector address.

2. DQ7 should be rechecked even if DQ5 = “1” because DQ7 may change simultaneously with DQ5.

DQ5 = 1?

Yes

Read DQ7–DQ0

Addr = VA

DQ7 = Data?

FAIL

Yes

PASS

Figure 5. Data# Polling Algorithm

28 DS42516

RY/BY#: Ready/Busy#

The RY/BY# is a dedicated, open-drain output pin which indic ates whe ther an Em bedd ed A lgo rithm is in progress or complete. The RY/BY# status is valid after the rising edge of the final WE# pulse in the command sequence. Since RY/BY# is an open-drain output, several RY/BY# pins can be tied together in parallel with a pull-up resistor to V

If the output is low (Busy), the device is actively erasing or programmin g. (This include s programmi ng in the Erase Suspend mode.) If the output is high (Ready), the device is re ading ar ray data, th e stan dby mode, or one of the banks is in the erase-suspend-read mode.

Table 13 shows the outputs for RY/BY#.

DQ6: T oggle Bit I

Toggle Bit I on DQ6 i ndicates whethe r an Emb edded Program or Erase algorithm is in progr ess or complete, or whether the device has entered the Erase Suspend mode. Toggle Bit I may be read at any address, and is valid after the rising edge of the final WE# pulse in the command sequence ( prior to the program or erase operation), and during the sector erase time-out.

DQ6 also toggles during the erase-suspend-pro gram mode, and stops toggling once the Embedded Program algorithm is complete.

Table 13 shows the outputs for Toggle Bit I on DQ6. Figure 6 shows the toggle bit algorithm. Figure 23 in the “AC Charac teristics” section shows the toggle bi t timing diagrams. Figure 24 shows the differences between DQ2 and DQ6 in graphical for m. See also th e subsection on DQ2: Toggle Bit II.

START

Read DQ7–DQ0

Toggle Bit

= Toggle?

During an Embedded P rogram or Erase alg orithm operation, successive read cycles to any address cause DQ6 to toggle. The system may use either OE# or CE#f to control the read cy c les. W hen the operation is complete, DQ6 stops toggling.

After an erase command sequence i s written, if all sectors selected for erasing are protected, DQ6 toggles for approxim ately 100 µs , then retur ns to readi ng array data. If not all selected sectors are protected, the Embedded Erase algorithm erases the unprotected sectors, and ignores the selected sectors that are protected.

The system can use DQ6 and DQ2 together to determine whether a sector is actively erasing or is erase-suspended. Wh en the device is activel y erasin g (that is, the Embedded Erase algorithm is in progress), DQ6 toggles. When the device enters the Erase Suspend mode, DQ6 stops togg li ng. Howe ver, the system must also use DQ2 to determine which sectors are erasing or e rase-s usp ended . Al ternat ive ly, the system can use DQ7 (see the subsection on DQ7: Data# Polling).

If a program address falls within a protected sector, DQ6 toggles for approximately 1

µs after the prog ram

command sequence is wri tten, then returns to read ing array data.

Yes

Note: The system shoul d recheck the toggle bit even if DQ5 = “1” because the toggle bit may stop toggling as DQ5 changes to “1.” See the subsections on DQ6 and DQ2 for more information.

DQ5 = 1?

Yes

Read DQ7–DQ0

Twice

Toggle Bit

= Toggle?

Yes

Program/Erase

Operation Not Complete, Write Reset Command

Program/Erase

Operation Complete

Figure 6. Toggle Bit Algorithm

DS42516 29

DQ2: Toggle Bit II

The “Toggle Bit II” on DQ2, whe n u sed wi th DQ6, indi- cates whether a particula r sector is actively erasin g (that is, the Embedded Erase algorithm is in progress), or whether that sector is erase-suspended. Toggle Bit II is valid after the rising edge of the final WE# pulse in the command sequence.

DQ2 toggles when the system reads at addresses within those sectors that have been selected for erasure. (The system may use either OE# or CE#f to control the read cycles.) But DQ2 cannot distinguish whether the s ector i s acti vely era sing or is er ase-s uspended. DQ6, by comparison, indicates whether the device is actively erasing, or is in Erase Suspend, but cannot distinguish which sectors are selected for erasure. Thus, both status bits are required for sector and mode information. Refer to Table 13 to compare outputs for DQ2 and DQ6.

Figure 6 shows the toggle bit algorit hm in flowchart form, and the se ct ion “DQ 2: Toggle Bit II” explains the algorithm. See also the DQ6: Toggle Bit I subsection. Figure 23 shows the toggle bit timing diagram. Figure 24 shows the differences between DQ2 and DQ6 in graphical form.

Reading Toggle Bits DQ6/DQ2

Refer to Figure 6 for the following discussion. Whenever the system initially begi ns reading toggle bit status, it must read DQ7–DQ0 at least twic e in a row to determine whether a toggle bit is tog gl ing. Typically, the system would note and store the value of the toggle bit after the first read. After the second read, the system would compare th e new va lue of th e tog gle bit with the first. If the toggle bit is not toggling, the device has completed the program or erase operation. The system can read array data on DQ7–DQ 0 on the following read cycle.

However, if after the initial two read cycles, the system determines that the toggle bit is still toggling, the system also should note whether the value of DQ5 is high (see the section on DQ5). If it is, the system should then determine again whether the toggle bit is toggling, since the toggle bit may ha ve stopped tog gling just as DQ5 went high . If the toggle bit is no longer toggling, the device has successfully completed the program or erase operation. If it is still toggling, the device did not completed the op eration su cces sfull y, and the system must write th e rese t comma nd to ret urn to reading array data.

The remaining scenario is that the system initially determines that the toggle bit is toggling and DQ5 has not gone high. The system may conti nue to monitor the toggle bit and DQ5 through successive re ad cy-

cles, determ ining the status as de scribed in the previous paragraph. Alternatively, it may choose to perform other system tasks. In this case, the system must start at the beginni ng o f the a lgo rithm when it r eturns to determin e the status of the operat ion (top of Figure 6).

DQ5: Exceeded Timing Limits

DQ5 indicates whether the program or erase time has exceeded a specified internal pulse count li mit. Under these conditions DQ5 produces a “1,” indicating that the program or erase c ycle was not s uccessfully completed.

The device may output a “1” on DQ5 if the system tries to program a “1” to a loc ation that was prev iousl y programmed to “0.” Only an erase opera tion can change a “0” back to a “1.” Under this condition, the device halts the operation, and when the timing limit has been exceeded, DQ5 produces a “1.”

Under both these conditions, the system must write the reset command to return to reading array data (or to the erase-suspend-read mode if a bank was previously in the erase-suspend-program mode).

DQ3: Sector Erase Timer

After writing a sect or erase co mmand sequ ence, the system may read DQ3 to determine whether or not erasure has begun. (The sector erase timer does not apply to the chip erase command.) If additional sectors are selected for erasure, the entire time-out also applies after each additional sector erase command. When the time-out period is c omplete, DQ3 switches from a “0” to a “1.” If the time between additional sector erase commands from the system can be assumed to be less than 50 µs, the system need not monitor DQ3. See also the Sector Erase Command Sequence section.

After the sector erase comman d is writte n, the syste m should read the statu s o f D Q7 (D ata # Po llin g) or DQ 6 (Toggle B it I) to ensure that the device has ac cepted the command sequence, and then read DQ3. If DQ3 is “1,” the Embedded Erase alg orithm has begun; al l further commands (e xcept E rase Sus pend) ar e ignor ed until the erase operation is complete. If DQ3 is “0,” the device will accept additional sector erase commands. To ensure the command has been accepted, the system software should check the status of DQ3 prior to and following each subsequent sector erase command. If DQ3 is high on the second status check, the last command might not have been accepted.

Table 13 show s the sta tus of DQ 3 relativ e to the ot her status bits.

30 DS42516

Table 13. Write Operation Status

Status

Standard

Mode

Erase

Suspend

Mode

Notes:

1. DQ5 switches to ‘1’ when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits. Refer to the section on DQ5 for more information.

2. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further details.

3. When reading write operation status bi ts, the system must always provide the bank address whe re the Embedde d Algorithm is in progress. The device outputs array data if the system addresses a non-busy bank.

Embedded Program Algorithm DQ7# Toggle 0 N/A No toggle 0 Embedded E rase Algorithm 0 Toggle 0 1 Toggle 0

Erase

Erase-Suspend-

Read

Erase-Suspend-Program DQ7# Toggle 0 N/A N/A 0

Suspended Sector Non-Erase

Suspended Sector

DQ7

(Note 2)

1 No toggle 0 N/A Toggle 1

Data Data Data Data Data 1

DQ6

DQ5

(Note 1)

DQ3

DQ2

(Note 2)

RY/BY#

DS42516 31

20 ns

+0.8 V

–0.5 V

20 ns

–2.0 V

ABSOLUTE MAXIMUM RATINGS

Storage Tempe ra ture

Plastic Packages . . . . . . . . . . . . . . . –55

Ambient Temperature

with Power Applied . . . . . . . . . . . . . . –25

Voltage with Respect to Ground

f/VCCs (Note 1) . . . . . . . . . . . .–0.3 V to +4.0 V

A9, OE#, and RESET#

(Note 2). . . . . . . . . . . . . . . . . . . .–0.5 V to +12.5 V

WP#/ACC . . . . . . . . . . . . . . . . . .–0.5 V to +10.5 V

All other pins (Note 1). . . . . . –0.5 V to V

Output Short Circuit Current (Note 3) . . . . . . 200 mA

Notes:

1. Minimum DC voltage on input or I/O pins is –0.5 V. During voltage transitions, input or I/O pins may overshoot V Maximum DC voltage on input or I/O pins is V See Figure 7. During vo lta ge transitions, input or I /O pins may overshoot to V Figure 8.

2. Minimum DC input voltage on pins OE#, RESET#, and WP#/ACC is –0.5 V. During voltage transitions, OE#, WP#/ACC, and RESET# may oversho ot V for periods of up to 20 ns. See Figure 7. Maximum DC input voltage on pin R ESET# is +12.5 V whi ch may overshoot to +14.0 V for periods up to 20 ns. Maximum DC input voltage on WP#/ACC is +9.5 V which may overshoot to +12.0 V for periods up to 20 ns.

3. No more than one output may be shorted to ground at a time. Duration of the short circuit should not be greater than one second.

Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only; fu nctional o perati on of the dev ice at these or any other conditions above those indicated in the operational sections of this d ata sheet is not implied. Exposure of the d evice to absolute maximum rating conditions for extended periods may affect device reliability.

to –2.0 V for periods of up to 20 ns.

+2.0 V for periods up to 2 0 ns. See

°C to +125°C

°C to +85°C

+0.5 V

+0.5 V.

to –2.0 V

OPERATING RANGES

Industrial (I) Devices

Ambient Temper a tur e (T

f/VCCs Supply Voltage

f/VCCs for standard voltage range. . 2.7 V to 3.3 V

Operating ranges de fine those limits between which the functionality of the device is guaranteed.

) . . . . . . . . .–25°C to +85°C

Figure 7. Maximum Negative

Overshoot Waveform

32 DS42516

+2.0 V

+0.5 V

2.0 V

20 ns

Figure 8. Maximum Positive

Overshoot Waveform

DC CHARACTERISTICS CMOS Compatible

Parameter

Symbol

LIT

LIA

CC1

CC2

fFlash VCC Standby Current (Note 2)

CC3

fFlash VCC Reset Current (Note 2)

CC4

CC5

CC6

CC7

CC8

Parameter Description Test Conditions Min Typ Max Unit

= VSS to VCC,

Input Load Current RESET# Input Load Current VCC = V Output Leakage Current

ACC Input Leakage Current

Flash V

Active Read Current

(Notes 1, 2)

Flash V

Active Write Current

(Notes 2, 3)

Flash V

Current Automatic Sleep

Mode (Notes 2, 4) Flash V

Active

Read-While-Program Curren t (Notes 1, 2)

Flash V

Active Read-While-Erase

Current (Notes 1, 2) Flash V

Active

Program-While-Erase-Suspended

= VCC

OUT

WP#/ACC = V

max

; RESET# = 12.5 V 35 µA

CC max

= VSS to VCC,

= V

CC max

= V

CC max

ACC max

CE#f = VIL, OE# = VIH, Byte Mode

CE#f = V

OE# = VIH,

IL,

Word Mode

CE#f = V

f = V

WP#/ACC = V

f = V

OE# = VIH, WE# = V

IL,

, CE#f, RESET#,

CC max

f ± 0.3 V

, RESET# = V

0.3 V, WP#/ACC = V VCCf = V

= V

CE#f = V

CC max

± 0.3 V

IL,

, OE# = V

, OE#f = V

, VIH = V

OE# = V

5 MHz 10 16 1 MHz 2 4 5 MHz 10 16 1 MHz 2 4

15 30 mA

0.2 5 µA

f ± 0.3 V

± 0.3 V;

0.2 5 µA

Byte 21 45

Word 21 45

Byte 21 45

Word 21 45

17 35 mA

Current (Notes 2, 5) ACC Accelerated Program Current,

Word or Byte

sSRAM VCC Active Current

sSRAM VCC Standby Current

CE#f = V

CE1#s = V CE2s = V

s = V

, OE# = V

CC max

CE1#s = 0.2 V, CE2s = V

1) CE1#s = V

2) CE2s = V CE1#s ≥ V

s – 0.2V

s – 0.2V , CE2s ≥

, CE2s = V

sSRAM VCC Standby Current CE2s ≤ 0.2V 12 µA

Input Low Voltage –0.2 0.8 V

Input High Voltage 2.4 VCC + 0.2 V

I I

ACC

CC1

CC2

CC3

CC4

CC5

V V

ACC pin 5 10 mA

pin 15 30 mA

10 MHz 45 mA

10 MHz 45

1 MHz 5

±1.0 µA

35 µA

0.3 mA

12 µA

DS42516 33

DC CHARACTERISTICS (Continued) CMOS Compatible

Parameter

Symbol

Parameter Description Test Conditions Min Typ Max Unit

Voltage for WP#/ACC Program

Acceleration and Sector

Protection/Unprotection Voltage for Sector Protection,

Autoselect and Temporary Sector

Unprotect

= 4.0 mA, VCCf = VCCs =

OH1

OH2

LKO

Output Low Voltage

Output Hi gh Voltage

Flash Low VCC Lock-Out Voltage (Note 5)

CC min

= –2.0 mA, VCCf = VCCs =

CC min

IOH = –100 µA, VCC = V

CC min

Notes:

1. The I

2. Maximum I

current listed is typically less than 2 mA/MHz, with OE# at VIH.

specifications are tested with VCC = VCCmax.

3. ICC active while Embedded Erase or Embedded Program is in progress.

4. Automatic sleep mode enables the low power mode when addresses remain stable for t 200 nA.

5. Not 100% tested.

8.5 9.5 V

8.5 12.5 V

0.45 V

0.85 x V

VCC–0.4

2.3 2.5 V

+ 30 ns. Typical sleep mode current is

ACC

SRAM DC AND OPERATING CHARACTERISTICS

Parameter

Symbol

s Average Operating Current

CC1

s Average Operating Current

CC2

SB1

Parameter Description Test Conditions Min Typ Max Unit

Input Leakage Current VIN = VSS to V Output Leakage Current

Operating Power Supply Current

CE1#s = V

or WE# = VIL, VIO= VSS to V

= 0 mA, CE1#s = VIL, CE2s =

WE# = V

, CE2s = VIL or OE# =

, VIN = VIH or V

Cycle time = 1 µs, 100% duty,

= 0 mA, CE1#s ≤ 0.2 V,

CE2 ≥ V V

≥ VCC – 0.2 V

– 0.2 V, VIN ≤ 0.2 V or

Cycle time = Min., I 100% duty, CE1#s = V V

, VIN = VIL = or V

Output Low Voltage IOL = 2.1 mA 0.4 V Output Hi gh Voltage IOH = –1.0 mA 2.4 V

Standby Current (TTL)

CE1#s = V inputs = V

CE2 = VIL, Other

IH,

or V

CE1#s ≥ VCC – 0.2 V, CE2 ≥ VCC –

Standby Current (CMOS)

0.2 V (CE1#s controlled) or CE2 ≤

0.2 V (CE2s controlled), CIOs = or VCC, Other input = 0 ~ V

= 0 mA,

, CE2s =

–1.0 1.0 µA –1.0 1.0 µA

3mA

5mA

45 mA

0.3 mA

12 µA

34 DS42516

DC CHARACTERISTICS Zero-Power Flash

Supply Current in mA

0 500 1000 1500 2000 2500 3000 3500 4000

Time in ns

Note: Addresses are switching at 1 MHz

Figure 9. I

Current vs. Time (Showing Active and Automatic Sleep Currents)

CC1

Supply Current in mA

3.3 V

2.7 V

1 2345

Note: T = 25 °C

Frequency in MHz

Figure 10. Typical I

DS42516 35

vs. Frequency

CC1

TEST CONDITIONS

2.7 kΩ

6.2 kΩ

3.3 V

Device

Under

Test

Note: Diodes are IN3064 or equivalent

Figure 11. Test Setup

Table 14. Test Specifications

Test Condition 90 ns Unit

Output Load 1 TTL gate

KEY TO SWITCHING WAVEFORMS

WAVEFORM INPUTS OUTPUTS

Output Load Capacitance, C (including jig capacitance)

Input Rise and Fall Times 5 ns Input Pulse Levels 0.0–3.0 V Input timing measurement reference

levels Output timing measurement

reference levels

Steady

Changing from H to L

Changing from L to H

30 pF

1.5 V

3.0 V

0.0 V

Don’t Care, Any Change Permitted Changing, State Unknown

Does Not Apply Center Line is High Impedance State (High Z)

KS000010-PAL

1.5 V 1.5 V

OutputMeasurement LevelInput

Figure 12. Input Waveforms and Measurement Levels

36 DS42516

AC CHARACTERISTICS SRAM CE#s Timing

Parameter

Speed

T est Setup

JEDEC Std 90

— t

Description

CE#s Recover Time — Min 0 ns

CCR

E#f

CCR

E1#s

CCR

E2s

Figure 13. Timing Diagram for Alternating Between SRAM to Flash

Unit

DS42516 37

AC CHARACTERISTICS Flash Read-Only Operations

Parameter

90 ns Speed

Test Setup

JEDEC Std Min Max

AVAV

AVQV

ELQV

GLQV

EHQZ

GHQZ

AXQX

Description

Read Cycle Time (Note 1) 90 ns

Address to Output Delay CE#f, OE# = V

ACC

Chip Enable to Output Delay OE# = V

Output Enable to Output Delay 40 ns

Chip Enable to Output High Z (Note 1) 16 ns

Output Enable to Output High Z (Note 1) 16 ns

Output Hold Time From Addresses, CE#f or OE#,

Whichever Occurs First

0ns

Read 0 ns

Output Enable Ho ld Time

OEH

(Note 1)

Toggle and Data# Polling

10 ns

Notes:

1. Not 100% tested.

2. See Figure 11 and Table 14 for test specifications.

Unit

90 ns 90 ns

Addresses

CE#f

OE#

WE#

Outputs

RESET#

RY/BY#

0 V

Addresses Stable

ACC

OEH

HIGH Z

Figure 14. Read Operation Timings

Output Valid

HIGH Z

38 DS42516

AC CHARACTERISTICS Hardware Reset (RESET#)

Parameter

JEDEC Std

Ready

RESET# Pin Low (During Embedded Algorithms) to Read Mode (See Note)

RESET# Pin Low (NOT During Embedded Algorithms) to Read Mode (See Note)

RESET# Pulse Width Min 500 ns

Reset High Time Before Read (See Note) Min 50 ns

RESET# Low to Standby Mode Min 20 µs

RPD

RY/BY# Recovery Time Min 0 ns

Note: Not 100% tested.

RY/BY#

CE#f, OE#

RESET#

Description 90 ns Unit

Max 20 µs

Max 500 ns

Ready

Reset Timings NOT during Embedded Algorithms

Reset Timings during Embedded Algorithms

Ready

RY/BY#

CE#f, OE#

RESET#

Figure 15. Reset Timings

DS42516 39

AC CHARACTERISTICS Flash Word/Byte Configuration (CIOf)

Parameter 90 ns Speed

JEDEC Std Description Min Typ Max Unit

ELFL/tELFH

FLQZ

FHQV

CIOf

Switching

from word

to byte

mode

CE#f to CIOf Switching Low or High 5 ns CIOf Switching Low to Output HIGH Z 30 ns CIOf Switching High to Output Active 90 ns

CE#f

OE#

CIOf

DQ0–DQ14

DQ15/A-1

ELFL

ELFH

Data Output

(DQ0–DQ14)

DQ15

Output

FLQZ

Data Output (DQ0–DQ7)

Address

Input

CIOf

Switching

from byte

to word

DQ0–DQ14

Data Output (DQ0–DQ7)

mode

DQ15/A-1

Address

Input

FHQV

Figure 16. CIOf Timings for Read Operations

CE#f

The falling edge of the last WE# signal

WE#

CIOf

SET

(tAS)

HOLD

(tAH)

Note: Refer to the Erase/Program Operations table for tAS and tAH specifications.

Figure 17. CIOf Timings for Write Operations

Data Output

(DQ0–DQ14)

DQ15

Output

40 DS42516

AC CHARACTERISTICS Flash Erase and Program Operations

Parameter 90 ns Speed

JEDEC Std Description Min Typ Max

AVAV

AVWL

WLAX

DVWH

WHDX

ASO

AHT

t t

Write Cycle Time (Note 1) 90 ns Address Setup Time (WE# to Address) 0 ns

Address Setup Time to OE# or CE#f Low During Toggle Bit Polling

Address Hold Time (WE# to Address) 45 ns

Address Hold T ime From CE#f or OE# High D uring Toggle Bit Polling

Data Setup Time 45 ns

Data Hold Time 0 ns

15 ns

0ns

Read 0 ns

GHEL

GHWL

WLEL

ELWL

EHWH

WHEH

WLWH

ELEH

WHDL

OEH

OEPH

GHEL

GHWL

WPH

SR/W

OE# Hold Time

Toggle and Data# Polling 10 ns Output Enable High During Toggle Bit Polling 20 20 20 ns Read Recovery Time Before Write (OE# High to CE#f Low) 0 ns Read Recovery Time Before Write (OE# High to WE# Low) 0 ns WE# Setup Time (CE#f to WE#) 0 ns CE#f Setup Time (WE# to CE#f) 0 ns

WE# Hold Time (CE#f to WE#) 0 ns CE#f Hold Time (CE#f to WE#) 0 ns

Write Pulse Width 35 ns CE#f Pulse Width 35 ns

Write Pulse Width High 30 ns Latency Between Read and Write Operations 0 ns

Byte 5

WHWH1

Programming Operation (Note 2)

Word 7

Unit

µs

WHWH1

WHWH2

WHWH1

WHWH2

VCS

BUSY

Accelerated Programming Operation, Word or Byte (Note 2)

Sector Erase Operation (Note 2) 0.7 sec VCCf Setup Time (Note 1) 50 µs Write Recovery Time From RY/BY# 0 ns

Program/Erase Valid To RY/BY# Delay 90 ns

Notes:

1. Not 100% tested.

2. See the “Flash Erase And Programming Performance” section for more information.

DS42516 41

4µs

AC CHARACTERISTICS

Addresses

CE#f

OE#

WE#

Data

RY/BY#

Program Command Sequence (last two cycles)

PA PA

WPH

BUSY

555h

GHWL

A0h

Read Status Data (last two cycles)

WHWH1

Status

OUT

VCS

otes:

. PA = program address, PD = program data, D . Illustration shows device in word mod e.

Figure 18. Program Operation Timings

or V

WP#/ACC

IH V

VHH

Figure 19. Accelerated Program Timing Diagram

is the true data at the program address.

OUT

VHH

or V

42 DS42516

AC CHARACTERISTICS

Erase Command Sequence (last two cycles) Read Status Data

555h for chip erase

Addresses

2AAh SA

CE#f

GHWL

OE#

WE#

Data

WPH

30h

10 for Chip Erase

BUSY

55h

WHWH2

Progress

Complete

RY/BY#

VCS

Notes:

1. SA = sector address (for Sector Erase), VA = Valid Address for reading status data (see “Write Operation Status”).

2. These waveforms are for the word mode.

Figure 20. Chip/Sector Erase Operation Timings

DS42516 43

AC CHARACTERISTICS

Addresses

CE#f

OE#

WE#

Data

WPH

Valid PA

Valid

OEH

Valid RA

ACC

SR/W

Valid

Out

Read Cycle

GHWL

Figure 21. Back-to-back Read/Write Cycle Timings

Valid PA

Valid

CE#f Controlled Write CyclesWE# Controlled Write Cycle

CPH

Valid PA

Valid

Addresses

ACC

VA VA

CE#f

OE#

OEH

WE#

DQ7

DQ0–DQ6

BUSY

Complement

Status Data

Complement

Status Data

True

Valid Data

High Z

RY/BY#

Note: VA = Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array data read cycle.

Figure 22. Data# Polling Timings (During Embedded Algorithms)

44 DS42516

AC CHARACTERISTICS

AHT

Addresses

ASO

CE#f

OEH

WE#

OE#

DQ6/DQ2 Valid Data

RY/BY#

Valid Data

(first read) (second read) (stops toggling)

Valid

Status

OEPH

Valid

Status

CEPH

AHT

Valid

Status

Note: VA = Valid address; not required for DQ6. Illustration shows first two status cycle after command sequence, last status read cycle, and array data read cycle

Figure 23. Toggle Bit Timings (During Embedded Algorithms)

Enter

Embedded

Erasing

WE#

Erase

Suspend

Erase Suspend

Suspend Program

Read

Enter Erase

Erase Suspend Program

Erase Suspend

Read

Erase

Resume

Erase

Complete

DQ6

DQ2

Note: DQ2 toggles only when read at an address within an erase-suspended sector. The system may use OE# or CE#f to toggle DQ2 and DQ6.

Figure 24. DQ2 vs. DQ6

DS42516 45

AC CHARACTERISTICS Temporary Sector/Sector Block Unprotect

Parameter

JEDEC Std Description

VID Rise and Fall Time (See Note) Min 500 ns

VIDR

VHH Rise and Fall Time (See Note) Min 250 ns

VHH

RESET# Setup Time for Temporary

RSP

Sector/Sector Block Unprotect RESET# Hold Time from RY/BY# High for

RRB

Temporary Sector/Sector Block Unprotect

Note: Not 100% tested.

RESET#

VSS, VIL, or V

CE#f

VIDR

Min 4 µs

Program or Erase Command Sequence

90 ns Speed Unit

VSS, VIL,

or V

VIDR

WE#

RY/BY#

RSP

RRB

Figure 25. Temporary Sector/Sector Block Unprotect Timing Diagram

46 DS42516

AC CHARACTERISTICS

RESET#

SA, A6,

A1, A0

Valid* Valid* Valid*

Sector/Sector Block Protect or Unprotect Verify

Data

60h 60h 40h

Sector/Sector Block Protect: 150 µs,

Sector/Sector Block Unprotect: 15 ms

1 µs

CE#f

WE#

OE#

* For sector protect, A6 = 0, A1 = 1, A0 = 0. For sector unprotect, A6 = 1, A1 = 1, A0 = 0.

Figure 26. Sector/Sector Block Protect and Unprotect Timing Diagram

Status

DS42516 47

AC CHARACTERISTICS Alternate CE#f Controlled Erase and Program Operations

Parameter 90 ns Speed

JEDEC Std Description Min Typ Max Unit

AVAV

AVWL

ELAX

DVEH

EHDX

GHEL

WLEL

EHWH

ELEH

EHEL

WHWH1

ASO

AHT

GHEL

CPH

WHWH1

Write Cycle Time (Note 1) 90 ns Address Setup Time (WE# to Address) 0 ns Address Setup Time to CE#f Low During Toggle

Bit Polling

15 ns

Address Hold Time 45 ns Address Hold time from CE# f or O E# High Duri ng

Toggle Bit Polling

0ns

Data Setup Time 45 ns Data Hold Time 0 ns Read Recovery Time Before Write

(OE# High to WE# Low)

0ns

WE# Setup Time 0 ns WE# Hold Time 0 ns CE#f Pulse Width 35 ns CE#f Pulse Width High 35 ns

Programming Operation (Note 2)

Accelerated Programming Operation, Word or Byte (Note 2)

Byte 5

µs

Word 7

4µs

WHWH2

Sector Erase Operation (Note 2) 0.7 sec

Notes:

1. Not 100% tested.

2. See the “Flash Erase And Programming Performance” section for more information.

48 DS42516

AC CHARACTERISTICS

Addresses

WE#

OE#

CE#f

Data

RESET#

555 for program 2AA for erase

PA for program SA for sector erase 555 for chip erase

GHEL

CPH

A0 for program 55 for erase

BUSY

PD for program 30 for sector erase 10 for chip erase

Data# Polling

WHWH1 or 2

DQ7# D

OUT

RY/BY#

Notes:

1. Figure indicates last two bus cycles of a program or erase operation.

2. PA = program address, SA = sector address, PD = program data.

3. DQ7# is the complement of the data written to the device. D

is the data written to the device.

OUT

4. Waveforms are for the word mode.

Figure 27. Flash Alternate CE#f Controlled Write (Erase/Program) Operation Timings

DS42516 49

AC CHARACTERISTICS SRAM Read Cycle

Parameter

Symbol

, t

CO1

CO2

, t

LZ1

LZ2

BLZ

OLZ

, t

HZ1

HZ2

BHZ

OHZ

Description Min Max Unit

Read Cycle T ime 85 ns Address Access Time 85 ns Chip Enable to Output 85 ns Output Enable Access Time 45 ns LB#s, UB#s to Valid Output 85 ns Chip Enable (CE1#s Low and CE2s High) to Low-Z Output 10 ns UB#, LB# Enable to Low-Z Output 10 ns Output Enable to Low-Z Output 5 ns Chip disable to High-Z Outpu t 0 25 ns UB#s, LB#s Disable to High-Z Output 0 25 ns Output Disable to High-Z Output 0 25 ns Output Data Hold from Address Change 15 ns

ddress

ata Out Previous Data Valid

Data Valid

Note: CE1#s = OE# = VIL, CE2s = WE# = VIH, UB#s and/or LB#s = V

Figure 28. SRAM Read Cycle—Address Contr olled

50 DS42516

AC CHARACTERISTICS

Address

CS#1

CO1

CS2

UB#, LB#

OE#

Data Out

High-Z

Figure 29. SRAM Read Cycle

Notes:

1. WE# = V and t

2. t

voltage levels.

3. At any given temperature and voltage condition, t

interconnection.

, if CIOs is low, ignore UB#s/LB#s timing.

are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output

OHZ

CO2

OLZ

BLZ

(Max.) is less than tLZ (Min.) both for a given device and from device to device

Data Valid

OHZ

BHZ

DS42516 51

AC CHARACTERISTICS SRAM Write Cycle

Parameter

Symbol

WHZ

Address

CS1#s

CS2s

UB#s, LB#s

Description Min Max Unit

Write Cycle Time 85 ns Chip Enable to End of Write 70 ns Address Setup Time 0 ns Address Valid to End of Write 70 ns UB#s, LB#s to End of Write 70 ns Write Pulse Time 60 ns Write Recovery Time 0 ns Write to Output High-Z 0 25 ns Data to Write Time Overlap 35 ns Data Hold from Write Time 0 ns End Write to Output Low-Z 5 ns

(See Note 1)

(See Note 2)

(See Note 1)

WE#

Data In

Data Out

(See Note 3)

High-Z

Data Undefined

(See Note 4)

Data Valid

High-Z

Notes:

1. WE# controlled, if CIOs is low, ignore UB#s and LB#s timing.

is measured from CE1#s going low to the end of write.

2. t

3. t

is measured from the end of write to the address change. tWR applied in case a write ends as CE1#s or WE# going high.

4. tAS is measured from the address valid to the beginning of write.

5. A write occurs during the overlap (tWP) of low CE#1 and low WE#. A write begins when CE1#s goes low and WE# goes low when

asserting UB#s or LB#s for a single byte operation or simultaneously asserting UB#s and LB#s for a double byte operation. A write ends at the earliest transition when CE1#s goes high and WE# goes high. The t

is measured from the beginning of write

to the end of write.

Figure 30. SRAM Write Cycle—WE# Control

52 DS42516

AC CHARACTERISTICS

Address

CE1#s

CE2s

UB#s, LB#s

WE#

Data In

(See Note 2 )

(See Note 3)

(See Note 5)

Data Valid

(See Note 4)

Data Out

High-Z High-Z

Notes:

1. CE1#s controlled, if CIOs is low, ignore UB#s and LB#s timing.

is measured from CE1#s going low to the end of write.

2. t

3. tWR is measured from the end of write to the address change. tWR applied in case a write ends as CE1#s or WE# going high.

4. t

is measured from the address valid to the beginning of write.

5. A write occurs during the overlap (tWP) of low CE#1 and low WE#. A write begins when CE1#s goes low and WE# goes low when

Figure 31. SRAM Write Cycle—CE1#s Control

DS42516 53

AC CHARACTERISTICS

Address

CE1#s

CE2s

UB#s, LB#s

WE#

Data In

(See Note 4)

(See Note 2)

(See Note 5)

Data Valid

(See Note 3)

Data Out

High-Z

Notes:

1. UB#s and LB#s controlled, CIOs must be high.

is measured from CE1#s going low to the end of write.

2. t

3. tWR is measured from the end of write to the address change. tWR applied in case a write ends as CE1#s or WE# going high.

4. t

is measured from the address valid to the beginning of write.

5. A write occurs during the overlap (tWP) of low CE#1 and low WE#. A write begins when CE1#s goes low and WE# goes low when

Figure 32. SRAM Write Cycle—UB#s and LB#s Control

54 DS42516

Flash Erase And Programming Performance

Parameter Typ (Note 1) Max (Note 2) Unit Comments

Sector Erase Time 0.7 15 sec Chip Erase Time 49 sec

Excludes 00h programming

prior to erasure (Note 4)

Byte Program Time 5 150 µs Word Program Time 7 210 µs Accelerated Byte/Word Program Time 4 120 µs

Chip Program Time (Note 3)

Byte Mode 21 63

sec

Word Mode 14 42

Excludes system lev el

overhead (Note 5)

Notes:

1. Typical program and erase times assume the following conditions: 25°C, 3.0 V V

, 1,000,000 cycles. Additi ona lly,

programming typicals assume checkerboard pattern.

2. Under worst case conditions of 90°C, V

= 2.7 V, 1,000,000 cycles.

3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes

program faster than the maximum program times listed.

4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure.

5. System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command. See Table

12 for further information on command definitions.

6. The device has a minimum erase and program cycle endurance of 1,000,000 cycles.

FLASH LATCHUP CHARACTERISTICS

Description Min Max

Input voltage with respect to V (including OE#, and RESET#)

Input voltage with respect to V

on all pins except I/O pins

on all I/O pins –1.0 V VCC + 1.0 V

–1.0 V 12.5 V

VCC Current –100 mA +100 mA

Note: Includes all pins except VCC. Test conditions: VCC = 3.0 V, one pin at a time.

PACKAGE PIN CAPACITANCE

Parameter

Symbol Description

OUT

IN2

IN3

Input Capacitance VIN = 0 11 14 p F Output Capacitance V Control Pin Capacitance VIN = 0 14 16 pF WP#/ACC Pin Capacitance VIN = 0 17 20 pF

Note: 7.Test conditions TA = 25°C, f = 1.0 MHz.

T est Setup Typ Max Unit

= 0 12 16 pF

OUT

FLASH DATA RETENTION

Parameter Description Test Conditions Min Unit

Minimum Pattern Data Retention Time

150°C10Years 125°C20Years

DS42516 55

SRAM DATA RETENTION

Parameter

Symbol

SDR

RDR

Parameter Description

Test Setup

Min Typ Max Unit

VCC for Data Retention CS1#s ≥ VCC – 0.2 V (See Note) 1.5 3.3 V

= 1.5 V, CE1#s ≥ VCC – 0.2 V

Data Retention Current Data Retention Set-Up Time

(See Note)

0.5 5 µA

0ns

See data retention waveforms

Recovery Time t

Note: CE1#s ≥ VCC – 0.2 V, CE 2s ≥ VCC – 0.2 V (CE1#s controlled) or CE2s ≤ 0.2 V (CE2s controlled), CIOs = VSS or VCC.

SDR

Data Retention Mode

RDR

2.7V

2.2V V

CE1#s

≥

CE1#s GND

VCC - 0.2 V

Figure 33. CE1#s Controlled Data Retention Mode

2.7 V CE2s

0.4 V GND

Data Retention Mode

SDR

CE2s £ 0.2 V

Figure 34. CE2s Controlled Data Retention Mode

RDR

56 DS42516

PHYSICAL DIMENSIONS FLB073—73-Ball Fine-Pitch Grid Array 8 x 11 mm

DS42516 57

REVISION SUMMARY Revision A (October 9, 2000)

Initial release as Preliminary Draft.

Revision B (March 8, 2001)

Global

Deleted Preliminary status from document. Added table of contents.

Flash Memory Block Diagram

Added OE# and BYTE# inputs to lower ban k secti on.

Sector/Sector Block Protection/Unprotection

Added to se cond par agrap h: “Note that the secto r u nprotect algorithm unprotects all sectors in parallel. All previously protected sectors must be individually re-protected. To change data in protected sectors efficiently, the temporary sector unprotect function is

available. See “Temporary Sector/Sector Block Unprotect”.”

Customer Lockable: SecSi Sector NOT Programmed or Protected At the Factory

Added to end of first parag raph: “Note that the accelerated programming (ACC) and unlock bypass functions are not available wh en pro gram ming t he SecS i Se cto r.”

Common Flash Memory Interface (CFI)

Added to second paragraph: “The CFI Query mode is not accessible when the device is executing an Embedded Program or embedded erase algorithm.”

Command Definitions

Tabl e 12, Comm and Defi nitions : The SecSi Sector Indicator Bit values have changed from 80h and 00h to 81h and 01h, respectively.

Revision B+1 (March 15, 2001)

Added “Am29DL324D Bottom Boot” to the product description on the top portion of the first page.

‘

Trademarks

Copyright © 2001 Advanced Micro Devices, Inc. All rights reserved. AMD, the AMD logo, and combinations thereof are registered trademarks of Advanced Micro Devices, Inc. ExpressFlash is a trademark of Advanced Micro Devices, Inc. Product names used in this publication are for identification purposes only and may be trademarks of their respective companies.

58 DS42516

AMD DS42516 Service Manual

Specifications and Main Features

Frequently Asked Questions

User Manual