Preliminary Information
TM
AMD Athlon XP
Processor Model 8
Data Sheet
Publication # 25175 Rev. H
Issue Date: March 2003
Preliminary Information
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Preliminary Information
25175H—March 2003 AMD Athlon™ XP Processor Model 8 Data Sheet
Contents
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1 QuantiSpeed™ Architecture Summary. . . . . . . . . . . . . . . . . . . 2
2 Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.2 Signaling Technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.3 Push-Pull (PP) Drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.4 AMD Athlon™ System Bus Signals . . . . . . . . . . . . . . . . . . . . . . 6
3 Logic Symbol Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
4 Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
4.1 Power Management States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Working State. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Halt State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Stop Grant States. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Probe State. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.2 Connect and Disconnect Protocol . . . . . . . . . . . . . . . . . . . . . . 12
Connect Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Connect State Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.3 Clock Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5 CPUID Support. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
6 Advanced 266 Front-Side Bus AMD Athlon™ XP
Processor Model 8 Specifications . . . . . . . . . . . . . . . . . . . . . . . 21
6.1 Part-Specific Electrical and Thermal Specifications
for Advanced 266 FSB AMD Athlon XP Processors
Model 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
6.2 Advanced 266 FSB AMD Athlon XP Processor Model 8
SYSCLK and SYSCLK# AC Characteristics . . . . . . . . . . . . . . 24
6.3 Advanced 266 FSB AMD Athlon System Bus
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
7 Advanced 333 Front-Side Bus AMD Athlon™ XP
Processor Model 8 Specifications . . . . . . . . . . . . . . . . . . . . . . . 27
7.1 Electrical and Thermal Specifications for the Advanced
333 FSB AMD Athlon XP Processor Model 8 . . . . . . . . . . . . . 27
7.2 Advanced 333 FSB AMD Athlon XP Processor Model 8
SYSCLK and SYSCLK# AC Characteristics . . . . . . . . . . . . . . 28
7.3 Advanced 333 FSB AMD Athlon System Bus
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table of Contents 3
Preliminary Information
AMD Athlon™ XP Processor Model 8 Data Sheet 25175H— March 2003
8 Electrical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
8.1 Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
8.2 Interface Signal Groupings . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
8.3 Voltage Identification (VID[4:0]) . . . . . . . . . . . . . . . . . . . . . . 33
8.4 Frequency Identification (FID[3:0]) . . . . . . . . . . . . . . . . . . . . 33
8.5 VCCA AC and DC Characteristics. . . . . . . . . . . . . . . . . . . . . . 33
8.6 Decoupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
8.7 V
8.8 Absolute Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
8.9 SYSCLK and SYSCLK# DC Characteristics . . . . . . . . . . . . . . 37
8.10 AMD Athlon System Bus DC Characteristics . . . . . . . . . . . . . 38
8.11 General AC and DC Characteristics . . . . . . . . . . . . . . . . . . . . 39
8.12 Open-Drain Test Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
8.13 Thermal Diode Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 42
8.14 APIC Pins AC and DC Characteristics . . . . . . . . . . . . . . . . . . 44
CC_CORE
Thermal Diode Electrical Characteristics. . . . . . . . . . . . . 42
Thermal Protection Characterization . . . . . . . . . . . . . . . . 43
Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
9 Signal and Power-Up Requirements . . . . . . . . . . . . . . . . . . . . 45
9.1 Power-Up Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Signal Sequence and Timing Description . . . . . . . . . . . . . 45
Clock Multiplier Selection (FID[3:0]) . . . . . . . . . . . . . . . . 48
9.2 Processor Warm Reset Requirements. . . . . . . . . . . . . . . . . . . 48
Northbridge Reset Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
10 Mechanical Data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
10.1 Die Loading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
10.2 Part Number 27291 OPGA Package Dimensions for
AMD Athlon XP Processors Model 8 with a
CPUID of 680 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
10.3 Part Number 27291 OPGA Package Dimensions for
AMD Athlon XP Processors Model 8 with a
CPUID of 681 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
10.4 Part Number 27648 OPGA Package Dimensions for
AMD Athlon XP Processors Model 8 with a
CPUID of 681 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
11 Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
11.1 Pin Diagram and Pin Name Abbreviations. . . . . . . . . . . . . . . 55
11.2 Pin List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
11.3 Detailed Pin Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
A20M# Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
AMD Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
AMD Athlon System Bus Pins . . . . . . . . . . . . . . . . . . . . . . 74
Analog Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
APIC Pins, PICCLK, PICD[1:0]# . . . . . . . . . . . . . . . . . . . . 74
CLKFWDRST Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
4 Table of Contents
Preliminary Information
25175H—March 2003 AMD Athlon™ XP Processor Model 8 Data Sheet
CLKIN, RSTCLK (SYSCLK) Pins. . . . . . . . . . . . . . . . . . . . 74
CONNECT Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
COREFB and COREFB# Pins . . . . . . . . . . . . . . . . . . . . . . . 75
CPU_PRESENCE# Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
DBRDY and DBREQ# Pins . . . . . . . . . . . . . . . . . . . . . . . . . 75
FERR Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
FID[3:0] Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
FSB_Sense[1:0] Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
FLUSH# Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
IGNNE# Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
INIT# Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
INTR Pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
JTAG Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
K7CLKOUT and K7CLKOUT# Pins. . . . . . . . . . . . . . . . . . 78
Key Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
NC Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
NMI Pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
PGA Orientation Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
PLL Bypass and Test Pins . . . . . . . . . . . . . . . . . . . . . . . . . . 78
PWROK Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
SADDIN[1:0]# and SADDOUT[1:0]# Pins. . . . . . . . . . . . . 79
Scan Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
SMI# Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
STPCLK# Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
SYSCLK and SYSCLK#. . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
THERMDA and THERMDC Pins. . . . . . . . . . . . . . . . . . . . 79
VCCA Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
VID[4:0] Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
VREFSYS Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
ZN and ZP Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
12 Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Standard AMD Athlon XP Processor Model 8 Products . . . . . . . . . . 81
Appendix A Thermal Diode Calculations . . . . . . . . . . . . . . . . . . . . . 83
Appendix A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Ideal Diode Equation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Temperature Offset Correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Appendix B Conventions and Abbreviations . . . . . . . . . . . . . . . . . . 87
Signals and Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Data Terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Abbreviations and Acronyms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Related Publications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Table of Contents 5
Preliminary Information
AMD Athlon™ XP Processor Model 8 Data Sheet 25175H— March 2003
6 Table of Contents
Preliminary Information
25175H—March 2003 AMD Athlon™ XP Processor Model 8 Data Sheet
List of Figures
Figure 1. Typical AMD Athlon™ XP Processor Model 8 System
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Figure 2. Logic Symbol Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 3. AMD Athlon XP Processor Model 8 Power Management
States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 4. AMD Athlon System Bus Disconnect Sequence in the
Stop Grant State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 5. Exiting the Stop Grant State and Bus Connect Sequence . . . . 15
Figure 6. Northbridge Connect State Diagram . . . . . . . . . . . . . . . . . . . . . 16
Figure 7. Processor Connect State Diagram . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 8. SYSCLK Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 9. SYSCLK Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 10. V
Figure 11. SYSCLK and SYSCLK# Differential Clock Signals . . . . . . . . . 37
Figure 12. General ATE Open-Drain Test Circuit. . . . . . . . . . . . . . . . . . . . 41
Figure 13. Signal Relationship Requirements During Power-Up
Figure 14. AMD Athlon XP Processor Model 8 Part Number
Figure 15. AMD Athlon XP Processor Model 8 Part Number
Figure 16. AMD Athlon XP Processor Model 8 Pin Diagram
Figure 17. AMD Athlon XP Processor Model 8 Pin Diagram
Figure 18. OPN Example for the AMD Athlon XP Processor
CC_CORE
Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
27291 OPGA Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
27648 OPGA Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
—Topside View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
—Bottomside View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Model 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Voltage Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
List of Figures 7
Preliminary Information
AMD Athlon™ XP Processor Model 8 Data Sheet 25175H— March 2003
8 List of Figures
Preliminary Information
25175H—March 2003 AMD Athlon™ XP Processor Model 8 Data Sheet
List of Tables
Table 1. Electrical and Thermal Specifications for Processors
with a CPUID of 680. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 2. Electrical and Thermal Specifications for Processors
with a CPUID of 681. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 3. SYSCLK and SYSCLK# AC Characteristics . . . . . . . . . . . . . . . 24
Table 4. AMD Athlon™ System Bus AC Characteristics . . . . . . . . . . . . 25
Table 5. Electrical and Thermal Specifications. . . . . . . . . . . . . . . . . . . . 27
Table 6. SYSCLK and SYSCLK# AC Characteristics . . . . . . . . . . . . . . . 28
Table 7. AMD Athlon System Bus AC Characteristics . . . . . . . . . . . . . . 29
Table 8. Interface Signal Groupings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 9. VID[4:0] DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 10. FID[3:0] DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 11. VCCA AC and DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . 33
Table 12. V
Table 13. Absolute Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 14. SYSCLK and SYSCLK# DC Characteristics . . . . . . . . . . . . . . . 37
Table 15. AMD Athlon System Bus DC Characteristics . . . . . . . . . . . . . . 38
Table 16. General AC and DC Characteristics. . . . . . . . . . . . . . . . . . . . . . 39
Table 17. Thermal Diode Electrical Characteristics . . . . . . . . . . . . . . . . . 42
Table 18. Guidelines for Platform Thermal Protection of the
Table 19. APIC Pin AC and DC Characteristics. . . . . . . . . . . . . . . . . . . . . 44
Table 20. Mechanical Loading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Table 21. Part Number 27291 OPGA Package Dimensions
Table 22. Part Number 27291 OPGA Package Dimensions
Table 23. Part Number 27648 OPGA Package Dimensions
CC_CORE
Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
for AMD Athlon XP Processors Model 8 with a
CPUID of 680 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
for AMD Athlon XP Processors Model 8 with a
CPUID of 681 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
for AMD Athlon XP Processors Model 8 with a
CPUID of 681 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
AC and DC Characteristics . . . . . . . . . . . . . . . . . . . . 34
Table 24. Pin Name Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Table 25. Cross-Reference by Pin Location . . . . . . . . . . . . . . . . . . . . . . . . 66
Table 26. FID[3:0] Clock Multiplier Encodings . . . . . . . . . . . . . . . . . . . . . 76
Table 27. Front-Side Bus Sense Truth Table . . . . . . . . . . . . . . . . . . . . . . . 77
List of Tables 9
Preliminary Information
AMD Athlon™ XP Processor Model 8 Data Sheet 25175H— March 2003
Table 28. VID[4:0] Code to Voltage Definition . . . . . . . . . . . . . . . . . . . . . 80
Table 29. Constants and Variables for the Ideal Diode Equation . . . . . . 83
Table 30. Constants and Variables Used in Temperature Offset
Equations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Table 31. Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Table 32. Acronyms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
10 List of Tables
Preliminary Information
25175H—March 2003 AMD Athlon™ XP Processor Model 8 Data Sheet
Revision History
Date Rev Description
Public revision H of the AMD Athlon™ XP Processor Model 8 Data Sheet includes the following
changes:
March 2003 H
March 2003 G
■ In Chapter 6, revised Table 2, “Electrical and Thermal Specifications for Processors with a
CPUID of 681,” on page 23.
■
In Chapter 12, revised Figure 18, “OPN Example for the AMD Athlon™ XP Processor Model 8,”
on page 81.
Public revision G of the AMD Athlon™ XP Processor Model 8 Data Sheet includes the following
changes:
■ In Chapter 6, revised Table 2, “Electrical and Thermal Specifications for Processors with a
CPUID of 681,” on page 23.
■ In Chapter 7, revised Table 6, “SYSCLK and SYSCLK# AC Characteristics,” on page 28.
■ In Chapter 10, renamed Table 21, “Part Number 27291 OPGA Package Dimensions for
AMD Athlon™ XP Processors Model 8 with a CPUID of 680,” on page 50, renamed Table 22,
“Part Number 27291 OPGA Package Dimensions for AMD Athlon™ XP Processors Model 8
with a CPUID of 681,” on page 51, added Table 23, “Part Number 27648 OPGA Package
Dimensions for AMD Athlon™ XP Processors Model 8 with a CPUID of 681,” on page 53,
renamed Figure 14, “AMD Athlon™ XP Processor Model 8 Part Number 27291 OPGA
Package,” on page 52, and added Figure 15, “AMD Athlon™ XP Processor Model 8 Part
Number 27648 OPGA Package,” on page 54.
■
In Chapter 12, revised Figure 18, “OPN Example for the AMD Athlon™ XP Processor Model 8,”
on page 81.
Public revision F of the AMD Athlon™ XP Processor Model 8 Data Sheet includes the following
changes:
December 2002 F
■ In Chapter 6, revised Table 2, “Electrical and Thermal Specifications for Processors with a
CPUID of 681,” on page 23.
■ In Chapter 8, revised Table 16, “General AC and DC Characteristics,” on page 39 and
Figure 12, “General ATE Open-Drain Test Circuit,” on page 41.
Public revision E of the AMD Athlon™ XP Processor Model 8 Data Sheet includes the following
changes:
■ In Chapter 6, revised Table 2, “Electrical and Thermal Specifications for Processors with a
CPUID of 681,” on page 23.
November 2002 E
■ In Chapter 3, revised Figure 2, “Logic Symbol Diagram,” on page 7.
■ In Chapter 7, revised Table 5, “Electrical and Thermal Specifications,” on page 27.
■ In Chapter 8, revised Table 9, “VID[4:0] DC Characteristics,” on page 33.
■
In Chapter 12, revised Figure 18, “OPN Example for the AMD Athlon™ XP Processor Model 8,”
on page 81.
Revision History 11
Preliminary Information
AMD Athlon™ XP Processor Model 8 Data Sheet 25175H— March 2003
Date Rev Description
Public revision D of the AMD Athlon™ XP Processor Model 8 Data Sheet includes the following
changes:
■ In Chapter 1, revised wording in Overview.
■ In Chapter 6, revised Table 2, “Electrical and Thermal Specifications for Processors with a
CPUID of 681,” on page 23, added Table 3, “SYSCLK and SYSCLK# AC Characteristics,” on
page 24, Figure 8, “SYSCLK Waveform,” on page 24, and Table 4, “AMD Athlon™ System
Bus AC Characteristics,” on page 25.
■ Added Chapter 7, “Advanced 333 Front-Side Bus AMD Athlon™ XP Processor Model 8
Specifications” on page 27, Table 5, “Electrical and Thermal Specifications,” on page 27,
Table 6, “SYSCLK and SYSCLK# AC Characteristics,” on page 28, Figure 9, “SYSCLK
October 2002 D
Waveform,” on page 28, and Table 7, “AMD Athlon™ System Bus AC Characteristics,” on
page 29.
■ In Chapter 8, revised Table 8, “Interface Signal Groupings,” on page 31, Table 9, “VID[4:0]
DC Characteristics,” on page 33, Table 10, “FID[3:0] DC Characteristics,” on page 33, and
Table 19, “APIC Pin AC and DC Characteristics,” on page 44.
■ In Chapter 10, revised Table 21, “Part Number 27291 OPGA Package Dimensions for
AMD Athlon™ XP Processors Model 8 with a CPUID of 680,” on page 50 and Table 22, “Part
Number 27291 OPGA Package Dimensions for AMD Athlon™ XP Processors Model 8 with a
CPUID of 681,” on page 51.
■ In Chapter 12, revised Figure 18, “OPN Example for the AMD Athlon™ XP Processor Model
8,” on page 81.
Public revision C of the AMD Athlon™ XP Processor Model 8 Data Sheet includes the following
changes:
■ In Chapter 3, revised Figure 2, “Logic Symbol Diagram,” on page 7.
■ In Chapter 6, added Table 1, “Electrical and Thermal Specifications for Processors with a
CPUID of 680,” on page 22 and Table 2, “Electrical and Thermal Specifications for
Processors with a CPUID of 681,” on page 23.
■ In Chapter 8, revised Table 8, “Interface Signal Groupings,” on page 31.
■ In Chapter 10, added Table 21, “Part Number 27291 OPGA Package Dimensions for
August 2002 C
AMD Athlon™ XP Processors Model 8 with a CPUID of 680,” on page 50 and Table 22, “Part
Number 27291 OPGA Package Dimensions for AMD Athlon™ XP Processors Model 8 with a
CPUID of 681,” on page 51.
■ In Chapter 11, revised Figure 16, “AMD Athlon™ XP Processor Model 8 Pin Diagram—
Topside View,” on page 56, Figure 17, “AMD Athlon™ XP Processor Model 8 Pin Diagram—
Bottomside View,” on page 57, Table 24, “Pin Name Abbreviations,” on page 58, Table 25,
“Cross-Reference by Pin Location,” on page 66, and added “FSB_Sense[1:0] Pins” on page
77, and Table 27, “Front-Side Bus Sense Truth Table,” on page 77.
■ In Chapter 12, revised Figure 18, “OPN Example for the AMD Athlon™ XP Processor Model
8,” on page 81.
June 2002 B First public release of the AMD Athlon™ XP Processor Model 8 Data Sheet
12 Revision History
Preliminary Information
25175H—March 2003 AMD Athlon™ XP Processor Model 8 Data Sheet
1Overview
The AMD Athlon™ XP processor model 8 with QuantiSpeed™
architecture powers the next generation in computing platforms,
®
delivering extreme performance for Windows
The AMD Athlon™ XP processor model 8, based on leadingedge 0.13 micron technology, integrates the innovative design
and manufacturing expertise of AMD to deliver improved
performance, lower power, and smaller die size while
maintaining the stable and compatible Socket A infrastructure
of the AMD Athlon processor.
Delivered in an OPGA package, the AMD Athlon XP processor
model 8 delivers the integer, floating-point, and 3D multimedia
performance for highly demanding applications running on x86
system platforms. The AMD Athlon XP processor model 8
delivers compelling performance for cutting-edge software
applications that include high-speed Internet capability, digital
content creation, digital photo editing, digital video, image
compression, video encoding for streaming over the Internet,
soft DVD, commercial 3D modeling, workstation-class
computer-aided design (CAD), commercial desktop publishing,
and speech recognition. The AMD Athlon XP processor model 8
also offers the scalability and reliability that IT managers and
business users require for enterprise computing.
XP.
The AMD Athlon XP processor model 8 features a
seventh-generation microarchitecture with an integrated,
exclusive L2 cache, which supports the growing processor and
system bandwidth requirements of emerging software,
graphics, I/O, and memory technologies. The high-speed
execution core of the AMD Athlon XP processor model 8
includes multiple x86 instruction decoders, a dual-ported
128-Kbyte split level-one (L1) cache, an exclusive 256-Kbyte L2
cache, three independent integer pipelines, three address
calculation pipelines, and a superscalar, fully pipelined,
out-of-order, three-way floating-point engine. The floating-point
engine is capable of delivering outstanding performance on
numerically complex applications.
Chapter 1 Overview 1
Preliminary Information
AMD Athlon™ XP Processor Model 8 Data Sheet 25175H—March 2003
The features of the AMD Athlon XP processor model 8 are
QuantiSpeed™ architecture, a high-performance full-speed cache,
an advanced 333 front-side Bus (FSB) with a 2.7-Gigabyte per
second system bus, or an advanced 266 FSB with a 2.1-Gigabyte per
second system bus, and 3DNow!™ Professional technology. The
AMD Athlon system bus combines the latest technological
advances, such as point-to-point topology, source-synchronous
packet-based transfers, and low-voltage signaling to provide an
extremely powerful, scalable bus for an x86 processor.
The AMD Athlon XP processor model 8 is binary-compatible with
existing x86 software and backwards compatible with applications
optimized for MMX™, SSE, and 3DNow! technology. Using a data
format and single-instruction multiple-data (SIMD) operations
based on the MMX instruction model, the AMD Athlon XP
processor model 8 can produce as many as four, 32-bit,
single-precision floating-point results per clock cycle. The 3DNow!
Professional technology implemented in the AMD Athlon XP
processor model 8 includes new integer multimedia instructions
and software-directed data movement instructions for optimizing
such applications as digital content creation and streaming video
for the internet, as well as new instructions for digital signal
processing (DSP) and communications applications.
1.1 QuantiSpeed™ Architecture Summary
The following features summarize the AMD Athlon XP
processor model 8 QuantiSpeed architecture:
■
Advanced 333 FSB technology available
■
An advanced nine-issue, superpipelined, superscalar x86
processor microarchitecture designed for increased instructions
per cycle (IPC) and high clock frequencies
■
Fully pipelined floating-point unit that executes all x87
(floating-point), MMX, SSE and 3DNow! instructions
■
Hardware data pre-fetch that increases and optimizes
performance on high-end software applications utilizing highbandwidth system capabilities
■
Advanced two-level translation look-aside buffer (TLB)
structures for both enhanced data and instruction address
translation. The AMD Athlon XP processor model 8 with
QuantiSpeed architecture incorporates three TLB
optimizations: the L1 DTLB increases from 32 to 40 entries, the
L2 ITLB and L2 DTLB both use exclusive architecture, and the
TLB entries can be speculatively loaded.
2 Overview Chapter 1
Preliminary Information
25175H—March 2003 AMD Athlon™ XP Processor Model 8 Data Sheet
The AMD Athlon XP processor model 8 delivers excellent
system performance in a cost-effective, industry-standard form
factor. The AMD Athlon XP processor model 8 is compatible
with motherboards based on Socket A.
Figure 1 shows a typical AMD Athlon XP processor model 8
system block diagram.
Thermal Monitor
AMD Athlon™ XP
Processor Model 8
AMD Athlon System Bus
AGP Bus
AGP
System Controller
(Northbridge)
Peripheral Bus
Controller
(Southbridge)
Dual EIDE
USB
Memory Bus
PCI Bus
LPC Bus
LAN
Modem / Audio
SDRAM or DDR
SCSI
BIOS
Figure 1. Typical AMD Athlon™ XP Processor Model 8 System Block Diagram
Chapter 1 Overview 3
Preliminary Information
AMD Athlon™ XP Processor Model 8 Data Sheet 25175H—March 2003
4 Overview Chapter 1
Preliminary Information
25175H—March 2003 AMD Athlon™ XP Processor Model 8 Data Sheet
2 Interface Signals
This section describes the interface signals utilized by the
AMD Athlon™ XP processor model 8.
2.1 Overview
The AMD Athlon™ system bus architecture is designed to
deliver excellent data movement bandwidth for nextgeneration x86 platforms as well as the high-performance
required by enterprise-class application software. The system
bus architecture consists of three high-speed channels (a
unidirectional processor request channel, a unidirectional
probe channel, and a 64-bit bidirectional data channel),
source-synchronous clocking, and a packet-based protocol. In
addition, the system bus supports several control, clock, and
legacy signals. The interface signals use an impedance
controlled push-pull, low-voltage, swing-signaling technology
contained within the Socket A socket.
For more information, see “AMD Athlon™ System Bus Signals”
on page 6, Chapter 11, “Pin Descriptions” on page 55, and the
AMD Athlon™ System Bus Specification, order# 21902.
2.2 Signaling Technology
The AMD Athlon system bus uses a low-voltage, swing-signaling
technology, that has been enhanced to provide larger noise
margins, reduced ringing, and variable voltage levels. The
signals are push-pull and impedance compensated. The signal
inputs use differential receivers that require a reference
voltage (V
determine if a signal is asserted or deasserted by the source.
Termination resistors are not needed because the driver is
impedance-matched to the motherboard and a high impedance
reflection is used at the receiver to bring the signal past the
input threshold.
For more information about pins and signals, see Chapter 11,
“Pin Descriptions” on page 55.
REF
). The reference signal is used by the receivers to
Chapter 2 Interface Signals 5
Preliminary Information
AMD Athlon™ XP Processor Model 8 Data Sheet 25175H—March 2003
2.3 Push-Pull (PP) Drivers
The AMD Athlon XP processor model 8 supports push-pull (PP)
drivers. The system logic configures the processor with the
configuration parameter called SysPushPull (1=PP). The
impedance of the PP drivers is set to match the impedance of
the motherboard by two external resistors connected to the ZN
and ZP pins.
See “ZN and ZP Pins” on page 80 for more information.
2.4 AMD Athlon™ System Bus Signals
The AMD Athlon system bus is a clock-forwarded, point-topoint interface with the following three point-to-point channels:
■ A 13-bit unidirectional output address/command channel
■ A 13-bit unidirectional input address/command channel
■ A 72-bit bidirectional data channel
For more information, see Chapter 8, “Electrical Data” on page
31 and the AMD Athlon™ System Bus Specification, order#
21902.
6 Interface Signals Chapter 2
Preliminary Information
25175H—March 2003 AMD Athlon™ XP Processor Model 8 Data Sheet
3 Logic Symbol Diagram
Figure 2 is the logic symbol diagram of the processor. This
diagram shows the logical grouping of the input and output
signals.
Clock
{
SYSCLK#SYSCLK
Data
{
SDATA[63:0]#
SDATAINCLK[3:0]#
SDATAOUTCLK[3:0]#
SDATAINVALID#
SDATAOUTVALID#
SFILLVALID#
VID[4:0]
COREFB
COREFB#
PWROK
FID[3:0]
{
Voltage
Control
Frequency
Control
Probe/SysCMD
Request
Power
Management
and
Initialization
Figure 2. Logic Symbol Diagram
{
{
{
SADDIN[14:2]#
SADDINCLK#
SADDOUT[14:2]#
SADDOUTCLK#
PROCRDY
CLKFWDRST
CONNECT
STPCLK#
RESET#
AMD Athlon™ XP
Processor Model 8
FSB_SENSE[1:0]
FERR
IGNNE#
INIT#
INTR
NMI
A20M#
SMI#
FLUSH#
THERMDA
THERMDC
PICCLK
PICD[1:0]
Front-Side Bus
Autodetect
{
Legacy
{
Thermal
Diode
{
APIC
Chapter 3 Logic Symbol Diagram 7
Preliminary Information
AMD Athlon™ XP Processor Model 8 Data Sheet 25175H—March 2003
8 Logic Symbol Diagram Chapter 3
Preliminary Information
25175H—March 2003 AMD Athlon™ XP Processor Model 8 Data Sheet
4 Power Management
This chapter describes the power management control system
of the AMD Athlon™ XP processor model 8. The power
management features of the processor are compliant with the
ACPI 1.0b and ACPI 2.0 specifications.
4.1 Power Management States
The AMD Athlon XP processor model 8 supports low-power
Halt and Stop Grant states. These states are used by advanced
configuration and power interface (ACPI) enabled operating
systems for processor power management.
Figure 3 shows the power management states of the processor.
The figure includes the ACPI “Cx” naming convention for these
states.
C1
Halt
Incoming Probe
Probe
State
SMI#, INTR, NMI, INIT#, RESET#
P
r
o
b
e
S
e
r
v
i
c
e
d
1
Execute HLT
S
T
P
C
L
S
T
P
C
L
K
#
Incoming Probe
Probe Serviced
C0
4
Working
(Read PLVL2 register
or throttling)
K
#
d
e
a
s
s
e
r
t
a
e
3
s
d
s
e
r
t
e
2
d
Stop Grant
Cache Snoopable
STPCLK# deasserted
STPCLK# asserted
C2
Note: The AMD AthlonTMSystem Bus is connected during the following states:
1) The Probe state
2) During transitions between the Halt state and the C2 Stop Grant state
3) During transitions between the C2 Stop Grant state and the Halt state
4) C0 Working state
S
T
P
C
L
K
S
T
P
C
L
K
#
a
s
#
d
e
a
s
s
e
r
t
e
d
s
e
r
t
e
d
Stop Grant
Cache Not Snoopable
Sleep
Legend
Hardware transitions
Software transitions
S1
Figure 3. AMD Athlon™ XP Processor Model 8 Power Management States
Chapter 4 Power Management 9
Preliminary Information
AMD Athlon™ XP Processor Model 8 Data Sheet 25175H—March 2003
The following sections provide an overview of the power
management states. For more details, refer to the
AMD Athlon™ System Bus Specification, order# 21902.
Note: In all power management states that the processor is
powered, the system must not stop the system clock
(SYSCLK/SYSCLK#) to the processor.
Working State The Working state is the state in which the processor is
executing instructions.
Halt State When the processor executes the HLT instruction, the processor
enters the Halt state and issues a Halt special cycle to the
AMD Athlon system bus. The processor only enters the low
power state dictated by the CLK_Ctl MSR if the system
controller (Northbridge) disconnects the AMD Athlon system
bus in response to the Halt special cycle.
If STPCLK# is asserted, the processor will exit the Halt state
and enter the Stop Grant state. The processor will initiate a
system bus connect, if it is disconnected, then issue a Stop
Grant special cycle. When STPCLK# is deasserted, the
processor will exit the Stop Grant state and re-enter the Halt
state. The processor will issue a Halt special cycle when
re-entering the Halt state.
The Halt state is exited when the processor detects the
assertion of INIT#, RESET#, SMI#, or an interrupt via the INTR
or NMI pins, or via a local APIC interrupt message. When the
Halt state is exited, the processor will initiate an AMD Athlon
system bus connect if it is disconnected.
Stop Grant States The processor enters the Stop Grant state upon recognition of
assertion of STPCLK# input. After entering the Stop Grant
state, the processor issues a Stop Grant special bus cycle on the
AMD Athlon system bus. The processor is not in a low-power
state at this time, because the AMD Athlon system bus is still
connected. After the Northbridge disconnects the AMD Athlon
system bus in response to the Stop Grant special bus cycle, the
processor enters a low-power state dictated by the CLK_Ctl
MSR. If the Northbridge needs to probe the processor during
the Stop Grant state while the system bus is disconnected, it
must first connect the system bus. Connecting the system bus
10 Power Management Chapter 4
Preliminary Information
25175H—March 2003 AMD Athlon™ XP Processor Model 8 Data Sheet
places the processor into the higher power probe state. After
the Northbridge has completed all probes of the processor, the
Northbridge must disconnect the AMD Athlon system bus
again so that the processor can return to the low-power state.
During the Stop Grant states, the processor latches INIT#,
INTR, NMI, SMI#, or a local APIC interrupt message, if they are
asserted.
The Stop Grant state is exited upon the deassertion of
STPCLK# or the assertion of RESET#. When STPCLK# is
deasserted, the processor initiates a connect of the
AMD Athlon system bus if it is disconnected. After the
processor enters the Working state, any pending interrupts are
recognized and serviced and the processor resumes execution
at the instruction boundary where STPCLK# was initially
recognized. If RESET# is sampled asserted during the Stop
Grant state, the processor exits the Stop Grant state and the
reset process begins.
There are two mechanisms for asserting STPCLK#—hardware
and software.
The Southbridge can force STPCLK# assertion for throttling to
protect the processor from exceeding its maximum case
temperature. This is accomplished by asserting the THERM#
input to the Southbridge. Throttling asserts STPCLK# for a
percentage of a predefined throttling period: STPCLK# is
repetitively asserted and deasserted until THERM# is
deasserted.
Software can force the processor into the Stop Grant state by
accessing ACPI-defined registers typically located in the
Southbridge.
The operating system places the processor into the C2 Stop
Grant state by reading the P_LVL2 register in the Southbridge.
If an ACPI Thermal Zone is defined for the processor, the
operating system can initiate throttling with STPCLK# using
the ACPI defined P_CNT register in the Southbridge. The
Northbridge connects the AMD Athlon system bus, and the
processor enters the Probe state to service cache snoops during
Stop Grant for C2 or throttling.
In C2, probes are allowed, as shown in Figure 3 on page 9
Chapter 4 Power Management 11
Preliminary Information
AMD Athlon™ XP Processor Model 8 Data Sheet 25175H—March 2003
The Stop Grant state is also entered for the S1, Powered On
Suspend, system sleep state based on a write to the SLP_TYP
and SLP_EN fields in the ACPI-defined Power Management 1
control register in the Southbridge. During the S1 Sleep state,
system software ensures no bus master or probe activity occurs.
The Southbridge deasserts STPCLK# and brings the processor
out of the S1 Stop Grant state when any enabled resume event
occurs.
Probe State The Probe state is entered when the Northbridge connects the
AMD Athlon system bus to probe the processor (for example, to
snoop the processor caches) when the processor is in the Halt or
Stop Grant state. When in the Probe state, the processor
responds to a probe cycle in the same manner as when it is in
the Working state. When the probe has been serviced, the
processor returns to the same state as when it entered the
Probe state (Halt or Stop Grant state). When probe activity is
completed the processor only returns to a low-power state after
the Northbridge disconnects the AMD Athlon system bus again.
4.2 Connect and Disconnect Protocol
Significant power savings of the processor only occur if the
processor is disconnected from the system bus by the
Northbridge while in the Halt or Stop Grant state. The
Northbridge can optionally initiate a bus disconnect upon the
receipt of a Halt or Stop Grant special cycle. The option of
disconnecting is controlled by an enable bit in the Northbridge.
If the Northbridge requires the processor to service a probe
after the system bus has been disconnected, it must first
initiate a system bus connect.
Connect Protocol In addition to the legacy STPCLK# signal and the Halt and Stop
Grant special cycles, the AMD Athlon system bus connect
protocol includes the CONNECT, PROCRDY, and CLKFWDRST
signals and a Connect special cycle.
AMD Athlon system bus disconnects are initiated by the
Northbridge in response to the receipt of a Halt or Stop Grant.
Reconnect is initiated by the processor in response to an
interrupt for Halt or STPCLK# deassertion. Reconnect is
initiated by the Northbridge to probe the processor.
12 Power Management Chapter 4
Preliminary Information
25175H—March 2003 AMD Athlon™ XP Processor Model 8 Data Sheet
The Northbridge contains BIOS programmable registers to
enable the system bus disconnect in response to Halt and Stop
Grant special cycles. When the Northbridge receives the Halt or
Stop Grant special cycle from the processor and, if there are no
outstanding probes or data movements, the Northbridge
deasserts CONNECT a minimum of eight SYSCLK periods after
the last command sent to the processor. The processor detects
the deassertion of CONNECT on a rising edge of SYSCLK and
deasserts PROCRDY to the Northbridge. In return, the
Northbridge asserts CLKFWDRST in anticipation of
reestablishing a connection at some later point.
Note: The Northbridge must disconnect the processor from the
AMD Athlon system bus before issuing the Stop Grant
special cycle to the PCI bus or passing the Stop Grant special
cycle to the Southbridge for systems that connect to the
Southbridge with HyperTransport™ technology.
This note applies to current chipset implementation—
alternate chipset implementations that do not require this
are possible.
Note: In response to Halt special cycles, the Northbridge passes the
Halt special cycle to the PCI bus or Southbridge
immediately.
The processor can receive an interrupt after it sends a Halt
special cycle, or STPCLK# deassertion after it sends a Stop
Grant special cycle to the Northbridge but before the
disconnect actually occurs. In this case, the processor sends the
Connect special cycle to the Northbridge, rather than
continuing with the disconnect sequence. In response to the
Connect special cycle, the Northbridge cancels the disconnect
request.
The system is required to assert the CONNECT signal before
returning the C-bit for the connect special cycle (assuming
CONNECT has been deasserted).
For more information, see the AMD Athlon™ System Bus
Specification, order# 21902 for the definition of the C-bit and
the Connect special cycle.
Chapter 4 Power Management 13
Preliminary Information
AMD Athlon™ XP Processor Model 8 Data Sheet 25175H—March 2003
Figure 4 shows STPCLK# assertion resulting in the processor in
the Stop Grant state and the AMD Athlon system bus
disconnected.
STPCLK#
AMD Athlon™
System Bus
CONNECT
PROCRDY
CLKFWDRST
Stop Grant
PCI Bus
Stop Grant
Figure 4. AMD Athlon™ System Bus Disconnect Sequence in the Stop Grant State
An example of the AMD Athlon system bus disconnect
sequence is as follows:
1. The peripheral controller (Southbridge) asserts STPCLK#
to place the processor in the Stop Grant state.
2. When the processor recognizes STPCLK# asserted, it enters
the Stop Grant state and then issues a Stop Grant special
cycle.
3. When the special cycle is received by the Northbridge, it
deasserts CONNECT, assuming no probes are pending,
initiating a bus disconnect to the processor.
4. The processor responds to the Northbridge by deasserting
PROCRDY.
5. The Northbridge asserts CLKFWDRST to complete the bus
disconnect sequence.
6. After the processor is disconnected from the bus, the
processor enters a low-power state. The Northbridge passes
the Stop Grant special cycle along to the Southbridge.
14 Power Management Chapter 4
Preliminary Information
25175H—March 2003 AMD Athlon™ XP Processor Model 8 Data Sheet
Figure 5 shows the signal sequence of events that takes the
processor out of the Stop Grant state, connects the processor to
the AMD Athlon system bus, and puts the processor into the
Working state.
STPCLK#
PROCRDY
CONNE CT
CLKFWDRST
Figure 5. Exiting the Stop Grant State and Bus Connect Sequence
The following sequence of events removes the processor from
the Stop Grant state and connects it to the system bus:
1. The Southbridge deasserts STPCLK#, informing the
processor of a wake event.
2. When the processor recognizes STPCLK# deassertion, it
exits the low-power state and asserts PROCRDY, notifying
the Northbridge to connect to the bus.
3. The Northbridge asserts CONNECT.
4. The Northbridge deasserts CLKFWDRST, synchronizing the
forwarded clocks between the processor and the
Northbridge.
5. The processor issues a Connect special cycle on the system
bus and resumes operating system and application code
execution.
Chapter 4 Power Management 15
Preliminary Information
AMD Athlon™ XP Processor Model 8 Data Sheet 25175H—March 2003
Connect State Diagram
Disconnect
Pending
5/B
Disconnect
Figure 6 below and Figure 7 on page 17 show the Northbridge
and processor connect state diagrams, respectively.
4/A
2/A
Connect
3/C
8
Reconnect
Pending
1
Disconnect
Requested
3
8
Probe
Pending 2
7/D,C
6/C 7/D
Condition
1 A disconnect is requested and probes are still pending.
2 A disconnect is requested and no probes are pending.
3 A Connect special cycle from the processor.
4 No probes are pending.
5 PROCRDY is deasserted.
6 A probe needs service.
7 PROCRDY is asserted.
Three SYSCLK periods after CLKFWDRST is deasserted.
Although reconnected to the system interface, the
8
Northbridge must not issue any non-NOP SysDC
commands for a minimum of four SYSCLK periods after
deasserting CLKFWDRST.
Figure 6. Northbridge Connect State Diagram
Probe
Pending 1
Action
Deassert CONNECT eight SYSCLK periods
A
after last SysDC sent.
B Assert CLKFWDRST.
C Assert CONNECT.
D Deassert CLKFWDRST.
16 Power Management Chapter 4
Preliminary Information
25175H—March 2003 AMD Athlon™ XP Processor Model 8 Data Sheet
Connect
6/B
1
2/B
Connect
Pending 2
Disconnect
Pending
5
Connect
Pending 1
3/A
Condition
CONNECT is deasserted by the Northbridge (for a
1
previously sent Halt or Stop Grant special cycle).
Processor receives a wake-up event and must cancel
2
the disconnect request.
3 Deassert PROCRDY and slow down internal clocks.
Processor wake-up event or CONNECT asserted by
4
Northbridge.
5 CLKFWDRST is deasserted by the Northbridge.
Forward clocks start three SYSCLK periods after
6
CLKFWDRST is deasserted.
Figure 7. Processor Connect State Diagram
Disconnect
4/C
Action
A CLKFWDRST is asserted by the Northbridge.
B Issue a Connect special cycle.*
Return internal clocks to full speed and assert
C
PROCRDY.
Note:
*
The Connect special cycle is only issued after a
processor wake-up event (interrupt or STPCLK#
deassertion) occurs. If the AMD Athlon™ system
bus is connected so the Northbridge can probe the
processor, a Connect special cycle is not issued at
that time (it is only issued after a subsequent
processor wake-up event).
Chapter 4 Power Management 17
Preliminary Information
AMD Athlon™ XP Processor Model 8 Data Sheet 25175H—March 2003
4.3 Clock Control
The processor implements a Clock Control (CLK_Ctl) MSR
(address C001_001Bh) that determines the internal clock
divisor when the AMD Athlon system bus is disconnected.
Refer to the AMD Athlon™ and AMD Duron™ Processors BIOS,
Software, and Debug Developers Guide, order# 21656, for more
details on the CLK_Ctl register.
18 Power Management Chapter 4
Preliminary Information
25175H—March 2003 AMD Athlon™ XP Processor Model 8 Data Sheet
5 CPUID Support
AMD Athlon™ XP processor model 8 version and feature set
recognition can be performed through the use of the CPUID
instruction, that provides complete information about the
processor—vendor, type, name, etc., and its capabilities.
Software can make use of this information to accurately tune
the system for maximum performance and benefit to users.
For information on the use of the CPUID instruction see the
following documents:
■ AMD Processor Recognition Application Note, order# 20734
■ AMD Athlon™ Processor Recognition Application Note
Addendum, order# 21922
■ AMD Athlon™ and AMD Duron™ Processors BIOS, Software,
and Debug Developers Guide, order# 21656
Chapter 5 CPUID Support 19
Preliminary Information
AMD Athlon™ XP Processor Model 8 Data Sheet 25175H—March 2003
20 CPUID Support Chapter 5
Preliminary Information
25175H—March 2003 AMD Athlon™ XP Processor Model 8 Data Sheet
6 Advanced 266 Front-Side Bus AMD Athlon™ XP
Processor Model 8 Specifications
This chapter describes the electrical specifications that are
unique to the advanced 266 front-side bus (FSB) AMD Athlon™
XP processor model 8.
6.1 Part-Specific Electrical and Thermal Specifications for
Advanced 266 FSB AMD Athlon™ XP Processors Model 8
This section provides part-specific electrical and thermal
information for each type of the Advanced 266 FSB
AMD Athlon XP processors model 8 in Table 1 on page 22 and
Table 2 on page 23.
Chapter 6 Advanced 266 Front-Side Bus AMD Athlon™ XP Processor Model 8 Specifications 21
Preliminary Information
AMD Athlon™ XP Processor Model 8 Data Sheet 25175H—March 2003
Table 1 shows the part-specific electrical and thermal
specifications in the C0 working state and the S1 Stop Grant
state for processors with a CPUID = 680.
Table 1. Electrical and Thermal Specifications for Processors with a CPUID of 680
I
(Processor Current)
CC
Stop Grant S1
1, 2, 3, 4
Thermal Power
5
Maximum Die
Temperature
Frequency in MHz
(Model Number)
V
CC_CORE
(Core
Voltage)
Working State C0
Maximum Typical Maximum Typical Maximum Typical
1467 (1700+)
1533 (1800+)
1600 (1900+)
1.50 V
32.9 A 29.9 A
34.0 A 30.9 A 51.0 W 46.3 W
5.87 A 3.7 A
35.0 A 31.8 A 52.5 W 47.7 W
49.4 W 44.9 W
1.60 V 37.7 A 34.2 A 7.68 A 4.7 A
1667 (2000+)
1733 (2100+)
1800 (2200+)
Notes:
1. See Figure 3, "AMD Athlon™ XP Processor Model 8 Power Management States" on page 9.
2. The maximum Stop Grant currents are absolute worst case currents for parts that may yield from the worst case corner of the
process and are not representative of the typical Stop Grant current that is currently about one-third of the maximum specified
current.
3. These currents occur when the AMD Athlon™ system bus is disconnected and has a low power ratio of 1/8 for Stop Grant
disconnect and a low power ratio of 1/8 Halt disconnect applied to the core clock grid of the processor as dictated by a value of
6003_1223h programmed into the Clock Control (CLK_Ctl) MSR. For more information, refer to the AMD Athlon™ and
AMD Duron™ Processors BIOS, Software, and Debug Developers Guide, order# 21656.
4. The Stop Grant current consumption is characterized at 50°C and not tested.
1.65 V 36.5 A 33.2 A 8.85 A 5.4 A
1.60 V 38.8 A 35.2 A 7.68 A 4.7 A 62.1 W 56.4 W
1.65 V 41.2 A 37.4 A 8.85 A 5.4 A 67.9 W 61.7 W 85°C
60.3 W 54.7 W
90°C
5. Thermal design power represents the maximum sustained power dissipated while executing publicly-available software or
instruction sequences under normal system operation at nominal V
the processor to prevent the processor from exceeding its maximum die temperature.
. Thermal solutions must monitor the temperature of
CC_CORE
22 Advanced 266 Front-Side Bus AMD Athlon™ XP Processor Model 8 Specifications Chapter 6
Preliminary Information
25175H—March 2003 AMD Athlon™ XP Processor Model 8 Data Sheet
Table 2 shows the part-specific electrical and thermal
specifications in the C0 working state and the S1 Stop Grant
state for processors with a CPUID = 681
Table 2. Electrical and Thermal Specifications for Processors with a CPUID of 681
I
(Processor Current)
CC
Stop Grant S1
1, 2, 3, 4
Thermal Power
5
Maximum Die
Temperature
Frequency in MHz
(Model Number)
V
CC_CORE
(Core
Voltage)
Working State C0
Maximum Typical Maximum Typical Maximum Typical
1400 (1600+)
1.60 V 30.3 A 27.5 A 8.1 A 4.9 A 48.5 W 44.0 W
1.50 V 32.9 A 29.9 A 5.4 A 3.9 A 49.4 W 44.9 W
1467 (1700+)
1.60 V 30.9 A 28.0 A 8.1 A 4.9 A 49.4 W 44.9 W
1.50 V 34.0 A 30.9 A 5.4 A 3.9 A 51.0 W 46.3 W
1533 (1800+)
1667 (2000+)
1733 (2100+)
1800 (2200+)
2000 (2400+)
2133 (2600+)
Notes:
1. See Figure 3, "AMD Athlon™ XP Processor Model 8 Power Management States" on page 9.
2. The maximum Stop Grant currents are absolute worst case currents for parts that may yield from the worst case corner of the
process and are not representative of the typical Stop Grant current that is currently about one-third of the maximum specified
current.
3. These currents occur when the AMD Athlon™ system bus is disconnected and has a low power ratio of 1/8 for Stop Grant
disconnect and a low power ratio of 1/8 Halt disconnect applied to the core clock grid of the processor as dictated by a value of
2003_1223h programmed into the Clock Control (CLK_Ctl) MSR. For more information, refer to the AMD Athlon™ and
AMD Duron™ Processors BIOS, Software, and Debug Developers Guide, order# 21656.
1.60 V 31.9 A 28.9 A 8.1 A 4.9 A 51.0 W 46.3 W
1.60 V 37.7 A 34.2 A 8.1 A 4.9 A 60.3 W 54.7 W
1.60 V 38.8 A 34.9 A 8.1 A 4.9 A 62.1 W 55.9 W
1.60 V 39.3 A 35.6 A 8.1 A 4.9 A 62.8 W 57.0 W
1.65 V 41.4 A 37.6 A 8.9 A 5.4 A 68.3 W 62.0 W
1.65 V 41.4 A 37.6 A 8.9 A 5.4 A 68.3 W 62.0 W
90°C
85°C
4. The Stop Grant current consumption is characterized at 50°C and not tested.
5. Thermal design power represents the maximum sustained power dissipated while executing publicly-available software or
instruction sequences under normal system operation at nominal V
the processor to prevent the processor from exceeding its maximum die temperature.
. Thermal solutions must monitor the temperature of
CC_CORE
Chapter 6 Advanced 266 Front-Side Bus AMD Athlon™ XP Processor Model 8 Specifications 23
Preliminary Information
AMD Athlon™ XP Processor Model 8 Data Sheet 25175H—March 2003
6.2 Advanced 266 FSB AMD Athlon™ XP Processor Model 8 SYSCLK and SYSCLK# AC Characteristics
Table 3 shows the SYSCLK/SYSCLK# differential clock AC
.
Table 3. SYSCLK and SYSCLK# AC Characteristics
Symbol Parameter Description Minimum Maximum Units Notes
Clock Frequency 50 133 MHz 1
Duty Cycle 30% 70%
characteristics of this processor.
t
1
t
2
t
3
t
4
t
5
Period 7.5 ns 2, 3
High Time 1.05 ns
Low Time 1.05 ns
Fall Time 2 ns
Rise Time 2 ns
Period Stability ± 300 ps
Notes:
1. The AMD Athlon™ system bus operates at twice this clock frequency.
2. Circuitry driving the AMD Athlon system bus clock inputs must exhibit a suitably low closed-loop jitter bandwidth to allow the PLL
to track the jitter. The –20dB attenuation point, as measured into a 20
3. Circuitry driving the AMD Athlon system bus clock inputs may purposely alter the AMD Athlon system bus clock frequency (spread
spectrum clock generators). In no cases can the AMD Athlon system bus period violate the minimum specification above.
AMD Athlon system bus clock inputs can vary from 100% of the specified frequency to 99% of the specified frequency at a
maximum rate of 100 kHz.
- or 30-pF load must be less than 500 kHz.
Figure 8 shows a sample waveform of the SYSCLK signal.
t
2
V
CROSS
t
5
V
Threshold-AC
t
3
t
4
t
1
Figure 8. SYSCLK Waveform
24 Advanced 266 Front-Side Bus AMD Athlon™ XP Processor Model 8 Specifications Chapter 6
Preliminary Information
25175H—March 2003 AMD Athlon™ XP Processor Model 8 Data Sheet
6.3 Advanced 266 FSB AMD Athlon™ System Bus AC Characteristics
The AC characteristics for the AMD Athlon system bus of this
processor are shown in Table 4. The parameters are grouped
based on the source or destination of the signals involved.
Table 4. AMD Athlon™ System Bus AC Characteristics
Group Symbol Parameter Min Max Units Notes
T
All Signals
Forward
Clocks
Sync
Notes:
1. Rise and fall time ranges are guidelines over which the I/O has been characterized.
2. T
SKEW-SAMEEDGE
forward clock, as measured at the package, with respect to the same clock edge.
T
SKEW-DIFFEDGE
forward clock, as measured at the package, with respect to different clock edges.
RISE
T
FALL
T
SKEW-SAMEEDGE
T
SKEW-DIFFEDGE
T
SU
T
HD
C
IN
C
OUT
T
VAL
T
SU
T
HD
is the maximum skew within a clock forwarded group between any two signals or between any signal and its
is the maximum skew within a clock forwarded group between any two signals or between any signal and its
Output Rise Slew Rate 1 3 V/ns 1
Output Fall Slew Rate 1 3 V/ns 1
Output skew with respect to
the same clock edge
Output skew with respect to a
different clock edge
Input Data Setup Time 300 ps 3
Input Data Hold Time 300 ps 3
Capacitance on input Clocks 4 25 pF
Capacitance on output Clocks 4 12 pF
RSTCLK to Output Valid 250 2000 ps 4, 5
Setup to RSTCLK 500 ps 4, 6
Hold from RSTCLK 1000 ps 4, 6
–385ps2
–770ps2
3. Input SU and HD times are with respect to the appropriate Clock Forward Group input clock.
4. The synchronous signals include
5. T
is RSTCLK rising edge to output valid for PROCRDY. Test Load is 25 pF.
VAL
6. T
is setup of CONNECT/CLKFWDRST to rising edge of RSTCLK. THD is hold of CONNECT/CLKFWDRST from rising edge of
SU
RSTCLK.
PROCRDY, CONNECT, and CLKFWDRST.
Chapter 6 Advanced 266 Front-Side Bus AMD Athlon™ XP Processor Model 8 Specifications 25
Preliminary Information
AMD Athlon™ XP Processor Model 8 Data Sheet 25175H—March 2003
26 Advanced 266 Front-Side Bus AMD Athlon™ XP Processor Model 8 Specifications Chapter 6
Preliminary Information
25175H—March 2003 AMD Athlon™ XP Processor Model 8 Data Sheet
7 Advanced 333 Front-Side Bus AMD Athlon™ XP
Processor Model 8 Specifications
This chapter describes the electrical specifications that are
unique to the advanced 333 front-side bus (FSB) AMD Athlon™
XP processor model 8.
7.1 Electrical and Thermal Specifications for the Advanced 333 FSB AMD Athlon™ XP Processor Model 8
Table 5 shows the electrical and thermal specifications for this
processor in the C0 working state and the S1 Stop Grant state.
Table 5. Electrical and Thermal Specifications
I
(Processor Current)
V
Frequency in MHz
(Model Number)
2083 (2600+)
2167 (2700+)
Notes:
1. See Figure 3, "AMD Athlon™ XP Processor Model 8 Power Management States" on page 9.
2. The maximum Stop Grant currents are absolute worst case currents for parts that may yield from the worst case corner of the
process and are not representative of the typical Stop Grant current that is currently about one-third of the maximum specified
current.
3. These currents occur when the AMD Athlon™ system bus is disconnected and has a low power ratio of 1/8 for Stop Grant
disconnect and a low power ratio of 1/8 Halt disconnect applied to the core clock grid of the processor as dictated by a value of
2003_1223h programmed into the Clock Control (CLK_Ctl) MSR. For more information, refer to the AMD Athlon™ and
AMD Duron™ Processors BIOS, Software, and Debug Developers Guide, order# 21656.
4. The Stop Grant current consumption is characterized at 50°C and not tested.
5. Thermal design power represents the maximum sustained power dissipated while executing publicly-available software or
instruction sequences under normal system operation at nominal V
the processor to prevent the processor from exceeding its maximum die temperature.
CC_CORE
(Core
Voltage)
1.65 V 41.4 A 37.6 A 8.9 A 5.9 A 68.3 W 62.0 W 85°C
Working State C0
Maximum Typical Maximum Typical Maximum Typical
CC
Stop Grant S1
CC_CORE
1, 2, 3, 4
Thermal Power
. Thermal solutions must monitor the temperature of
5
Maximum Die
Temperature
Chapter 7 Advanced 333 Front-Side Bus AMD Athlon™ XP Processor Model 8 Specifications 27
Preliminary Information
AMD Athlon™ XP Processor Model 8 Data Sheet 25175H—March 2003
7.2 Advanced 333 FSB AMD Athlon™ XP Processor Model 8 SYSCLK and SYSCLK# AC Characteristics
Table 6 shows the SYSCLK/SYSCLK# differential clock AC
characteristics of this processor.
Table 6. SYSCLK and SYSCLK# AC Characteristics
Symbol Parameter Description Minimum Maximum Units Notes
Clock Frequency 50 166 MHz 1
Duty Cycle 30% 70%
t
1
t
2
t
3
t
4
t
5
Period 6 ns 2, 3
High Time 1.0 ns
Low Time 1.0 ns
Fall Time 2 ns
Rise Time 2 ns
Period Stability ± 300 ps
Notes:
1. The AMD Athlon™ system bus operates at twice this clock frequency.
2. Circuitry driving the AMD Athlon system bus clock inputs must exhibit a suitably low closed-loop jitter bandwidth to allow the PLL
to track the jitter. The –20dB attenuation point, as measured into a 20
3. Circuitry driving the AMD Athlon system bus clock inputs may purposely alter the AMD Athlon system bus clock frequency (spread
spectrum clock generators). In no cases can the AMD Athlon system bus period violate the minimum specification above.
AMD Athlon system bus clock inputs can vary from 100% of the specified frequency to 99% of the specified frequency at a
maximum rate of 100 kHz.
- or 30-pF load must be less than 500 kHz.
Figure 9 shows a sample waveform of the SYSCLK signal.
t
2
V
CROSS
t
5
V
Threshold-AC
t
3
t
4
t
1
Figure 9. SYSCLK Waveform
28 Advanced 333 Front-Side Bus AMD Athlon™ XP Processor Model 8 Specifications Chapter 7
Preliminary Information
25175H—March 2003 AMD Athlon™ XP Processor Model 8 Data Sheet
7.3 Advanced 333 FSB AMD Athlon™ System Bus AC Characteristics
The AC characteristics of the AMD Athlon system bus of this
processor are shown in Table 7. The parameters are grouped
based on the source or destination of the signals involved.
Table 7. AMD Athlon™ System Bus AC Characteristics
Group Symbol Parameter Min Max Units Notes
T
All Signals
Forward
Clocks
Sync
Notes:
1. Rise and fall time ranges are guidelines over which the I/O has been characterized.
2. T
SKEW-DIFFEDGE
forward clock, as measured at the package, with respect to different clock edges.
3. Input SU and HD times are with respect to the appropriate Clock Forward Group input clock.
4. The synchronous signals include
RISE
T
FALL
T
SKEW-DIFFEDGE
T
SU
T
HD
C
IN
C
OUT
T
VAL
T
SU
T
HD
is the maximum skew within a clock forwarded group between any two signals or between any signal and its
Output Rise Slew Rate 1 3 V/ns 1
Output Fall Slew Rate 1 3 V/ns 1
Output skew with respect to a
different clock edge
–770ps2
Input Data Setup Time 300 ps 3
Input Data Hold Time 300 ps 3
Capacitance on input Clocks 4 25 pF
Capacitance on output Clocks 4 12 pF
RSTCLK to Output Valid 800 2000 ps 4, 5
Setup to RSTCLK 500 ps 4, 6
Hold from RSTCLK 500 ps 4, 6
PROCRDY, CONNECT, and CLKFWDRST.
5. T
is RSTCLK rising edge to output valid for PROCRDY. Test Load is 25 pF.
VAL
6. T
is setup of CONNECT/CLKFWDRST to rising edge of RSTCLK. THD is hold of CONNECT/CLKFWDRST from rising edge of
SU
RSTCLK.
Chapter 7 Advanced 333 Front-Side Bus AMD Athlon™ XP Processor Model 8 Specifications 29
Preliminary Information
AMD Athlon™ XP Processor Model 8 Data Sheet 25175H—March 2003
30 Advanced 333 Front-Side Bus AMD Athlon™ XP Processor Model 8 Specifications Chapter 7
Preliminary Information
25175H—March 2003 AMD Athlon™ XP Processor Model 8 Data Sheet
8 Electrical Data
This chapter describes the electrical characteristics that apply
to all desktop AMD Athlon™ XP processors model 8.
8.1 Conventions
The conventions used in this chapter are as follows:
■ Current specified as being sourced by the processor is
negative.
■ Current specified as being sunk by the processor is positive.
8.2 Interface Signal Groupings
The electrical data in this chapter is presented separately for
each signal group.
Table 8 defines each group and the signals contained in each
group.
Table 8. Interface Signal Groupings
Signal Group Signals Notes
See “Advanced 266 FSB
AMD Athlon™ System Bus AC
SADDIN[14:2]#, SADDOUT[14:2]#, SADDINCLK#, SADDOUTCLK#,
AMD Athlon™
System Bus
APIC PICD[1:0]#, PICCLK
Frequency FID[3:0], FSB_Sense[1:0]
JTAG TMS, TCK, TRST#, TDI, TDO
SFILLVAL#, SDATAINVAL#, SDATAOUTVAL#, SDATA[63:0]#,
SDATAINCLK[3:0]#, SDATAOUTCLK[3:0]#, CLKFWDRST, PROCRDY,
CONNECT
Characteristics” on page 25,
“Advanced 333 FSB AMD Athlon™
System Bus AC Characteristics” on
page 29, “AMD Athlon™ System
Bus DC Characteristics” on page 36,
and “CLKFWDRST Pin” on page 73.
See “APIC Pins AC and DC
Characteristics” on page 44, and
“APIC Pins, PICCLK, PICD[1:0]#” on
page 73.
See “Frequency Identification
(FID[3:0])” on page 33, “FID[3:0]
Pins” on page 75, and
“FSB_Sense[1:0] Pins” on page 76.
See “General AC and DC
Characteristics” on page 39.
Chapter 8 Electrical Data 31
Preliminary Information
AMD Athlon™ XP Processor Model 8 Data Sheet 25175H—March 2003
Table 8. Interface Signal Groupings (continued)
Signal Group Signals Notes
See “Voltage Identification
(VID[4:0])” on page 33, “VID[4:0]
Pins” on page 78,“VCCA AC and DC
Power
Southbridge
VID[4:0], VCCA, V
CC_CORE
, COREFB, COREFB#
RESET#, INTR, NMI, SMI#, INIT#, A20M#, FERR, IGNNE#,
STPCLK#, FLUSH#
Characteristics” on page 33,
“V
CC_CORE
Characteristics” on page
34,“VCCA Pin” on page 78, and
“COREFB and COREFB# Pins” on
page 74.
See “General AC and DC
Characteristics” on page 39, “INTR
Pin” on page 76, “NMI Pin” on page
77, “SMI# Pin” on page 78, “INIT#
Pin” on page 76, “A20M# Pin” on
page 73, “FERR Pin” on page
74,“IGNNE# Pin” on page 76,
“STPCLK# Pin” on page 79, and
“FLUSH# Pin” on page 77.
System Clocks
Test
SYSCLK, SYSCLK# (Tied to CLKIN/CLKIN# and RSTCLK/RSTCLK#),
PLLBYPASSCLK#, PLLBYPASSCLK
PLLBYPASS#, PLLTEST#, PLLMON1, PLLMON2, SCANCLK1,
SCANCLK2, SCANSHIFTEN, SCANINTEVAL, ANALOG
Thermal THERMDA, THERMDC
Miscellaneous DBREQ#, DBRDY, PWROK
See “Advanced 266 FSB
AMD Athlon™ XP Processor Model
8 SYSCLK and SYSCLK# AC
Characteristics” on page 24,
“Advanced 333 FSB AMD Athlon™
XP Processor Model 8 SYSCLK and
SYSCLK# AC Characteristics” on
page 28, Table 14, “SYSCLK and
SYSCLK# DC Characteristics,” on
page 37, “SYSCLK and SYSCLK#”
on page 78, and “PLL Bypass and
Test Pins” on page 77.
See “General AC and DC
Characteristics” on page 39, “PLL
Bypass and Test Pins” on page 77,
“Scan Pins” on page 78, “Analog
Pin” on page 73.
Table 17, “Thermal Diode Electrical
Characteristics,” on page 42, and
“THERMDA and THERMDC Pins”
on page 78.
See “General AC and DC
Characteristics” on page 39,
“DBRDY and DBREQ# Pins” on
page 74, “PWROK Pin” on page 77.
32 Electrical Data Chapter 8
Preliminary Information
25175H—March 2003 AMD Athlon™ XP Processor Model 8 Data Sheet
8.3 Voltage Identification (VID[4:0])
Table 9 shows the VID[4:0] DC Characteristics. For more information on VID[4:0] DC Characteristics, see “VID[4:0] Pins” on
page 78.
Table 9. VID[4:0] DC Characteristics
Parameter Description Min Max
I
OL
V
OH
Note:
* The VID pins are either open circuit or pulled to ground. It is recommended that these pins
Output Current Low 6 mA
Output High Voltage – 5.25 V *
are not pulled above 5.25 V, which is 5.0 V + 5%.
8.4 Frequency Identification (FID[3:0])
Table 10 shows the FID[3:0] DC characteristics. For more
information, see “FID[3:0] Pins” on page 75.
Table 10. FID[3:0] DC Characteristics
Parameter Description Min Max
I
OL
V
OH
Note:
* The FID pins must not be pulled above this voltage by an external pullup resistor.
Output Current Low 6 mA
Output High Voltage – 2.625 V *
8.5 VCCA AC and DC Characteristics
Table 11 shows the AC and DC characteristics for VCCA. For
more information, see “VCCA Pin” on page 78.
Table 11. VCCA AC and DC Characteristics
Symbol Parameter Min Nominal Max Units Notes
V
VCCA
I
VCCA
Notes:
1. Minimum and Maximum voltages are absolute. No transients below minimum nor above maximum voltages are permitted.
2. Measured at 2.5 V.
VCCA Pin Voltage 2.25 2.5 2.75 V 1
VCCA Pin Current 0 50 mA/GHz 2
Chapter 8 Electrical Data 33
Preliminary Information
AMD Athlon™ XP Processor Model 8 Data Sheet 25175H—March 2003
8.6 Decoupling
See the AMD Athlon™ Processor-Based Motherboard Design
Guide, order# 24363, or contact your local AMD office for
information about the decoupling required on the motherboard
for use with the AMD Athlon™ XP processor model 8.
8.7 V
CC_CORE
Characteristics
Table 12 shows the AC and DC characteristics for V
See Figure 10 on page 35 for a graphical representation of the
V
CC_CORE
Table 12. V
CC_CORE
AC and DC Characteristics
Symbol Parameter Limit in Working State Units
V
CC_CORE_DC_MAX
V
CC_CORE_DC_MIN
V
CC_CORE_AC_MAX
V
CC_CORE_AC_MIN
t
MAX_AC
t
MIN_AC
Note:
*
All voltage measurements are taken differentially at the COREFB/COREFB# pins.
Maximum static voltage above V
Maximum static voltage below V
Maximum excursion above V
Maximum excursion below V
Maximum excursion time for AC transients 10 µs
Negative excursion time for AC transients 5 µs
waveform.
CC_CORE_NOM
CC_CORE_NOM
CC_CORE_NOM
CC_CORE_NOM
*
*
*
*
50 mV
–50 mV
150 mV
–100 mV
CC_CORE
.
34 Electrical Data Chapter 8
Preliminary Information
25175H—March 2003 AMD Athlon™ XP Processor Model 8 Data Sheet
V
CC_CORE_AC_MAX
V
CC_CORE_DC_MAX
V
CC_CORE_NOM
V
CC_CORE_DC_MIN
Figure 10 shows the processor core voltage (V
waveform response to perturbation. The t
transient excursion time) and t
max_AC
min_AC
(positive AC transient
CC_CORE
(negative AC
excursion time) represent the maximum allowable time below
or above the DC tolerance thresholds.
t
MAX_AC
)
V
CC_CORE_AC_MIN
Figure 10. V
I
CORE_MAX
I
CORE_MIN
CC_CORE
t
Voltage Waveform
MIN_AC
dI /dt
Chapter 8 Electrical Data 35
Preliminary Information
AMD Athlon™ XP Processor Model 8 Data Sheet 25175H—March 2003
8.8 Absolute Ratings
The AMD Athlon XP processor model 8 should not be subjected
to conditions exceeding the absolute ratings, as such conditions
can adversely affect long-term reliability or result in functional
damage.
Table 13 lists the maximum absolute ratings of operation for the
AMD Athlon XP processor model 8.
Table 13. Absolute Ratings
Parameter Description Min Max
V
CC_CORE
VCCA AMD Athlon XP processor model 8 PLL supply –0.5 V VCCA Max + 0.5 V
V
PIN
T
STORAGE
AMD Athlon™ XP processor model 8 core supply –0.5 V
Voltage on any signal pin –0.5 V
Storage temperature of processor –40ºC 100ºC
V
CC_CORE
V
CC_CORE
Max + 0.5 V
Max + 0.5 V
36 Electrical Data Chapter 8
Preliminary Information
25175H—March 2003 AMD Athlon™ XP Processor Model 8 Data Sheet
8.9 SYSCLK and SYSCLK# DC Characteristics
Table 14 shows the DC characteristics of the SYSCLK and
SYSCLK# differential clocks. The SYSCLK signal represents
CLKIN and RSTCLK tied together while the SYSCLK# signal
represents CLKIN# and RSTCLK# tied together. For
information about SYSCLK and SYSCLK#, see “SYSCLK and
SYSCLK#” on page 79 and Table 24, “Pin Name
Abbreviations,” on page 58.
Table 14. SYSCLK and SYSCLK# DC Characteristics
Symbol Description Min Max Units
V
Threshold-DC
V
Threshold-AC
I
LEAK_P
I
LEAK_N
V
CROSS
C
PIN
Note:
* The following processor inputs have twice the listed capacitance because they connect to two input pads—SYSCLK and SYSCLK#.
Crossing before transition is detected (DC) 400 mV
Crossing before transition is detected (AC) 450 mV
Leakage current through P-channel pullup to V
CC_CORE
–1 mA
Leakage current through N-channel pulldown to VSS (Ground) 1 mA
Differential signal crossover
V
CC_CORE
Capacitance * 4 25 * pF
SYSCLK connects to CLKIN/RSTCLK. SYSCLK# connects to CLKIN#/RSTCLK#.
/ 2±100
Figure 11 shows the DC characteristics of the SYSCLK and
SYSCLK# signals.
mV
V
CROSS
V
Threshold-DC
= 400mV V
Threshold-AC
= 450mV
Figure 11. SYSCLK and SYSCLK# Differential Clock Signals
Chapter 8 Electrical Data 37
Preliminary Information
AMD Athlon™ XP Processor Model 8 Data Sheet 25175H—March 2003
8.10 AMD Athlon™ System Bus DC Characteristics
Table 15 shows the DC characteristics of the AMD Athlon
system bus used by the AMD Athlon XP processor model 8.
Table 15. AMD Athlon™ System Bus DC Characteristics
Symbol Parameter Condition Min Max Units Notes
V
REF
I
VREF_LEAK_PVREF
I
VREF_LEAK_NVREF
V
IH
V
IL
I
LEAK_P
I
LEAK_N
C
IN
R
ON
R
setP
R
setN
Notes:
1. V
DC Input Reference Voltage
Tristate Leakage Pullup VIN = V
Tristate Leakage Pulldown VIN = V
REF
REF
Nominal
Nominal
Input High Voltage
Input Low Voltage –500
V
= VSS
Tristate Leakage Pullup
Tristate Leakage Pulldown
IN
(Ground)
V
= V
IN
Nominal
CC_CORE
Input Pin Capacitance 4 7 pF
Output Resistance
Impedance Set Point, P Channel 40 70 Ω 2
Impedance Set Point, N Channel 40 70 Ω 2
is nominally set to 50% of V
REF
created with a sufficiently accurate DC source and a sufficiently quiet AC response to adhere to the ± 50 mV specification listed
above.
with actual values that are specific to motherboard design implementation. V
CC_CORE
(0.5 x V
CC_CORE
–50
–100 µA
V
+ 200 V
REF
–1 mA
0.90 x R
setN,P
)
(0.5 x V
CC_CORE
+50
100 µA
CC_CORE
V
– 200
REF
1mA
1.1 x R
+ 500
setN,P
)
mV 1
mV
mV
Ω 2
must be
REF
2. Measured at V
CC_CORE
/ 2.
38 Electrical Data Chapter 8
Preliminary Information
25175H—March 2003 AMD Athlon™ XP Processor Model 8 Data Sheet
8.11 General AC and DC Characteristics
Table 16 shows the AMD Athlon XP processor model 8 AC and
DC characteristics of the Southbridge, JTAG, test, and miscellaneous pins.
Table 16. General AC and DC Characteristics
Symbol Parameter Description Condition Min Max Units Notes
(V
V
IH
Input High Voltage
CC_CORE
200 mV
/ 2) +
V
CC_CORE
300 mV
+
V1,2
V
IL
V
OH
V
OL
I
LEAK_P
I
LEAK_N
I
OH
I
OL
T
SU
T
HD
T
DELAY
Notes:
1. Characterized across DC supply voltage range.
2. Values specified at nominal V
3. I
4. Synchronous inputs/outputs are specified with respect to RSTCLK and RSTCK# at the pins.
5. These are aggregate numbers.
6. Edge rates indicate the range over which inputs were characterized.
7. In asynchronous operation, the signal must persist for this time to enable capture.
8. This value assumes RSTCLK period is 10 ns ==> TBIT = 2*fRST.
9. The approximate value for standard case in normal mode operation.
10. This value is dependent on RSTCLK frequency, divisors, Low Power mode, and core frequency.
11. Reassertions of the signal within this time are not guaranteed to be seen by the core.
12. This value assumes that the skew between RSTCLK and K7CLKOUT is much less than one phase.
13. This value assumes RSTCLK and K7CLKOUT are running at the same frequency, though the processor is capable of other
14. Time to valid is for any open-drain pins. See requirements 7 and 8 in the “Power-Up Timing Requirements“ chapter for more
Input Low Voltage –300 350 mV 1, 2
Output High Voltage
V
CC_CORE
400
–
V
CC_CORE
300
+
mV
Output Low Voltage –300 400 mV
V
= VSS
Tristate Leakage Pullup
Tristate Leakage Pulldown
IN
(Ground)
V
= V
IN
Nominal
CC_CORE
–1 mA
600 µA
Output High Current –6 mA 3
Output Low Current 6 mA 3
Sync Input Setup Time 2.0 ns 4, 5
Sync Input Hold Time 0.0 ps 4, 5
Output Delay with respect to RSTCLK 0.0 6.1 ns 5
CC_CORE
and IOH are measured at VOL maximum and VOH minimum, respectively.
OL
configurations.
information.
. Scale parameters between V
CC_CORE.
minimum and V
CC_CORE.
maximum.
Chapter 8 Electrical Data 39
Preliminary Information
AMD Athlon™ XP Processor Model 8 Data Sheet 25175H—March 2003
Table 16. General AC and DC Characteristics (continued)
Symbol Parameter Description Condition Min Max Units Notes
T
BIT
T
RPT
T
RISE
T
FALL
C
PIN
T
VALID
Notes:
1. Characterized across DC supply voltage range.
2. Values specified at nominal V
3. I
4. Synchronous inputs/outputs are specified with respect to RSTCLK and RSTCK# at the pins.
5. These are aggregate numbers.
6. Edge rates indicate the range over which inputs were characterized.
7. In asynchronous operation, the signal must persist for this time to enable capture.
8. This value assumes RSTCLK period is 10 ns ==> TBIT = 2*fRST.
9. The approximate value for standard case in normal mode operation.
10. This value is dependent on RSTCLK frequency, divisors, Low Power mode, and core frequency.
11. Reassertions of the signal within this time are not guaranteed to be seen by the core.
12. This value assumes that the skew between RSTCLK and K7CLKOUT is much less than one phase.
13. This value assumes RSTCLK and K7CLKOUT are running at the same frequency, though the processor is capable of other
14. Time to valid is for any open-drain pins. See requirements 7 and 8 in the “Power-Up Timing Requirements“ chapter for more
Input Time to Acquire 20.0 ns 7, 8
Input Time to Reacquire 40.0 ns 9–13
Signal Rise Time 1.0 3.0 V/ns 6
Signal Fall Time 1.0 3.0 V/ns 6
Pin Capacitance 4 12 pF
Time to data valid 100 ns 14
CC_CORE
and IOH are measured at VOL maximum and VOH minimum, respectively.
OL
configurations.
information.
. Scale parameters between V
CC_CORE.
minimum and V
CC_CORE.
maximum.
40 Electrical Data Chapter 8
Preliminary Information
25175H—March 2003 AMD Athlon™ XP Processor Model 8 Data Sheet
8.12 Open-Drain Test Circuit
Figure 12 is a test circuit that may be used on automated test
equipment (ATE) to test for validity on open drain pins.
Refer to Table 16, “General AC and DC Characteristics,” on
page 39 for timing requirements.
V
Termination
Open-Drain Pin
IOL = Output Current
Notes:
1. V
Termination
V
Termination
= 1.2 V for VID and FID pins
= 1.0 V for APIC pins
2. IOL = –6 mA for VID and FID pins
IOL = –9 mA for APIC pins
Figure 12. General ATE Open-Drain Test Circuit
1
50 Ω ±3%
2
Chapter 8 Electrical Data 41
Preliminary Information
AMD Athlon™ XP Processor Model 8 Data Sheet 25175H—March 2003
8.13 Thermal Diode Characteristics
The AMD Athlon XP processor model 8 provides a diode that
can be used in conjunction with an external temperature sensor
to determine the die temperature of the processor. The diode
anode (THERMDA) and cathode (THERMDC) are available as
pins on the processor, as described in “THERMDA and
THERMDC Pins” on page 78.
For information about thermal design for the AMD Athlon XP
processor model 8, including layout and airflow considerations,
see the AMD Processor Thermal, Mechanical, and Chassis Cooling
Design Guide, order# 23794, and the cooling guidelines on
http://www.amd.com.
Thermal Diode Electrical Characteristics
Table 17 shows the AMD Athlon XP processor model 8
characteristics of the on-die thermal diode. For information
about calculations for the ideal diode equation and
temperature offset correction, see Appendix A, "Thermal
Diode Calculations," on page 77.
Table 17. Thermal Diode Electrical Characteristics
Symbol
I
n
f, lumped
n
f, actual
R
T
Notes:
1. The sourcing current should always be used in forward bias only.
2. Characterized at 95°C with a forward bias current pair of 10 µA and 100 µA. AMD
recommends using a minimum of two sourcing currents to accurately measure the
temperature of the thermal diode.
3. Not 100% tested. Specified by design and limited characterization.
4. The lumped ideality factor adds the effect of the series resistance term to the actual ideality
factor. The series resistance term indicates the resistance from the pins of the processor to the
on-die thermal diode. The value of the lumped ideality factor depends on the sourcing current
pair used.
Parameter
Description
Sourcing current 5 300 µA 1
Lumped ideality
factor
Actual ideality factor 1.00261 3, 4
Series Resistance 0.93 Ω 3, 4
Min Nom Max Units Notes
1.00000 1.00374 1.00900 2, 3, 4
42 Electrical Data Chapter 8
Preliminary Information
25175H—March 2003 AMD Athlon™ XP Processor Model 8 Data Sheet
Thermal Protection Characterization
The following section describes parameters relating to thermal
protection. The implementation of thermal control circuitry to
control processor temperature is left to the manufacturer to
determine how to implement.
Thermal limits in motherboard design are necessary to protect
the processor from thermal damage. T
SHUTDOWN
is the
temperature for thermal protection circuitry to initiate
shutdown of the processor. T
SD_DELAY
is the maximum time
allowed from the detection of the over-temperature condition to
processor shutdown to prevent thermal damage to the
processor.
Systems that do not implement thermal protection circuitry or
that do not react within the time specified by T
SD_DELAY
can
cause thermal damage to the processor during the unlikely
events of fan failure or powering up the processor without a
heat-sink. The processor relies on thermal circuitry on the
motherboard to turn off the regulated core voltage to the
processor in response to a thermal shutdown event.
Thermal protection circuitry reference designs and thermal
solution guidelines are found in the following documents:
■ AMD Athlon™ Processor-Based Motherboard Design Guide,
order# 24363
■ AMD Thermal, Mechanical, and Chassis Cooling Design Guide,
order# 23794
See http://www.amd.com for more information about thermal
solutions.
Table 18 on page 44 shows the T
SHUTDOWN
and T
SD_DELAY
specifications for circuitry in motherboard design necessary for
thermal protection of the processor.
Chapter 8 Electrical Data 43
Preliminary Information
AMD Athlon™ XP Processor Model 8 Data Sheet 25175H—March 2003
Table 18. Guidelines for Platform Thermal Protection of the Processor
Symbol Parameter Description Max Units Notes
TSHUTDOWN
T
SD_DELAY
Notes:
1. The thermal diode is not 100% tested, it is specified by design and limited characterization.
2. The thermal diode is capable of responding to thermal events of 40°C/s or faster.
3. The AMD Athlon™ XP processor model 8 provides a thermal diode for measuring die temperature of the processor. The
processor relies on thermal circuitry on the motherboard to turn off the regulated core voltage to the processor in response to a
thermal shutdown event. Refer to AMD Athlon™ Processor-Based Motherboard Design Guide, order# 24363, for thermal
protection circuitry designs.
Thermal diode shutdown temperature for processor protection 125 °C1, 2, 3
Maximum allowed time from T
SHUTDOWN
detection to processor shutdown
500 ms 1, 3
8.14 APIC Pins AC and DC Characteristics
Table 19 shows the AMD Athlon XP processor model 8 AC and
DC characteristics of the APIC pins.
Table 19. APIC Pin AC and DC Characteristics
Symbol Parameter Description Condition Min Max Units Notes
V
IH
V
IL
V
OH
V
OL
I
LEAK_P
I
LEAK_N
I
OL
T
RISE
T
FALL
T
SU
T
HD
C
PIN
Notes:
1. Characterized across DC supply voltage range.
2. The 2.625-V value is equal to 2.5 V plus a maximum of five percent.
3. Edge rates indicate the range for characterizing the inputs.
Input High Voltage 1.7 2.625 V 1, 2
Input Low Voltage –300 700 mV 1
Output High Voltage 2.625 V 2
Output Low Voltage –300 400 mV
V
Tristate Leakage Pullup
Tristate Leakage Pulldown
Output Low Current
= VSS (Ground)
IN
= 2.5 V
V
IN
V
Max
OL
–1 mA
1mA
9mA
Signal Rise Time 1.0 3.0 V/ns 3
Signal Fall Time 1.0 3.0 V/ns 3
Setup Time 1 ns
Hold Time 1 ns
Pin Capacitance 4 12 pF
44 Electrical Data Chapter 8
Preliminary Information
25175H—March 2003 AMD Athlon™ XP Processor Model 8 Data Sheet
9 Signal and Power-Up Requirements
The AMD Athlon™ XP processor model 8 is designed to provide
functional operation if the voltage and temperature parameters
are within the limits of normal operating ranges.
9.1 Power-Up Requirements
Signal Sequence and Timing Description
3.3 V Supply
VCCA (2.5 V)
(for PLL)
V
CC_CORE
RESET#
NB_RESET#
PWROK
Figure 13 shows the relationship between key signals in the
system during a power-up sequence. This figure details the
requirements of the processor.
2
1
5
6
4
7
8
Warm reset
condition
FID[3:0]
3
System Clock
Figure 13. Signal Relationship Requirements During Power-Up Sequence
Notes: 1. Figure 13 represents several signals generically by using names not necessarily consistent
with any pin lists or schematics.
2.
Requirements 1–8 in Figure 13 are described in “Power-Up Timing Requirements” on page 46.
Chapter 9 Signal and Power-Up Requirements 45
Preliminary Information
AMD Athlon™ XP Processor Model 8 Data Sheet 25175H—March 2003
Power-Up Timing Requirements.
The signal timing requirements are
as follows:
1. RESET# must be asserted before PWROK is asserted.
The AMD Athlon XP processor model 8 does not set the
correct clock multiplier if PWROK is asserted prior to a
RESET# assertion. It is recommended that RESET# be
asserted at least 10 nanoseconds prior to the assertion of
PWROK.
In practice, a Southbridge asserts RESET# milliseconds
before PWROK is asserted.
2. All motherboard voltage planes must be within
specification before PWROK is asserted.
PWROK is an output of the voltage regulation circuit on the
motherboard. PWROK indicates that V
CC_CORE
and all
other voltage planes in the system are within specification.
The motherboard is required to delay PWROK assertion for
a minimum of three milliseconds from the 3.3 V supply
being within specification. This delay ensures that the
system clock (SYSCLK/SYSCLK#) is operating within
specification when PWROK is asserted.
The processor core voltage, V
CC_CORE
, must be within
specification as dictated by the VID[4:0] pins driven by the
processor before PWROK is asserted. Before PWROK
assertion, the AMD Athlon processor is clocked by a ring
oscillator.
The processor PLL is powered by VCCA. The processor PLL
does not lock if VCCA is not high enough for the processor
logic to switch for some period before PWROK is asserted.
VCCA must be within specification at least five
microseconds before PWROK is asserted.
In practice VCCA, V
CC_CORE
, and all other voltage planes
must be within specification for several milliseconds before
PWROK is asserted.
After PWROK is asserted, the processor PLL locks to its
operational frequency.
3. The system clock (SYSCLK/SYSCLK#) must be running
before PWROK is asserted.
When PWROK is asserted, the processor switches from
driving the internal processor clock grid from the ring
oscillator to driving from the PLL. The reference system
46 Signal and Power-Up Requirements Chapter 9
Preliminary Information
25175H—March 2003 AMD Athlon™ XP Processor Model 8 Data Sheet
clock must be valid at this time. The system clocks are
designed to be running after 3.3 V has been within
specification for three milliseconds.
4. PWROK assertion to deassertion of RESET#
The duration of RESET# assertion during cold boots is
intended to satisfy the time it takes for the PLL to lock with
a less than 1 ns phase error. The processor PLL begins to
run after PWROK is asserted and the internal clock grid is
switched from the ring oscillator to the PLL. The PLL lock
time may take from hundreds of nanoseconds to tens of
microseconds. It is recommended that the minimum time
between PWROK assertion to the deassertion of RESET# be
at least 1.0 milliseconds. Southbridges enforce a delay of
1.5 to 2.0 milliseconds between PWRGD (Southbridge
version of PWROK) assertion and NB_RESET# deassertion.
5. PWROK must be monotonic and meet the timing
requirements as defined in Table 16, “General AC and DC
Characteristics,” on page 39. The processor should not
switch between the ring oscillator and the PLL after the
initial assertion of PWROK.
6. NB_RESET# must be asserted (causing CONNECT to also
assert) before RESET# is deasserted. In practice all
Southbridges enforce this requirement.
If NB_RESET# does not assert until after RESET# has
deasserted, the processor misinterprets the CONNECT
assertion (due to NB_RESET# being asserted) as the
beginning of the SIP transfer. There must be sufficient
overlap in the resets to ensure that CONNECT is sampled
asserted by the processor before RESET# is deasserted.
7. The FID[3:0] signals are valid within 100 ns after PWROK is
asserted. The chipset must not sample the FID[3:0] signals
until they become valid. Refer to the AMD Athlon™
Processor-Based Motherboard Design Guide, order# 24363, for
the specific implementation and additional circuitry
required.
8. The FID[3:0] signals become valid within 100 ns after
RESET# is asserted. Refer to the AMD Athlon™ Processor-
Based Motherboard Design Guide, order# 24363, for the
specific implementation and additional circuitry required.
Chapter 9 Signal and Power-Up Requirements 47
Preliminary Information
AMD Athlon™ XP Processor Model 8 Data Sheet 25175H—March 2003
Clock Multiplier Selection (FID[3:0])
The chipset samples the FID[3:0] signals in a chipset-specific
manner from the processor and uses this information to
determine the correct serial initialization packet (SIP). The
chipset then sends the SIP information to the processor for
configuration of the AMD Athlon system bus for the clock
multiplier that determines the processor frequency indicated
by the FID[3:0] code. The SIP is sent to the processor using the
SIP protocol. This protocol uses the PROCRDY, CONNECT, and
CLKFWDRST signals, that are synchronous to SYSCLK.
For more information about FID[3:0], see “FID[3:0] Pins” on
page 75.
Serial Initialization Packet (SIP) Protocol. Refer to AMD Athlon™
System Bus Specification, order# 21902 for details of the SIP
protocol.
9.2 Processor Warm Reset Requirements
Northbridge Reset Pins
RESET# cannot be asserted to the processor without also being
asserted to the Northbridge. RESET# to the Northbridge is the
same as PCI RESET#. The minimum assertion for PCI RESET#
is one millisecond. Southbridges enforce a minimum assertion
of RESET# for the processor, Northbridge, and PCI of 1.5 to 2.0
milliseconds.
48 Signal and Power-Up Requirements Chapter 9
Preliminary Information
25175H—March 2003 AMD Athlon™ XP Processor Model 8 Data Sheet
10 Mechanical Data
The AMD Athlon™ XP processor model 8 connects to the
motherboard through a Pin Grid Array (PGA) socket named
Socket A. This processor utilizes the organic pin grid array
(OPGA) package type described in this chapter. For more
information, see the AMD Athlon™ Processor-Based Motherboard
Design Guide, order# 24363.
10.1 Die Loading
The processor die on the OPGA package is exposed at the top of
the package. This feature facilitates heat transfer from the die
to an approved heat sink. Any heat sink design should avoid
loads on corners and edges of die. The OPGA package has
compliant pads that serve to bring surfaces in planar contact.
Tool-assisted zero insertion force sockets should be designed so
that no load is placed on the substrate of the package.
Table 20 shows the mechanical loading specifications for the
processor die. It is critical that the mechanical loading of the
heat sink does not exceed the limits shown in Table 20.
Table 20. Mechanical Loading
Location Dynamic (MAX) Static (MAX) Units Note
Die Surface 100 30 lbf 1
Die Edge 10 10 lbf 2
Notes:
1. Load specified for coplanar contact to die surface.
2. Load defined for a surface at no more than a two-degree angle of inclination to die surface.
Chapter 10 Mechanical Data 49
Preliminary Information
AMD Athlon™ XP Processor Model 8 Data Sheet 25175H—March 2003
10.2 Part Number 27291 OPGA Package Dimensions for
AMD Athlon™ XP Processors Model 8 with a CPUID of 680
For AMD Athlon XP processors model 8 with a CPUID of 680,
Table 21 shows the 27291 OPGA package dimensions in
millimeters assigned to the letters and symbols used in the
27291 package diagram, Figure 14 on page 52.
Table 21. Part Number 27291 OPGA Package Dimensions for AMD Athlon™
XP Processors Model 8 with a CPUID of 680
Letter or
Symbol
D/E 49.27 49.78 E9 1.66 1.96
D1/E1 45.72 BSC G/H – 4.50
D2 7.31 REF A 1.942 REF
D3 3.30 3.60 A1 1.00 1.20
D4 10.78 11.33 A2 0.80 0.88
D5 10 .78 11. 33 A 3 0 .116 –
D6 8.13 8.68 A4 – 1.90
D7 12.33 12.88 φP – 6.60
D8 3.05 3.35 φb0.430.50
D9 12.71 13.26 φb1 1.40 REF
E2 11.06 REF S 1.435 2.375
E3 2.35 2.65 L 3.05 3.31
E4 7.87 8.42 M 37
E5 7.87 8.42 N 453
E6 10.73 11.28 e 1.27 BSC
E7 10.73 11.28 e1 2.54 BSC
E8 13.28 13.83
Note:
1. Dimensions are given in millimeters.
2. The mass consists of the completed package, including processor, surface mounted parts, and
pins.
Minimum
Dimension
Maximum
1
Dimension
1
Letter or
Symbol
2
Mass
Minimum
Dimension
11.0 g REF
Maximum
1
Dimension
1
50 Mechanical Data Chapter 10
Preliminary Information
25175H—March 2003 AMD Athlon™ XP Processor Model 8 Data Sheet
10.3 Part Number 27291 OPGA Package Dimensions for
AMD Athlon™ XP Processors Model 8 with a CPUID of 681
For AMD Athlon XP processors model 8 with a CPUID of 681,
Table 22 shows the 27291 OPGA package dimensions in
millimeters assigned to the letters and symbols used in the
27291 package diagram, Figure 14 on page 52.
Table 22. Part Number 27291 OPGA Package Dimensions for
AMD Athlon™ XP Processors Model 8 with a CPUID of 681
Letter or
Symbol
D/E 49.27 49.78 E9 1.66 1.96
D1/E1 45.72 BSC G/H – 4.50
D2 7.47 REF A 1.942 REF
D3 3.30 3.60 A1 1.00 1.20
D4 10.78 11.33 A2 0.80 0.88
D5 10 .78 11. 33 A 3 0 .116 –
D6 8.13 8.68 A4 – 1.90
D7 12.33 12.88 φP – 6.60
D8 3.05 3.35 φb0.430.50
D9 12.71 13.26 φb1 1.40 REF
E2 11.33 RE F S 1.435 2.375
E3 2.35 2.65 L 3.05 3.31
E4 7.87 8.42 M 37
E5 7.87 8.42 N 453
E6 10.73 11.28 e 1.27 BSC
E7 10.73 11.28 e1 2.54 BSC
E8 13.28 13.83
Note:
1. Dimensions are given in millimeters.
2. The mass consists of the completed package, including processor, surface mounted parts, and
pins.
Minimum
Dimension
Maximum
1
Dimension
1
Letter or
Symbol
2
Mass
Minimum
Dimension
11.0 g REF
Maximum
1
Dimension
1
Chapter 10 Mechanical Data 51
Preliminary Information
AMD Athlon™ XP Processor Model 8 Data Sheet 25175H—March 2003
Figure 14. AMD Athlon™ XP Processor Model 8 Part Number 27291 OPGA Package
52 Mechanical Data Chapter 10
Preliminary Information
25175H—March 2003 AMD Athlon™ XP Processor Model 8 Data Sheet
10.4 Part Number 27648 OPGA Package Dimensions for
AMD Athlon™ XP Processors Model 8 with a CPUID of 681
For AMD Athlon XP processors model 8 with a CPUID of 681,
Table 23 shows the part number 27648 OPGA package
dimensions in millimeters assigned to the letters and symbols
used in the 27648 package diagram, Figure 15 on page 54.
Table 23. Part Number 27648 OPGA Package Dimensions for
AMD Athlon™ XP Processors Model 8 with a CPUID of 681
Letter or
Symbol
D/E 49.27 49.78 G/H – 4.50
D1/E1 45.72 BSC A 1.917 REF
D2 7.47 REF A1 0.977 1.177
D3 3.30 3.60 A2 0.80 0.88
D4 10.78 11. 33 A3 0 .116 –
D5 10.78 11.33 A4 – 1.90
D6 8.13 8.68 φP – 6.60
D7 12.33 12.88 φb0.430.50
D8 3.05 3.35 φb1 1.40 REF
D9 12.71 13.26 S 1.435 2.375
E2 11.33 REF L 3.05 3.31
E3 2.35 2.65 M 37
E4 7.87 8.42 N 453
E5 7.87 8.42 e 1.27 BSC
E6 10.73 11.28 e1 2.54 BSC
E8 13.28 13.83
Minimum
Dimension
Maximum
1
Dimension
1
Letter or
Symbol
2
Mass
Minimum
Dimension
11.0 g REF
Maximum
1
Dimension
1
E9 1.66 1. 96
Note:
1. Dimensions are given in millimeters.
2. The mass consists of the completed package, including processor, surface mounted parts, and
pins.
Chapter 10 Mechanical Data 53
Preliminary Information
AMD Athlon™ XP Processor Model 8 Data Sheet 25175H—March 2003
Figure 15. AMD Athlon™ XP Processor Model 8 Part Number 27648 OPGA Package
54 Mechanical Data Chapter 10
Preliminary Information
25175H—March 2003 AMD Athlon™ XP Processor Model 8 Data Sheet
11 Pin Descriptions
This chapter includes pin diagrams of the organic pin grid array
(OPGA) for the AMD Athlon™ XP processor model 8, a listing
of pin name abbreviations, and a cross-referenced listing of pin
locations to signal names.
11.1 Pin Diagram and Pin Name Abbreviations
Figure 16 on page 56 shows the staggered pin grid array (PGA)
for the AMD Athlon™ XP processor model 8. Because some of
the pin names are too long to fit in the grid, they are
abbreviated. Figure 17 on page 57 shows the bottomside view of
the array. Table 24 on page 58 lists all the pins in alphabetical
order by pin name, along with the abbreviation where
necessary.
Chapter 11 Pin Descriptions 55
Preliminary Information
AMD Athlon™ XP Processor Model 8 Data Sheet 25175H—March 2003
B
A
C
F
D
E
G
K
H
J
L
P
M
N
Q
T
R
S
U
X
V
W
Z
Y
AB
AA
AC
AF
AD
AE
AG
AK
AH
AJ
AM
AL
AN
12345678910111213141516171819202122232425262728 293031323334353637
Model 8
Topside Vie w
AMD Athlon™ XP Processor
Figure 16. AMD Athlon™ XP Processor Model 8 Pin Diagram—Topside View
SAO#12 SAO#5 SAO#3 SD#55 SD#61 SD#53 SD#63 SD#62 NC SD#57 SD#39 SD#35 SD#34 SD#44 NC SDOC#2 SD#40 SD#30
VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC
VCC VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS V SS
VSS VSS VSS NC VSS VCC VSS VCC V SS VCC VSS VCC VSS VCC NC VCC VCC VCC
VCC VCC NC NC NC VCC VSS VCC VSS VCC VSS VCC VSS NC NC NC VSS VSS
VSS VSS VSS NC NC VCC VCC VCC
VCC VCC VCC VCC VSS VSS VSS VSS
VSS VSS VSS VSS VCC VCC VCC VCC
VCC VCC VCC VCC VSS VSS VSS VSS
VSS VSS VSS VSS VCC VCC VCC VCC
VCC VCC VCC VCC VSS VSS VSS VSS
VSS VSS VSS VSS VCC VCC VCC VCC
VCC VCC VCC VCC VSS VSS VSS VSS
VSS VSS VSS VSS VCC VCC VCC VCC
VCC VCC VCC NC NC VSS VSS VSS
VSS VSS NC NC NC VSS VCC VSS VCC VSS VCC VSS VCC NC NC NC VCC VCC
VCC VCC AMD NC VCC VSS VCC VSS VCC V SS VCC VSS VCC VSS FSB1 VSS VSS VSS
VSS VSS CPR# NC VCC VSS VCC VSS VCC V SS VCC VSS VCC VSS VCC VSS VCC VCC
SAO#7 SAO#9 SAO#8 SAO#2 SD#54 SDOC#3 NC SD#51 SD#60 SD#59 SD#56 SD#37 SD#47 SD#38 SD#45 SD#43 SD#42 SD#41 SDOC#1
SAO#11 SAOC# SAO#4 SAO#6 SD#52 SD#50 SD#49 SDIC#3 SD#48 SD#58 SD#36 SD#46 NC SDIC#2 SD#33 SD#32 NC SD#31 SD#22
B
A
C
F
D
E
SAO#0 SAO#1 NC VID[4] NC SD#19 SDIC#1 SD#29
SAO#10 SAO#14 SAO#13 KEY KEY NC NC KEY KEY NC NC KEY KEY NC NC NC SD#20 SD#23 SD#21
H
G
VID[0] VID[1] VID[2] VID[3] NC SD#26 NC SD#28
K
M
L
J
TCK TMS SCNSN KEY NC SD#24 SD#17 SD#16
PICCLK PICD#0 PICD#1 KEY NC SD#25 SD#27 S D#18
P
R
Q
N
TDI TRST# TDO THDC NC SD#5 SD#4 NC
FID[0] FID[1] VREF_S NC NC SDIC#0 SD#2 SD#1
SCNCK1 SCNINV SCNCK2 THDA NC SD#7 SD#15 SD#6
T
V
U
S
FID[2] FID[3] NC KEY NC NC SD#3 SD#12
X
Z
Y
W
STPC# PLTST# ZN NC NC S D#10 SD#14 SD#11
DBRDY DBREQ# NC KEY NC SD #8 SD#0 SD#13
AB
AD
AC
AA
FERR RESET# NC KEY KEY COREFB COREFB# KEY KEYNCNCNCNC KEYKEYFSB0SAI#2SAI#11SAI#7
A20M# PWROK ZP NC NC SAI#5 SDOC#0 SD#9
AF
AE
IGNNE# INIT# VCC NC NC NC ANLOG NC NC NC CLKFR VCCA PLBYP# NC SAI#0 SFILLV# SAIC# SAI#6 SAI#3
AK
AH
AG
AJ
NMI SMI# NC NC NC PLMN1 PLBYC CLKIN RCLK K7CO# PRCRDY NC NC SAI#12 SAI#14 SDINV# SAI#13 SAI#9
VCC V SS VSS NC VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS
AM
12345678910111213141516171819202122232425262728 293031323334353637
AN
INTR FLUSH# VCC NC NC NC PLMN2 PLBYC# CLKIN# RCLK# K7CO CNNCT NC NC SAI#1 SDOV# SAI#8 S AI#4 SAI#10
AL
56 Pin Descriptions Chapter 11
Preliminary Information
25175H—March 2003 AMD Athlon™ XP Processor Model 8 Data Sheet
2
4
6
1
3
5
8
7
9
12
14
10
11
13
16
18
15
17
20
19
21
24
22
23
26
28
30
25
27
29
32
31
33
36
34
35
37
Model 8
Bottomside View
AMD Athlon™ XP Processor
Figure 17. AMD Athlon™ XP Processor Model 8 Pin Diagram—Bottomside View
SAO#7 SAO#11 SAO#10 SAO#0 VID[0] PICCLK TCK SCNCK1 TDI FID[0] FID[2] DBRDY STPC# A20M# FERR IGNNE# INTR
VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC
VCC VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VSS
VSS VSS VSS NC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC NC AMD CPR# VSS
VCC VCC NC NC NC VCC VSS VCC VSS VCC VSS VCC VSS NC NC NC NC NC
VSS VSS VSS NC NC VCC VCC VCC
VCC VCC VCC VCC VSS VSS VSS VSS
VSS VSS VSS VSS VCC VCC VCC VCC
VCC VCC VCC VCC VSS VSS VSS VSS
VSS VSS VSS VSS VCC VCC VCC VCC
VCC VCC VCC VCC VSS VSS VSS VSS
VSS VSS VSS VSS VCC VCC VCC VCC
VCC VCC VCC VCC VSS VSS VSS VSS
VSS VSS VSS VSS VCC VCC VCC VCC
VCC VCC VCC NC NC VSS VSS VSS
VSS VSS NC NC NC VSS VCC VSS VCC VSS VCC VSS VCC NC NC FSB1 VCC VCC
VCC VCC VCC NC VCC VSS VCC VSS VCC VSS VCC V SS VCC VSS NC VSS VSS VSS
VSS VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VCC
VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS
A B C D E F G H J K L M N P Q R S T U V W X Y Z AA AB AC AD AE AF AG AH AJ AK AL AM AN
2
1
SAO#5 SAO#8 SAO#4 SAO#13 NC VID[2] PICD#1 SCNSN SCNCK2 TDO VREF_S NC NC ZN ZP NC VCC VCC SMI#
SAO#12 SAO#9 SAOC# SAO#14 SAO#1 VID[1] PICD#0 TMS SCNINV TRST# FID[1] FID[3] DBREQ# PLTST# PWROK RESET# INIT# FLUSH# NMI
4
3
SAO#3 SAO#2 SAO#6 KEY VID[4] VID[3] KEY KEY THDA THDC NC KEY KEY NC NC KEY NC NC NC
6
5
8
7
SD#55 SD#54 SD#52 KEY KEYNCNCNC
10
9
SD#61 SDOC#3 SD#50 NC COREFB NC NC NC
SD#53 NC SD#49 NC COREFB# ANLOG PLMN2 PLMN1
SD#63 SD#51 SDIC#3 KEY KEY NC PLBYC# PLBYC
12
14
13
11
16
15
NC SD#59 SD#58 NC NC NC RCLK# RCLK
SD#62 SD#60 SD#48 KEY KEY NC CLKIN# CLKIN
18
17
SD#57 SD#56 SD#36 NC NC CLKFR K7CO K7CO#
SD#39 SD#37 SD#46 KEY NC VCCA CNNCT PRCRDY
SD#35 SD#47 NC KEY NC PLBYP# NC NC
SD#34 SD#38 SDIC#2 NC KEYNCNCNC
20
21
19
24
22
23
26
25
28
27
NC SD#43 SD#32 NC NC NC NC NC NC NC NC NC NC NC NC FSB0 SFILLV# SDOV# SAI#14
SD#44 SD#45 SD#33 NC KEY SAI#0 SAI#1 SAI#12
30
29
32
31
SD#40 SD#41 SD#31 SD#23 SDIC#1 NC SD#27 SD#17 SD#15 SD#4 SD#2 SD#3 SD#0 SD#14 SDOC#0 SAI#11 SAI#6 SAI#4 SAI#13
SDOC#2 SD #42 NC SD#20 SD#19 SD#26 SD#25 SD#24 SD#7 SD#5 SDIC#0 NC SD#8 SD#10 SAI#5 SAI#2 SAIC# SAI#8 SDINV#
34
33
35
A B C D E F G H J K L M N P Q R S T U V W X Y Z AA AB AC AD AE AF AG AH AJ AK AL AM AN
SD#30 SDOC#1 SD#22 SD #21 SD#29 SD#28 SD#18 SD #16 SD#6 NC SD#1 SD#12 SD#13 SD #11 SD#9 SAI#7 SAI#3 SAI#10 S AI#9
36
37
Chapter 11 Pin Descriptions 57
Preliminary Information
AMD Athlon™ XP Processor Model 8 Data Sheet 25175H—March 2003
Table 24. Pin Name Abbreviations
Abbreviation Full Name Pin
A20M# AE1
AMD AH6
ANLOG ANALOG AJ13
CLKFR CLKFWDRST AJ21
CLKIN AN17
CLKIN# AL17
CNNCT CONNECT AL23
COREFB AG11
COREFB# AG13
CPR# CPU_PRESENCE# AK6
DBRDY AA1
DBREQ# AA3
FERR AG1
FID[0] W1
FID[1] W3
FID[2] Y1
FID[3] Y3
Table 24. Pin Name Abbreviations (continued)
Abbreviation Full Name Pin
KEY AA7
KEY AG7
KEY AG9
KEY AG15
KEY AG17
KEY AG27
KEY AG29
NC A19
NC A31
NC C13
NC E25
NC E33
NC F8
NC F30
NC G11
NC G13
NC G19
FLUSH# AL3
FSB0 FSB_Sense[0] AG31
FSB1 FSB_Sense[1] AH30
IGNNE# AJ1
INIT# AJ3
INTR AL1
K7CO K7CLKOUT AL21
K7CO# K7CLKOUT# AN21
KEY G7
KEY G9
KEY G15
KEY G17
KEY G23
KEY G25
KEY N7
KEY Q7
KEY Y7
NC G21
NC G27
NC G29
NC G31
NC H6
NC H8
NC H10
NC H28
NC H30
NC H32
NC J5
NC J31
NC K8
NC K30
NC L31
NC L35
NC N31
58 Pin Descriptions Chapter 11
Preliminary Information
25175H—March 2003 AMD Athlon™ XP Processor Model 8 Data Sheet
Table 24. Pin Name Abbreviations (continued)
Abbreviation Full Name Pin
NC Q31
NC S31
NC U31
NC U37
NC W7
NC W31
NC Y5
NC Y31
NC Y33
NC AA5
NC AA31
NC AC7
NC AC31
NC AD8
NC AD30
NC AE7
NC AE31
Table 24. Pin Name Abbreviations (continued)
Abbreviation Full Name Pin
NC AJ19
NC AJ27
NC AK8
NC AL7
NC AL9
NC AL11
NC AL25
NC AL27
NC AM8
NC AN7
NC AN9
NC AN11
NC AN25
NC AN27
NMI AN3
PICCLK N1
PICD#0 PICD[0]# N3
NC AF6
NC AF8
NC AF10
NC AF28
NC AF30
NC AF32
NC AG5
NC AG19
NC AG21
NC AG23
NC AG25
NC AH8
NC AJ7
NC AJ9
NC AJ11
NC AJ15
NC AJ17
PICD#1 PICD[1]# N5
PLBYP# PLLBYPASS# AJ25
PLBYC PLLBYPASSCLK AN15
PLBYC# PLLBYPASSCLK# AL15
PLMN1 PLLMON1 AN13
PLMN2 PLLMON2 AL13
PLTST# PLLTEST# AC3
PRCRDY PROCREADY AN23
PWROK AE3
RESET# AG3
RCLK RSTCLK AN19
RCLK# RSTCLK# AL19
SAI#0 SADDIN[0]# AJ29
SAI#1 SADDIN[1]# AL29
SAI#2 SADDIN[2]# AG33
SAI#3 SADDIN[3]# AJ37
SAI#4 SADDIN[4]# AL35
Chapter 11 Pin Descriptions 59
Preliminary Information
AMD Athlon™ XP Processor Model 8 Data Sheet 25175H—March 2003
Table 24. Pin Name Abbreviations (continued)
Abbreviation Full Name Pin
SAI#5 SADDIN[5]# AE33
SAI#6 SADDIN[6]# AJ35
SAI#7 SADDIN[7]# AG37
SAI#8 SADDIN[8]# AL33
SAI#9 SADDIN[9]# AN37
SAI#10 SADDIN[10]# AL37
SAI#11 SADDIN[11]# AG35
SAI#12 SADDIN[12]# AN29
SAI#13 SADDIN[13]# AN35
SAI#14 SADDIN[14]# AN31
SAIC# SADDINCLK# AJ33
SAO#0 SADDOUT[0]# J1
SAO#1 SADDOUT[1]# J3
SAO#2 SADDOUT[2]# C7
SAO#3 SADDOUT[3]# A7
SAO#4 SADDOUT[4]# E5
SAO#5 SADDOUT[5]# A5
Table 24. Pin Name Abbreviations (continued)
Abbreviation Full Name Pin
SD#3 SDATA[3]# Y35
SD#4 SDATA[4]# U35
SD#5 SDATA[5]# U33
SD#6 SDATA[6]# S37
SD#7 SDATA[7]# S33
SD#8 SDATA[8]# AA33
SD#9 SDATA[9]# AE37
SD#10 SDATA[10]# AC33
SD#11 SDATA[11]# AC37
SD#12 SDATA[12]# Y37
SD#13 SDATA[13]# AA37
SD#14 SDATA[14]# AC35
SD#15 SDATA[15]# S35
SD#16 SDATA[16]# Q37
SD#17 SDATA[17]# Q35
SD#18 SDATA[18]# N37
SD#19 SDATA[19]# J33
SAO#6 SADDOUT[6]# E7
SAO#7 SADDOUT[7]# C1
SAO#8 SADDOUT[8]# C5
SAO#9 SADDOUT[9]# C3
SAO#10 SADDOUT[10]# G1
SAO#11 SADDOUT[11]# E1
SAO#12 SADDOUT[12]# A3
SAO#13 SADDOUT[13]# G5
SAO#14 SADDOUT[14]# G3
SAOC# SADDOUTCLK# E3
SCNCK1 SCANCLK1 S1
SCNCK2 SCANCLK2 S5
SCNINV SCANINTEVAL S3
SCNSN SCANSHIFTEN Q5
SD#0 SDATA[0]# AA35
SD#1 SDATA[1]# W37
SD#2 SDATA[2]# W35
SD#20 SDATA[20]# G33
SD#21 SDATA[21]# G37
SD#22 SDATA[22]# E37
SD#23 SDATA[23]# G35
SD#24 SDATA[24]# Q33
SD#25 SDATA[25]# N33
SD#26 SDATA[26]# L33
SD#27 SDATA[27]# N35
SD#28 SDATA[28]# L37
SD#29 SDATA[29]# J37
SD#30 SDATA[30]# A37
SD#31 SDATA[31]# E35
SD#32 SDATA[32]# E31
SD#33 SDATA[33]# E29
SD#34 SDATA[34]# A27
SD#35 SDATA[35]# A25
SD#36 SDATA[36]# E21
60 Pin Descriptions Chapter 11
Preliminary Information
25175H—March 2003 AMD Athlon™ XP Processor Model 8 Data Sheet
Table 24. Pin Name Abbreviations (continued)
Abbreviation Full Name Pin
SD#37 SDATA[37]# C23
SD#38 SDATA[38]# C27
SD#39 SDATA[39]# A23
SD#40 SDATA[40]# A35
SD#41 SDATA[41]# C35
SD#42 SDATA[42]# C33
SD#43 SDATA[43]# C31
SD#44 SDATA[44]# A29
SD#45 SDATA[45]# C29
SD#46 SDATA[46]# E23
SD#47 SDATA[47]# C25
SD#48 SDATA[48]# E17
SD#49 SDATA[49]# E13
SD#50 SDATA[50]# E11
SD#51 SDATA[51]# C15
SD#52 SDATA[52]# E9
SD#53 SDATA[53]# A13
SD#54 SDATA[54]# C9
SD#55 SDATA[55]# A9
SD#56 SDATA[56]# C21
SD#57 SDATA[57]# A21
SD#58 SDATA[58]# E19
SD#59 SDATA[59]# C19
SD#60 SDATA[60]# C17
SD#61 SDATA[61]# A11
SD#62 SDATA[62]# A17
SD#63 SDATA[63]# A15
SDIC#0 SDATAINCLK[0]# W33
SDIC#1 SDATAINCLK[1]# J35
SDIC#2 SDATAINCLK[2]# E27
SDIC#3 SDATAINCLK[3]# E15
SDINV# SDATAINVALID# AN33
SDOC#0 SDATAOUTCLK[0]# AE35
SDOC#1 SDATAOUTCLK[1]# C37
Table 24. Pin Name Abbreviations (continued)
Abbreviation Full Name Pin
SDOC#2 SDATAOUTCLK[2]# A33
SDOC#3 SDATAOUTCLK[3]# C11
SDOV# SDATAOUTVALID# AL31
SFILLV# SFILLVALID# AJ31
SMI# AN5
STPC# STPCLK# AC1
TCK Q1
TDI U1
TDO U5
THDA THERMDA S7
THDC THERMDC U7
TMS Q3
TRST# U3
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
V
CC_CORE
V
CC_CORE
V
CC_CORE
V
CC_CORE
V
CC_CORE
V
CC_CORE
V
CC_CORE
V
CC_CORE
V
CC_CORE
V
CC_CORE
V
CC_CORE
V
CC_CORE
V
CC_CORE
V
CC_CORE
V
CC_CORE
V
CC_CORE
V
CC_CORE
V
CC_CORE
V
CC_CORE
V
CC_CORE
V
CC_CORE
B4
B8
B12
B16
B20
B24
B28
B32
B36
D2
D4
D8
D12
D16
D20
D24
D28
D32
F12
F16
F20
Chapter 11 Pin Descriptions 61
Preliminary Information
AMD Athlon™ XP Processor Model 8 Data Sheet 25175H—March 2003
Table 24. Pin Name Abbreviations (continued)
Abbreviation Full Name Pin
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
V
CC_CORE
V
CC_CORE
V
CC_CORE
V
CC_CORE
V
CC_CORE
V
CC_CORE
V
CC_CORE
V
CC_CORE
V
CC_CORE
V
CC_CORE
V
CC_CORE
V
CC_CORE
V
CC_CORE
V
CC_CORE
V
CC_CORE
V
CC_CORE
V
CC_CORE
V
CC_CORE
V
CC_CORE
V
CC_CORE
V
CC_CORE
V
CC_CORE
V
CC_CORE
V
CC_CORE
V
CC_CORE
V
CC_CORE
V
CC_CORE
V
CC_CORE
V
CC_CORE
V
CC_CORE
V
CC_CORE
V
CC_CORE
V
CC_CORE
V
CC_CORE
F24
F28
F32
F34
F36
H2
H4
H12
H16
H20
H24
K32
K34
K36
M2
M4
M6
M8
P30
P32
P34
P36
R2
R4
R6
R8
T30
T32
T34
T36
V2
V4
V6
V8
Table 24. Pin Name Abbreviations (continued)
Abbreviation Full Name Pin
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
V
CC_CORE
V
CC_CORE
V
CC_CORE
V
CC_CORE
V
CC_CORE
V
CC_CORE
V
CC_CORE
V
CC_CORE
V
CC_CORE
V
CC_CORE
V
CC_CORE
V
CC_CORE
V
CC_CORE
V
CC_CORE
V
CC_CORE
V
CC_CORE
V
CC_CORE
V
CC_CORE
V
CC_CORE
V
CC_CORE
V
CC_CORE
V
CC_CORE
V
CC_CORE
V
CC_CORE
V
CC_CORE
V
CC_CORE
V
CC_CORE
V
CC_CORE
V
CC_CORE
V
CC_CORE
V
CC_CORE
V
CC_CORE
V
CC_CORE
V
CC_CORE
X30
X32
X34
X36
Z2
Z4
Z6
Z8
AB30
AB32
AB34
AB36
AD2
AD4
AD6
AF14
AF18
AF22
AF26
AF34
AF36
AH2
AH4
AH10
AH14
AH18
AH22
AH26
AK10
AK14
AK18
AK22
AK26
AK30
62 Pin Descriptions Chapter 11
Preliminary Information
25175H—March 2003 AMD Athlon™ XP Processor Model 8 Data Sheet
Table 24. Pin Name Abbreviations (continued)
Abbreviation Full Name Pin
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VREF_S VREF_SYS W5
V
CC_CORE
V
CC_CORE
V
CC_CORE
V
CC_CORE
V
CC_CORE
V
CC_CORE
V
CC_CORE
V
CC_CORE
V
CC_CORE
V
CC_CORE
V
CC_CORE
V
CC_CORE
V
CC_CORE
V
CC_CORE
AK34
AK36
AJ5
AL5
AM2
AM10
AM14
AM18
AM22
AM26
AM22
AM26
AM30
AM34
VCCA AJ23
VID[0] L1
VID[1] L3
VID[2] L5
VID[3] L7
VID[4] J7
VSS B2
VSS B6
VSS B10
VSS B14
VSS B18
VSS B22
VSS B26
VSS B30
VSS B34
VSS D6
VSS D10
VSS D14
VSS D18
Table 24. Pin Name Abbreviations (continued)
Abbreviation Full Name Pin
VSS D22
VSS D26
VSS D30
VSS D34
VSS D36
VSS F2
VSS F4
VSS F6
VSS F10
VSS F14
VSS F18
VSS F22
VSS F26
VSS H14
VSS H18
VSS H22
VSS H26
VSS H34
VSS H36
VSS K2
VSS K4
VSS K6
VSS M30
VSS M32
VSS M34
VSS M36
VSS P2
VSS P4
VSS P6
VSS P8
VSS R30
VSS R32
VSS R34
VSS R36
Chapter 11 Pin Descriptions 63
Preliminary Information
AMD Athlon™ XP Processor Model 8 Data Sheet 25175H—March 2003
Table 24. Pin Name Abbreviations (continued)
Abbreviation Full Name Pin
VSS T2
VSS T4
VSS T6
VSS T8
VSS V30
VSS V32
VSS V34
VSS V36
VSS X2
VSS X4
VSS X6
VSS X8
VSS Z30
VSS Z32
VSS Z34
VSS Z36
VSS AB2
Table 24. Pin Name Abbreviations (continued)
Abbreviation Full Name Pin
VSS AH36
VSS AK2
VSS AK4
VSS AK12
VSS AK16
VSS AK20
VSS AK24
VSS AK28
VSS AK32
VSS AM4
VSS AM6
VSS AM12
VSS AM16
VSS AM20
VSS AM24
VSS AM28
VSS AM32
VSS AB8
VSS AB4
VSS AB6
VSS AD32
VSS AD34
VSS AD36
VSS AF2
VSS AF4
VSS AF12
VSS AF16
VSS AH12
VSS AH16
VSS AH20
VSS AH24
VSS AH28
VSS AH32
VSS AH34
VSS AM36
ZN AC5
ZP AE5
64 Pin Descriptions Chapter 11
Preliminary Information
25175H—March 2003 AMD Athlon™ XP Processor Model 8 Data Sheet
11.2 Pin List
Table 25 on page 66 cross-references Socket A pin location to
signal name.
The “L” (Level) column shows the electrical specification for
this pin. “P” indicates a push-pull mode driven by a single
source. “O” indicates open-drain mode that allows devices to
share the pin.
Note: The AMD Athlon processor supports push-pull drivers. For
more information, see “Push-Pull (PP) Drivers” on page 6.
The “P” (Port) column indicates if this signal is an input (I),
output (O), or bidirectional (B) signal. The “R” (Reference)
column indicates if this signal should be referenced to VSS (G)
or V
CC_CORE
respect to the current return paths.
(P) planes for the purpose of signal routing with
Chapter 11 Pin Descriptions 65
Preliminary Information
AMD Athlon™ XP Processor Model 8 Data Sheet 25175H—March 2003
Table 25. Cross-Reference by Pin Location
Pin Name Description L P R
A1
A3 SADDOUT[12]# P O
A5 SADDOUT[5]# P O
A7 SADDOUT[3]# P O
A9 SDATA[55]# P B
A11 SDATA[61]# P B
A13 SDATA[53]# P B
A15 SDATA[63]# P B
A17 SDATA[62]# P B
A19 NC Pin page 78 - -
A21 SDATA[57]# P B
A23 SDATA[39]# P B
A25 SDATA[35]# P B
A27 SDATA[34]# P B
No Pin
page 78 - - -
Table 25. Cross-Reference by Pin Location
Pin Name Description L P R
B24
B26 VSS ---
G
G
B28
B30 VSS ---
G
P
B32
B34 VSS ---
P
G
B36
C1 SADDOUT[7]# P O G
G
C3 SADDOUT[9]# P O G
G
C5 SADDOUT[8]# P O G
-
C7 SADDOUT[2]# P O G
G
C9 SDATA[54]# P B P
G
C11 SDATAOUTCLK[3]# P O G
P
C13 NC Pin page 78 - - -
P
V
CC_CORE
V
CC_CORE
V
CC_CORE
V
CC_CORE
---
---
---
---
A29 SDATA[44]# P B
A31 NC Pin page 78 - -
A33 SDATAOUTCLK[2]# P O
A35 SDATA[40]# P B
A37 SDATA[30]# P B
B2 VSS - -
B4
V
CC_CORE
---
G
-
P
G
P
-
B6 VSS ---
B8
V
CC_CORE
---
B10 VSS ---
B12
V
CC_CORE
---
B14 VSS ---
B16
V
CC_CORE
---
B18 VSS ---
B20
V
CC_CORE
---
B22 VSS ---
C15 SDATA[51]# P B P
C17 SDATA[60]# P B G
C19 SDATA[59]# P B G
C21 SDATA[56]# P B G
C23 SDATA[37]# P B P
C25 SDATA[47]# P B G
C27 SDATA[38]# P B G
C29 SDATA[45]# P B G
C31 SDATA[43]# P B G
C33 SDATA[42]# P B G
C35 SDATA[41]# P B G
C37 SDATAOUTCLK[1]# P O G
D2
D4
V
CC_CORE
V
CC_CORE
---
---
D6 VSS ---
D8
V
CC_CORE
---
66 Pin Descriptions Chapter 11
Preliminary Information
25175H—March 2003 AMD Athlon™ XP Processor Model 8 Data Sheet
Table 25. Cross-Reference by Pin Location
(continued)
Pin Name Description L P R
D10 VSS ---
D12
V
CC_CORE
---
D14 VSS ---
D16
V
CC_CORE
---
D18 VSS ---
D20
V
CC_CORE
---
D22VSS ---
D24
V
CC_CORE
---
D26VSS ---
D28
V
CC_CORE
---
D30VSS ---
D32
V
CC_CORE
---
D34VSS ---
D36VSS ---
Table 25. Cross-Reference by Pin Location
Pin Name Description L P R
E33 NC Pin page 78 - - -
E35 SDATA[31]# P B P
E37 SDATA[22]# P B G
F2 VSS ---
F4 VSS ---
F6 VSS ---
F8 NC Pin page 78 - - -
F10 VSS ---
F12
F14 VSS ---
F16
F18 VSS ---
F20
F22 VSS ---
V
CC_CORE
V
CC_CORE
V
CC_CORE
---
---
---
E1 SADDOUT[11]# P O P
E3 SADDOUTCLK# P O G
E5 SADDOUT[4]# P O P
E7 SADDOUT[6]# P O G
E9 SDATA[52]# P B P
E11 SDATA[50]# P B P
E13 SDATA[49]# P B G
E15 SDATAINCLK[3]# P I G
E17 SDATA[48]# P B P
E19 SDATA[58]# P B G
E21 SDATA[36]# P B P
E23 SDATA[46]# P B P
E25 NC Pin page 78 - - -
E27 SDATAINCLK[2]# P I G
E29 SDATA[33]# P B P
E31 SDATA[32]# P B P
F24
V
CC_CORE
---
F26 VSS ---
F28
V
CC_CORE
---
F30 NC Pin page 78 - - -
F32
F34
F36
V
CC_CORE
V
CC_CORE
V
CC_CORE
---
---
---
G1 SADDOUT[10]# P O P
G3 SADDOUT[14]# P O G
G5 SADDOUT[13]# P O G
G7 Key Pin page 78 - - -
G9 Key Pin page 78 - - -
G11 NC Pin page 78 - - -
G13 NC Pin page 78 - - -
G15 Key Pin page 78 - - -
G17 Key Pin page 78 - - -
Chapter 11 Pin Descriptions 67
Preliminary Information
AMD Athlon™ XP Processor Model 8 Data Sheet 25175H—March 2003
Table 25. Cross-Reference by Pin Location
(continued)
Pin Name Description L P R
G19 NC Pin page 78 - - -
G21 NC Pin page 78 - - -
G23 Key Pin page 78 - - -
G25 Key Pin page 78 - - -
G27 NC Pin page 78 - - -
G29 NC Pin page 78 - - -
G31 NC Pin page 78 - - -
G33 SDATA[20]# P B G
G35 SDATA[23]# P B G
G37 SDATA[21]# P B G
H2
H4
V
CC_CORE
V
CC_CORE
---
---
H6 NC Pin page 78 - - -
H8 NC Pin page 78 - - -
H10 NC Pin page 78 - - -
Table 25. Cross-Reference by Pin Location
Pin Name Description L P R
J5 NC Pin page 78 - - -
J7 VID[4] page 79 O O -
J31 NC Pin page 78 - - -
J33 SDATA[19]# P B G
J35 SDATAINCLK[1]# P I P
J37 SDATA[29]# P B P
K2 VSS ---
K4 VSS ---
K6 VSS ---
K8 NC Pin page 78 - - -
K30 NC Pin page 78 - - -
K32
K34
K36
L1 VID[0] page 79 O O -
V
CC_CORE
V
CC_CORE
V
CC_CORE
---
---
---
H12
V
CC_CORE
---
H14 VSS ---
H16
V
CC_CORE
---
H18 VSS ---
H20
V
CC_CORE
---
H22VSS ---
H24
V
CC_CORE
---
H26VSS ---
H28 NC Pin page 78 - - -
H30 NC Pin page 78 - - -
H32 NC Pin page 78 - - -
H34VSS ---
H36VSS ---
J1 SADDOUT[0]# page 79 P O -
J3 SADDOUT[1]# page 79 P O -
L3 VID[1] page 79 O O -
L5 VID[2] page 79 O O -
L7 VID[3] page 79 O O -
L31 NC Pin page 78 - - -
L33 SDATA[26]# P B P
L35 NC Pin page 78 - - -
L37 SDATA[28]# P B P
M2
M4
M6
M8
V
CC_CORE
V
CC_CORE
V
CC_CORE
V
CC_CORE
---
---
---
---
M30VSS ---
M32VSS ---
M34VSS ---
M36VSS ---
68 Pin Descriptions Chapter 11
Preliminary Information
25175H—March 2003 AMD Athlon™ XP Processor Model 8 Data Sheet
Table 25. Cross-Reference by Pin Location
(continued)
Pin Name Description L P R
N1 PICCLK page 74 O I -
N3 PICD#[0] page 74 O B -
N5 PICD#[1] page 74 O B -
N7 Key Pin page 78 - - -
N31 NC Pin page 78 - - -
N33 SDATA[25]# P B P
N35 SDATA[27]# P B P
N37 SDATA[18]# P B G
P2 VSS ---
P4 VSS ---
P6 VSS ---
P8 VSS ---
P30
P32
P34
P36
Q1 TCK page 77 P I
Q3 TMS page 77 P I
Q5 SCANSHIFTEN page 79 P I
V
CC_CORE
V
CC_CORE
V
CC_CORE
V
CC_CORE
---
---
---
---
-
-
-
Table 25. Cross-Reference by Pin Location
Pin Name Description L P R
R34 VSS ---
R36 VSS ---
S1 SCANCLK1 page 79 P I -
S3 SCANINTEVAL page 79 P I -
S5 SCANCLK2 page 79 P I -
S7 THERMDA page 79 - - -
S31 NC Pin page 78 - - -
S33 SDATA[7]# P B G
S35 SDATA[15]# P B P
S37 SDATA[6]# P B G
T2 VSS ---
T4 VSS ---
T6 VSS ---
T8 VSS ---
T30
T32
T34
T36
U1 TDI page 77 P I -
V
CC_CORE
V
CC_CORE
V
CC_CORE
V
CC_CORE
---
---
---
---
Q7 Key Pin page 78 - -
Q31 NC Pin page 78 - -
Q33 SDATA[24]# P B
Q35 SDATA[17]# P B
Q37 SDATA[16]# P B
R2
R4
R6
R8
V
CC_CORE
V
CC_CORE
V
CC_CORE
V
CC_CORE
---
---
---
---
R30 VSS ---
R32 VSS ---
U3 TRST# page 77 P I -
-
U5 TDO page 77 P O -
-
U7 THERMDC page 79 - - -
P
U31 NC Pin page 78 - - -
G
U33 SDATA[5]# P B G
G
U35 SDATA[4]# P B G
U37 NC Pin page 78 - - -
V2
V4
V6
V8
V
CC_CORE
V
CC_CORE
V
CC_CORE
V
CC_CORE
---
---
---
---
Chapter 11 Pin Descriptions 69
Preliminary Information
AMD Athlon™ XP Processor Model 8 Data Sheet 25175H—March 2003
Table 25. Cross-Reference by Pin Location
(continued)
Pin Name Description L P R
V30 VSS ---
V32 VSS ---
V34 VSS ---
V36 VSS ---
W1 FID[0] page 76 O O -
W3 FID[1] page 76 O O -
W5 VREFSYS page 80 P - -
W7 NC Pin page 78 - - -
W31 NC Pin page 78 - - -
W33 SDATAINCLK[0]# P I G
W35 SDATA[2]# P B G
W37 SDATA[1]# P B P
X2 VSS ---
X4 VSS ---
Table 25. Cross-Reference by Pin Location
Pin Name Description L P R
Z6
Z8
Z30 VSS ---
Z32 VSS ---
Z34 VSS ---
Z36 VSS ---
AA1 DBRDY page 75 P O -
AA3 DBREQ# page 75 P I -
AA5NC ---
AA7 Key Pin page 78 - - -
AA31 NC Pin page 78 - - -
AA33 SDATA[8]# P B P
AA35 SDATA[0]# P B G
AA37 SDATA[13]# P B G
V
CC_CORE
V
CC_CORE
---
---
X6 VSS ---
X8 VSS ---
X30
X32
X34
X36
V
CC_CORE
V
CC_CORE
V
CC_CORE
V
CC_CORE
---
---
---
---
Y1 FID[2] page 76 O O -
Y3 FID[3] page 76 O O -
Y5 NC Pin page 78 - - -
Y7 Key Pin page 78 - - -
Y31 NC Pin page 78 - - -
Y33 NC Pin page 78 - - -
Y35 SDATA[3]# P B G
Y37 SDATA[12]# P B P
Z2
Z4
V
CC_CORE
V
CC_CORE
---
---
AB2VSS ---
AB4VSS ---
AB6VSS ---
AB8VSS ---
AB30
AB32
AB34
AB36
V
CC_CORE
V
CC_CORE
V
CC_CORE
V
CC_CORE
---
---
---
---
AC1 STPCLK# page 79 P I -
AC3 PLLTEST# page 78 P I -
AC5 ZN page 80 P - -
AC7NC ---
AC31 NC Pin page 78 - - -
AC33 SDATA[10]# P B P
AC35 SDATA[14]# P B G
AC37 SDATA[11]# P B G
70 Pin Descriptions Chapter 11
Preliminary Information
25175H—March 2003 AMD Athlon™ XP Processor Model 8 Data Sheet
Table 25. Cross-Reference by Pin Location
(continued)
Pin Name Description L P R
AD2
AD4
AD6
V
CC_CORE
V
CC_CORE
V
CC_CORE
---
---
---
AD8 NC Pin page 78 - -
AD30 NC Pin page 78 - -
AD32 VSS - -
AD34 VSS - -
AD36 VSS - -
AE1 A20M# P I
AE3 PWROK P I
AE5 ZP page 80 P -
AE7 NC - -
AE31 NC Pin page 78 - -
AE33 SADDIN[5]# P I
Table 25. Cross-Reference by Pin Location
Pin Name Description L P R
AF30 NC Pin page 78 - - -
AF32 NC Pin page 78 - - -
AF34
-
AF36
AG1 FERR page 75 P O -
-
AG3 RESET# - I -
-
AG5 NC Pin page 78 - - -
-
AG7 Key Pin page 78 - - -
-
AG9 Key Pin page 78 - - -
-
AG11COREFB page75 ---
-
AG13COREFB# page75 ---
-
AG15 Key Pin page 78 - - -
-
AG17 Key Pin page 78 - - -
-
AG19 NC Pin page 78 - - -
G
V
CC_CORE
V
CC_CORE
---
---
AE35 SDATAOUTCLK[0]# P O
AE37 SDATA[9]# P B
AF2 VSS - -
AF4 VSS - -
AF6 NC Pin page 78 - -
AF8 NC Pin page 78 - -
AF10 NC Pin page 78 - -
AF12 VSS - -
AF14
V
CC_CORE
---
P
G
-
-
-
-
-
-
AF16VSS ---
AF18
V
CC_CORE
---
AF20VSS ---
AF22
V
CC_CORE
---
AF24VSS ---
AF26
V
CC_CORE
---
AF28 NC Pin page 78 - - -
AG21 NC Pin page 78 - - -
AG23 NC Pin page 78 - - -
AG25 NC Pin page 78 - - -
AG27 Key Pin page 78 - - -
AG29 Key Pin page 78 - - -
AG31 FSB_Sense[0] page 77 - O G
AG33 SADDIN[2]# P I G
AG35 SADDIN[11]# P I G
AG37 SADDIN[7]# P I P
AH2
AH4
V
CC_CORE
V
CC_CORE
---
---
AH6AMD Pin page74 ---
AH8 NC Pin page 78 - - -
AH10
V
CC_CORE
---
AH12VSS ---
AH14
V
CC_CORE
---
Chapter 11 Pin Descriptions 71
Preliminary Information
AMD Athlon™ XP Processor Model 8 Data Sheet 25175H—March 2003
Table 25. Cross-Reference by Pin Location
(continued)
Pin Name Description L P R
AH16VSS ---
AH18
V
CC_CORE
---
AH20VSS ---
AH22
V
CC_CORE
---
AH24VSS ---
AH26
V
CC_CORE
---
AH28VSS ---
AH30 FSB_Sense[1] page 77 - O G
AH32VSS ---
AH34VSS ---
AH36VSS ---
AJ1 IGNNE# page 77 P I -
AJ3 INIT# page 77 P I -
AJ5
V
CC_CORE
---
AJ7 NC Pin page 78 - - -
AJ9 NC Pin page 78 - - -
Table 25. Cross-Reference by Pin Location
Pin Name Description L P R
AK2 VSS - - -
AK4 VSS - - -
AK6 CPU_PRESENCE# page 75 - - -
AK8 NC Pin page 78 - - -
AK10
AK12 VSS - - -
AK14
AK16 VSS - - -
AK18
AK20 VSS - - -
AK22
AK24 VSS - - -
AK26
AK28 VSS - - -
AK30
AK32 VSS - - -
V
CC_CORE
V
CC_CORE
V
CC_CORE
V
CC_CORE
V
CC_CORE
V
CC_CORE
---
---
---
---
---
---
AJ11 NC Pin page 78 - - -
AJ13 Analog page 74 - - -
AJ15 NC Pin page 78 - - -
AJ17 NC Pin page 78 - - -
AJ19 NC Pin page 78 - - -
AJ21 CLKFWDRST page 74 P I P
AJ23 VCCA page 79 - - -
AJ25 PLLBYPASS# page 78 P I -
AJ27 NC Pin page 78 - - -
AJ29 SADDIN[0]# page 79 P I -
AJ31 SFILLVALID# P I G
AJ33 SADDINCLK# P I G
AJ35 SADDIN[6]# P I P
AJ37 SADDIN[3]# P I G
AK34
AK36
V
CC_CORE
V
CC_CORE
---
---
AL1 INTR page 77 P I -
AL3 FLUSH# page 77 P I -
AL5
V
CC_CORE
---
AL7 NC Pin page 78 - - -
AL9 NC Pin page 78 - - -
AL11 NC Pin page 78 - - -
AL13 PLLMON2 page 78 O O -
AL15 PLLBYPASSCLK# page 78 P I -
AL17 CLKIN# page 74 P I P
AL19 RSTCLK# page 74 P I P
AL21 K7CLKOUT page 78 P O -
AL23 CONNECT page 75 P I P
72 Pin Descriptions Chapter 11
Preliminary Information
25175H—March 2003 AMD Athlon™ XP Processor Model 8 Data Sheet
Table 25. Cross-Reference by Pin Location
Pin Name Description L P R
AL25 NC Pin page 78 - - -
AL27 NC Pin page 78 - - -
AL29 SADDIN[1]# page 79 P I -
AL31 SDATAOUTVALID# P O P
AL33 SADDIN[8]# P I P
AL35 SADDIN[4]# P I G
AL37 SADDIN[10]# P I G
AM2
AM4VSS ---
AM6VSS ---
AM8 NC Pin page 78 - - -
AM10
AM12VSS ---
AM14
AM16VSS ---
V
CC_CORE
V
CC_CORE
V
CC_CORE
---
---
---
Table 25. Cross-Reference by Pin Location
Pin Name Description L P R
AN11 NC Pin page 78 - - -
AN13 PLLMON1 page 78 O B -
AN15 PLLBYPASSCLK page 78 P I -
AN17 CLKIN page 74 P I P
AN19 RSTCLK page 74 P I P
AN21 K7CLKOUT# page 78 P O -
AN23 PROCRDY P O P
AN25 NC Pin page 78 - - -
AN27 NC Pin page 78 - - -
AN29 SADDIN[12]# P I G
AN31 SADDIN[14]# P I G
AN33 SDATAINVALID# P I P
AN35 SADDIN[13]# P I G
AN37 SADDIN[9]# P I G
AM18
V
CC_CORE
---
AM20VSS ---
AM22
V
CC_CORE
---
AM24VSS ---
AM26
V
CC_CORE
---
AM28VSS ---
AM30
V
CC_CORE
---
AM32VSS ---
AM34
V
CC_CORE
---
AM36VSS ---
AN1 No Pin page 78 - - -
AN3 NMI P I -
AN5 SMI# P I -
AN7 NC Pin page 78 - - -
AN9 NC Pin page 78 - - -
Chapter 11 Pin Descriptions 73
Preliminary Information
AMD Athlon™ XP Processor Model 8 Data Sheet 25175H—March 2003
11.3 Detailed Pin Descriptions
The information in this section pertains to Table 25 on page 66.
A20M# Pin A20M# is an input from the system used to simulate address
wrap-around in the 20-bit 8086.
AMD Pin AMD Socket A processors do not implement a pin at location
AH6. All Socket A designs must have a top plate or cover that
blocks this pin location. When the cover plate blocks this
location, a non-AMD part (e.g., PGA370) does not fit into the
socket. However, socket manufacturers are allowed to have a
contact loaded in the AH6 position. Therefore, motherboard
socket design should account for the possibility that a contact
could be loaded in this position.
AMD Athlon™ System Bus Pins
Analog Pin Treat this pin as a NC.
APIC Pins, PICCLK, PICD[1:0]#
CLKFWDRST Pin CLKFWDRST resets clock-forward circuitry for both the system
See the AMD Athlon™ System Bus Specification, order# 21902
for information about the system bus pins—PROCRDY,
PWROK, RESET#, SADDIN[14:2]#, SADDINCLK#,
SADDOUT[14:2]#, SADDOUTCLK#, SDATA[63:0]#,
SDATAINCLK[3:0]#, SDATAINVALID#, SDATAOUTCLK[3:0]#,
SDATAOUTVALID#, SFILLVALID#.
The Advanced Programmable Interrupt Controller (APIC) is a
feature that provides a flexible and expandable means of
delivering interrupts in a system using an AMD processor. The
pins, PICD[1:0], are the bi-directional message-passing signals
used for the APIC and are driven to the Southbridge or a
dedicated I/O APIC. The pin, PICCLK, must be driven with a
valid clock input.
For more information, see Table 19, “APIC Pin AC and DC
Characteristics,” on page 44.
and processor.
CLKIN, RSTCLK (SYSCLK) Pins
74 Pin Descriptions Chapter 11
Connect CLKIN with RSTCLK and name it SYSCLK. Connect
CLKIN# with RSTCLK# and name it SYSCLK#. Length match
the clocks from the clock generator to the Northbridge and
processor.
See “SYSCLK and SYSCLK#” on page 79 for more information.
Preliminary Information
25175H—March 2003 AMD Athlon™ XP Processor Model 8 Data Sheet
CONNECT Pin CONNECT is an input from the system used for power
management and clock-forward initialization at reset.
COREFB and COREFB# Pins
COREFB and COREFB# are outputs to the system that provide
processor core voltage feedback to the system.
CPU_PRESENCE# Pin CPU_PRESENCE# is connected to VSS on the processor
package. If pulled-up on the motherboard, CPU_PRESENCE#
may be used to detect the presence or absence of a processor in
the Socket A-style socket.
DBRDY and DBREQ# Pins
DBRDY and DBREQ# are routed to the debug connector.
DBREQ# is tied to V
CC_CORE
with a pullup resistor.
FERR Pin FERR is an output to the system that is asserted for any
unmasked numerical exception independent of the NE bit in
CR0. FERR is a push-pull active High signal that must be
inverted and level shifted to an active Low signal. For more
information about FERR and FERR#, see the “Required
Circuits” chapter of the AMD Athlon™ Processor-Based
Motherboard Design Guide, order# 24363.
FID[3:0] Pins FID[3] (Y3), FID[2] (Y1), FID[1] (W3), and FID[0] (W1) are the
4-bit processor clock-to-SYSCLK ratio.
Table 26 on page 76 shows the encodings of the clock
multipliers on FID[3:0].
Chapter 11 Pin Descriptions 75
Preliminary Information
AMD Athlon™ XP Processor Model 8 Data Sheet 25175H—March 2003
Table 26. FID[3:0] Clock Multiplier Encodings
FID[3:0]
Notes:
1. All ratios greater than or equal to 12.5x have the same FID[3:0] code of 0011b, which causes
the SIP configuration for all ratios of 12.5x or greater to be the same.
2. BIOS initializes the CLK_Ctl MSR during the POST routine. This CLK_Ctl setting is used with all
FID combinations and selects a Halt disconnect divisor and a Stop Grant disconnect divisor.
For more information, refer to the AMD Athlon™ and AMD Duron™ Processors BIOS,
Software, and Debug Developers Guide, order# 21656.
2
0000 11
0001 11.5
0010 12
0011
0100 5
0101 5 .5
0110 6
0111 6 .5
1000 7
1001 7.5
1010 8
1011 8 .5
1100 9
1101 9 .5
1110 10
1111 10.5
Processor Clock to SYSCLK Frequency Ratio
≥ 12.5
1
The FID[3:0] signals are open-drain processor outputs that are
pulled High on the motherboard and sampled by the chipset to
determine the SIP (Serialization Initialization Packet) that is
sent to the processor. The FID[3:0] signals are valid after
PWROK is asserted. The FID[3:0]signals must not be sampled
until they become valid. See the AMD Athlon™ System Bus
Specification, order# 21902 for more information about
Serialization Initialization Packets and SIP protocol.
The processor FID[3:0] outputs are open-drain and 2.5-V
tolerant. To prevent damage to the processor, if these signals
are pulled High to above 2.5 V, they must be electrically
isolated from the processor. For information about the FID[3:0]
isolation circuit, see the AMD Athlon™ Processor-Based
Motherboard Design Guide, order# 24363.
76 Pin Descriptions Chapter 11
Preliminary Information
25175H—March 2003 AMD Athlon™ XP Processor Model 8 Data Sheet
See “Frequency Identification (FID[3:0])” on page 33 for the
DC characteristics for FID[3:0].
FSB_Sense[1:0] Pins FSB_Sense[1:0] pins are either open circuit (logic level of 1) or
are pulled to ground (logic level of 0) on the processor package
with a 1 kΩ resistor. In conjunction with a circuit on the
motherboard, these pins may be used to automatically detect
the front-side bus (FSB) setting of this processor. Proper
detection of the FSB setting requires the implementation of a
pull-up resistor on the motherboard. Refer to the AMD Athlon™
Processor-Based Motherboard Design Guide, order# 24363 and the
technical note FSB_Sense Auto Detection Circuitry for Desktop
Processors, order# TN26673 for more information.
Table 27 is the truth table to determine the FSB of desktop
processors.
Table 27. Front-Side Bus Sense Truth Table
FSB_Sense[1] FSB_Sense[0] Bus Frequency
1 0 RESERVED
11 133 MHz
01 166 MHz
0 0 RESERVED
The FSB_Sense[1:0] pins are 3.3-V tolerant.
FLUSH# Pin FLUSH# must be tied to V
CC_CORE
with a pullup resistor. If a
debug connector is implemented, FLUSH# is routed to the
debug connector.
IGNNE# Pin IGNNE# is an input from the system that tells the processor to
ignore numeric errors.
INIT# Pin INIT# is an input from the system that resets the integer
registers without affecting the floating-point registers or the
internal caches. Execution starts at 0_FFFF_FFF0h.
INTR Pin INTR is an input from the system that causes the processor to
start an interrupt acknowledge transaction that fetches the
8-bit interrupt vector and starts execution at that location.
JTAG Pins TCK, TMS, TDI, TRST#, and TDO are the JTAG interface.
Connect these pins directly to the motherboard debug
connector. Pull TDI, TCK, TMS, and TRST# up to V
CC_CORE
with
pullup resistors.
Chapter 11 Pin Descriptions 77
Preliminary Information
AMD Athlon™ XP Processor Model 8 Data Sheet 25175H—March 2003
K7CLKOUT and K7CLKOUT# Pins
K7CLKOUT and K7CLKOUT# are each run for two to three
inches and then terminated with a resistor pair: 100 ohms to
V
CC_CORE
resistance and voltage are 50 ohms and V
and 100 ohms to VSS. The effective termination
CC_CORE
/2.
Key Pins These 16 locations are for processor type keying for forwards
and backwards compatibility (G7, G9, G15, G17, G23, G25, N7,
Q7, Y7, AA7, AG7, AG9, AG15, AG17, AG27, and AG29).
Motherboard designers should treat key pins like NC (No
Connect) pins. A socket designer has the option of creating a
top mold piece that allows PGA key pins only where designated.
However, sockets that populate all 16 key pins must be allowed,
so the motherboard must always provide for pins at all key pin
locations.
See “NC Pins” for more information.
NC Pins The motherboard should provide a plated hole for an NC pin.
The pin hole should not be electrically connected to anything.
NMI Pin NMI is an input from the system that causes a non-maskable
interrupt.
PGA Orientation Pins No pin is present at pin locations A1 and AN1. Motherboard
designers should not allow for a PGA socket pin at these
locations.
For more information, see the AMD Athlon™ Processor-Based
Motherboard Design Guide, order# 24363.
PLL Bypass and Test Pins
PLLTEST#, PLLBYPASS#, PLLMON1, PLLMON2,
PLLBYPASSCLK, and PLLBYPASSCLK# are the PLL bypass
and test interface. This interface is tied disabled on the
motherboard. All six pin signals are routed to the debug
connector. All four processor inputs (PLLTEST#, PLLBYPASS#,
PLLMON1, and PLLMON2) are tied to V
CC_CORE
with pullup
resistors.
PWROK Pin The PWROK input to the processor must not be asserted until
all voltage planes in the system are within specification and all
system clocks are running within specification.
For more information, Chapter 9, “Signal and Power-Up
Requirements” on page 45.
78 Pin Descriptions Chapter 11
Preliminary Information
25175H—March 2003 AMD Athlon™ XP Processor Model 8 Data Sheet
SADDIN[1:0]# and SADDOUT[1:0]# Pins
The AMD Athlon XP processor model 8 does not support
SADDIN[1:0]# or SADDOUT[1:0]#. SADDIN[1]# is tied to VCC
with pullup resistors, if this bit is not supported by the
Northbridge (future models can support SADDIN[1]#).
SADDOUT[1:0]# are tied to VCC with pullup resistors if these
pins are supported by the Northbridge. For more information,
see the AMD Athlon™ System Bus Specification, order# 21902.
Scan Pins SCANSHIFTEN, SCANCLK1, SCANINTEVAL, and SCANCLK2
are the scan interface. This interface is AMD internal and is
tied disabled with pulldown resistors to ground on the
motherboard.
SMI# Pin SMI# is an input that causes the processor to enter the system
management mode.
STPCLK# Pin STPCLK# is an input that causes the processor to enter a lower
power mode and issue a Stop Grant special cycle.
SYSCLK and SYSCLK# SYSCLK and SYSCLK# are differential input clock signals
provided to the PLL of the processor from a system-clock
generator.
See “CLKIN, RSTCLK (SYSCLK) Pins” on page 74 for more
information.
THERMDA and THERMDC Pins
Thermal Diode anode and cathode pins are used to monitor the
actual temperature of the processor die, providing more
accurate temperature control to the system.
See Table 17, “Thermal Diode Electrical Characteristics,” on
page 42 for more information.
VCCA Pin VCCA is the processor PLL supply. For information about the
VCCA pin, see Table 5, “VCCA AC and DC Characteristics,” on
page 35 and the AMD Athlon™ Processor-Based Motherboard
Design Guide, order# 24363.
VID[4:0] Pins The VID[4:0] (Voltage Identification) outputs are used to
dictate the V
CC_CORE
voltage level. The VID[4:0] pins are
strapped to ground or left unconnected on the processor
package. The VID[4:0] pins are pulled-up on the motherboard
and used by the V
CC_CORE
DC/DC converter.
The VID codes and corresponding voltage levels are shown in
Table 28.
Chapter 11 Pin Descriptions 79
Preliminary Information
AMD Athlon™ XP Processor Model 8 Data Sheet 25175H—March 2003
Table 28. VID[4:0] Code to Voltage Definition
VID[4:0]
00000 1.850 10000 1.450
00001 1.825 10001 1.425
00010 1. 80 0 10010 1.40 0
00011 1.775 10011 1. 375
00100 1.750 1010 0 1.350
00101 1. 725 10101 1. 325
00111 1. 675 10111 1. 275
01000 1. 65 0 110 00 1.250
01001 1.625 11001 1.225
01010 1. 600 11010 1. 200
01011 1. 575 11011 1.175
01100 1.55 0 11100 1.150
01101 1. 525 11101 1.125
01110 1. 500 11110 1.100
01111 1.475 11111 No C PU
V
CC_CORE
(V)
VID[4:0]
V
CC_CORE
(V)
For more information, see the “Required Circuits” chapter of
the AMD Athlon™ Processor-Based Motherboard Design Guide,
order# 24363.
VREFSYS Pin VREFSYS (W5) drives the threshold voltage for the system bus
input receivers. The value of VREFSYS is system specific. In
addition, to minimize V
CC_CORE
noise rejection from VREFSYS,
include decoupling capacitors. For more information, see the
AMD Athlon™ Processor-Based Motherboard Design Guide, order#
24363.
ZN and ZP Pins ZN (AC5) and ZP (AE5) are the push-pull compensation circuit
pins. In Push-Pull mode (selected by the SIP parameter
SysPushPull asserted), ZN is tied to V
CC_CORE
that has a resistance matching the impedance Z
with a resistor
of the
0
transmission line. ZP is tied to VSS with a resistor that has a
resistance matching the impedance Z0 of the transmission line.
80 Pin Descriptions Chapter 11
Preliminary Information
25175H—March 2003 AMD Athlon™ XP Processor Model 8 Data Sheet
12 Ordering Information
This section provides the ordering information for the
AMD Athlon™ XP processor model 8.
Standard AMD Athlon™ XP Processor Model 8 Products
AMD standard products are available in several operating
ranges. The ordering part numbers (OPN) are formed by a
combination of the elements, as shown in Figure 18.
1
OPN
AXD A D2700
D K V 3
Advanced Front-Side Bus (FSB): C = 266, D = 333
Size of L2 Cache: 3 = 256 Kbytes
Die Temperature: T = 90°C, V = 85°C
Operating Voltage: L = 1.50 V, U = 1.60 V, K = 1.65 V
Package Type: D = OPGA
Model Number: 1600 operates at 1400 MHz
1700 at 1467 MHz
1800 at 1533 MHz
1900 at 1600 MHz
2000
at 1667 MHz
2100 at 1733 MHz
2200 at 1800 MHz
2400 at 2000 MHz
2600 at 2083 MHz
2700 at 2167 MHz
2
,
2
,
2
,
2
,
2
,
2
,
2
,
3
or 2133 MHz2,
3
2
,
Maximum Power: A = Desktop Processor
Architecture Segment: AXD = AMD Athlon™ XP Processor Model 8 with
QuantiSpeed™ Architecture for Desktop Products
Notes:
1. Spaces are added to the number shown above for viewing clarity only.
2. This processor is available only with a 266 advanced FSB.
3. This processor is available only with a 333 advanced FSB.
Figure 18. OPN Example for the AMD Athlon™ XP Processor Model 8
Chapter 12 Ordering Information 81
Preliminary Information
AMD Athlon™ XP Processor Model 8 Data Sheet 25175H—March 2003
82 Ordering Information Chapter 12
Preliminary Information
Preliminary Information
25175H—March 2003 AMD Athlon™ XP Processor Model 8 Data Sheet
Appendix A
Thermal Diode Calculations
This section contains information about the calculations for the
on-die thermal diode of the AMD Athlon™ XP processor model
8. For electrical information about this thermal diode, see
Table 17, “Thermal Diode Electrical Characteristics,” on
page 42.
Ideal Diode Equation
The ideal diode equation uses the variables and constants
defined in Table 29.
Table 29. Constants and Variables for the Ideal Diode Equation
Equation Symbol Variable, Constant Description
n
f, lumped
k Boltzmann constant
q Electron charge constant
T Diode temperature (Kelvin)
V
BE
I
C
I
S
Lumped ideality factor
Voltage from base to emitter
Collector current
Saturation current
Appendix A - Thermal Diode Calculations 83
Preliminary Information
AMD Athlon™ XP Processor Model 8 Data Sheet 25175H—March 2003
Equation (1) shows the ideal diode calculation.
BE
n
flumped,
V
Sourcing two currents and using Equation (1) derives the
difference in the base-to-emitter voltage that leads to finding
the diode temperature as shown in Equation (2). The use of
dual sourcing currents allows the measurement of the thermal
diode temperature to be more accurate and less susceptible to
die and process revisions. Temperature sensors that utilize
series resistance cancellation can use more than two sourcing
currents and are suitable to be used with the AMD thermal
diode. Equation (2) is the formula for calculating the
temperature of a thermal diode.
V
BE high,
-------------------------------------------------------------- -
T
=
n
f lumped,
Temperature Offset Correction
A temperature offset may be required to correct the value
measured by a temperature sensor. An offset is necessary if a
difference exists between the lumped ideality factor of the
processor and the ideality factor assumed by the temperature
sensor. The lumped ideality factor can be calculated using the
equations in this section to find the temperature offset that
should be used with the temperature sensor.
k
-- -
q
–
k
-- -
q
T
ln⋅⋅⋅=
V
BE low,
I
------- -
ln⋅⋅
I
I
--- -
I
high
low
C
S
(1)
(2)
Table 30 shows the constants and variables used to calculate the
temperature offset correction.
Table 30. Constants and Variables Used in Temperature Offset Equations
Equation Symbol Variable, Constant Description
n
f, actual
n
f, lumped
n
f, TS
I
high
I
low
T
die, spec
T
offset
Actual ideality factor
Lumped ideality factor
Ideality factor assumed by temperature sensor
High sourcing current
Low sourcing current
Die temperature specification
Temperature offset
84 Appendix A - Thermal Diode Calculations
Preliminary Information
25175H—March 2003 AMD Athlon™ XP Processor Model 8 Data Sheet
The formulas in Equation (3) and Equation (4) can be used to
calculate the temperature offset for temperature sensors that
do not employ series resistance cancellation. The result is
added to the value measured by the temperature sensor.
Contact the vendor of the temperature sensor being used for
the value of n
. Refer to the document, On-Die Thermal Diode
f,TS
Characterization, order# 25443, for further details.
Equation (3) shows the equation for calculating the lumped
ideality factor (n
f, lumped
) in sensors that do not employ series
resistance cancellation.
n
f lumped,
n
=
factual,
----------------------------------------------------------------------+
k
-- -
q
RTI
T
die spec,
–()⋅
highIlow
I
high
273.15+()
------- -
ln⋅
I
low
(3)
Equation (4) shows the equation for calculating temperature
offset (T
) in sensors that do not employ series resistance
offset
cancellation.
n
T
offset
T
die spec,
273.15+()= 1
⋅
flumped,
---------------–
n
fTS,
(4)
Equation (5) is the temperature offset for temperature sensors
that utilize series resistance cancellation. Add the result to the
value measured by the temperature sensor. Note that the value
of n
in Equation (5) may not equal the value used in
f,TS
Equation (4).
n
T
offset
T
die spec,
273.15+()= 1
⋅
f actual,
---------------–
n
fTS,
(5)
Appendix A - Thermal Diode Calculations 85
Preliminary Information
AMD Athlon™ XP Processor Model 8 Data Sheet 25175H—March 2003
86 Appendix A - Thermal Diode Calculations
Preliminary Information
25175H—March 2003 AMD Athlon™ XP Processor Model 8 Data Sheet
Appendix B
Conventions and Abbreviations
Signals and Bits
This section contains information about the conventions and
abbreviations used in this document.
■ Active-Low Signals—Signal names containing a pound sign,
such as SFILL#, indicate active-Low signals. They are
asserted in their Low-voltage state and negated in their
High-voltage state. When used in this context, High and Low
are written with an initial upper case letter.
■ Signal Ranges—In a range of signals, the highest and lowest
signal numbers are contained in brackets and separated by a
colon (for example, D[63:0]).
■ Reserved Bits and Signals— Signals or bus bits marked
reserved must be driven inactive or left unconnected, as
indicated in the signal descriptions. These bits and signals
are reserved by AMD for future implementations. When
software reads registers with reserved bits, the reserved bits
must be masked. When software writes such registers, it
must first read the register and change only the
non-reserved bits before writing back to the register.
■ Three-State—In timing diagrams, signal ranges that are
high impedance are shown as a straight horizontal line
half-way between the high and low levels.
Appendix B - Conventions and Abbreviations 87
Preliminary Information
AMD Athlon™ XP Processor Model 8 Data Sheet 25175H—March 2003
■ Invalid and Don’t-Care— In timing diagrams, signal ranges
that are invalid or don't-care are filled with a screen pattern.
Data Terminology
The following list defines data terminology:
■ Quantities
• A word is two bytes (16 bits)
• A doubleword is four bytes (32 bits)
• A quadword is eight bytes (64 bits)
■ Addressing—Memory is addressed as a series of bytes on
eight-byte (64-bit) boundaries in which each byte can be
separately enabled.
■ Abbreviations—The following notation is used for bits and
bytes:
• Kilo (K, as in 4-Kbyte page)
• Mega (M, as in 4 Mbits/sec)
• Giga (G, as in 4 Gbytes of memory space)
See Table 31 on page 89 for more abbreviations.
■ Little-Endian Convention —The byte with the address
xx...xx00 is in the least-significant byte position (little end).
In byte diagrams, bit positions are numbered from right to
left—the little end is on the right and the big end is on the
left. Data structure diagrams in memory show low addresses
at the bottom and high addresses at the top. When data
items are aligned, bit notation on a 64-bit data bus maps
directly to bit notation in 64-bit-wide memory. Because byte
addresses increase from right to left, strings appear in
reverse order when illustrated.
■ Bit Ranges—In text, bit ranges are shown with a dash (for
example, bits 9–1). When accompanied by a signal or bus
name, the highest and lowest bit numbers are contained in
brackets and separated by a colon (for example, AD[31:0]).
■ Bit Values— Bits can either be set to 1 or cleared to 0.
■ Hexadecimal and Binary Numbers—Unless the context
makes interpretation clear, hexadecimal numbers are
followed by an h and binary numbers are followed by a b.
88 Appendix B - Conventions and Abbreviations
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