AMD Advanced Micro Devices AMC020DFLKACS, AMC008DFLKACS, AMC004DFLKACS, AMC032DFLKACS Datasheet
FINAL
Publication# 19521 Rev: D Amendment/0
Issue Date: December 1996
AmC0XXDFLKA
4, 8, 20, or 32 Megabyte 5.0 Volt-only Flash Memory PC Card
DISTINCTIVE CHARACTERISTICS
■
High performance
— 150 ns maximum access time
■
Single supply operation
— Write and erase voltage, 5.0 V ± 5%
— Read voltage, 5.0 V ± 5%
■
CMOS low power consumption
— 45 mA maximum active read current (x8 mode)
— 65 mA maximum active write/erase current
(x8 mode)
■
High write endurance
— Minimum 100,000 program/erase cycles per
sector
— 1,000,000 typical program/erase cycles per card
■
PCMCIA/JEIDA 68-pin standard
— Selectable byte-/or word-wide configuration
■
Write protect switch
— Prevents accidental data loss
■
Zero data retention power
— Batteries not required for data storage
■
Enhanced power management for standby
mode
—1 µ A typical standby current
— Standard access time from standby mode
■
Separate attribute memory
■
Automated write and erase operations increase
system write performance
— 64K byte memory sectors for faster automated
erase speed
— Typically 1 s per single memory sector erase
— Random address writes to previously erased
bytes (8 µ s typical per byte)
■
Total system integration solution
— Support from independent software and
hardware vendors
■
Low insertion and removal force
— State-of-the-art connector allows for minimum
card insertion and removal effort
■
Erase Suspend/Resume
— Supports reading or programming data to a
sector not being erased within the same device
■
Support for RY/BY
and RESET signals
GENERAL DESCRIPTION
AMD’s 5.0 Volt-only Flash Memory PC Card provides
the highest system level performance for data and file
storage solutions to the portable PC market segment
and a wide range of embedded applications. Manufactured with AMD’s Negative Gate Erase, 5.0 Volt-only
technology, the AMD 5.0 Volt-only Flash Memory
Cards are the most cost-effective and reliable approach to single-supply Flash memory cards. Data files
and application programs can be stored on the D-Series cards. This allows OEM manufacturers of portable
systems to eliminate the weight, high-power consumption and reliability issues associated with
electro-mechanical disk-based systems. The D-Series
cards also allow today’ s b ulky and hea vy battery packs
to be reduced in weight and size. AMD’ s Flash Memory
PC Cards provide the most efficient method to transfer
useful work between different hardware platforms. The
enabling technology of the D-Series cards enhances
the productivity of mobile workers.
Widespread acceptance of the D-Series cards
is assured due to their compatibility with the
68-pin PCMCIA/JEIDA international standard. AMD’s
Flash Memory Cards can be read in either a byte-wide
or word-wide mode which allows for flexible integration
into various system platforms. Compatibility is assured
at the hardware interface and software interchange
specification. The Card Information Structure (CIS) or
Metaformat, can be written by the OEM into the memory card’s attribute memory address space beginning
at address 00000H by using a format utility. The CIS
appears at the beginning of the Card’s attribute memory space and defines the low-level organization of
data on the PC Card. The D-Series cards contains a
separate EEPROM memory for the cards’ attribute
memory space. This allows all of the Flash memory to
be used for the common memory space.
Third party software solutions such as Microsoft’s and
SystemSoft’s Flash File System (FFS2), SCM’s
SCM-FTL, and Datalight’s Cardtrick enable AMD’s
Flash Memory PC Card to replicate the function
of traditional disk-based memory systems.
2 AmC0XXDFLKA
BLOCK DIAGRAM
Notes:
R = 20 K(min)/140 K
Ω
(max)
*4 Mbyte card = S0 + S1, 8 Mbyte card = S0…S3, 20 Mbyte card = S0…S9, 32 Mbyte card = S0…S15
Address
Buffers
and
Decoders
I/O
Transceivers
and
Buffers
A0–A8 D0–D7
Attribute Memory
CE
Write Protect Switch
V
CC
D0–D15
WE
OE
D8–D15
D0–D7
A0
A1–A24
CE
2
CE
1
A1–A9
A0
CE
2
CE1
REG
CD1
CD
2
Card Detect
GND
V
CC
R
R
Decoder
V
CC
RR
Am29F016C
A0–A20 D0–D7
CE
WE
OE RY/BY
V
SS VCC
RST
S0*
Am29F016C
A0–A20 D8–D15
CE
WE
OE RY/BY
V
SS VCC
RST
S1*
A0–A20 D0–D7
CE
WE
OE RY/BY
V
SS VCC
RST
S2*
A0–A20 D8–D15
CE
WE
OE RY/BY
V
SS VCC
RST
S3*
A0–A20 D0–D7
CE
WE
OE RY/BY
V
SS VCC
RST
S14*
A0–A20 D8–D15
CE
WE
OE RY/BY
V
SS VCC
RST
S15*
19521D-1
WP
10K
10K
A0–A24
ICE7
ICE0
ICE1
IOEL
IWEL
IOEH
IWEH
A1-A21
V
CC
RESET
RY/BY
(Output)
R
V
CC
3.3K
AmC0XXDFLKA 3
PC CARD PIN ASSIGNMENTS
Notes:
I = Input to card, O = Output from card
I/O = Bidirectional
NC = No connect
In systems which switch V
CC
individually to cards, no signal should be directly connected between cards other than ground.
1. V
PP
not required for Programming or Reading operations.
2. BVD
= Internally pulled-up.
3. Signal must not be connected between cards.
Pin# Signal I/O Function Pin# Signal I/O Function
1 GND Ground 35 GND Ground
2 D3 I/O Data Bit 3 36 CD1 O Card Detect 1 (Note 3)
3 D4 I/O Data Bit 4 37 D11 I/O Data Bit 11
4 D5 I/O Data Bit 5 38 D12 I/O Data Bit 12
5 D6 I/O Data Bit 6 39 D13 I/O Data Bit 13
6 D7 I/O Data Bit 7 40 D14 I/O Data Bit 14
7CE
1 I Card Enable 1 (Note 3) 41 D15 I/O Data Bit 15
8 A10 I Address Bit 10 42 CE
2 I Card Enable 2 (Note 3)
9OE
I Output Enable 43 NC No Connect
10 A11 I Address Bit 11 44 NC No Connect
11 A9 I Address Bit 9 45 NC No Connect
12 A8 I Address Bit 8 46 A17 I Address Bit 17
13 A13 I Address Bit 13 47 A18 I Address Bit 18
14 A14 I Address Bit 14 48 A19 I Address Bit 19
15 WE
I Write Enable 49 A20 I Address Bit 20
16 RY/BY
Ready/Busy 50 A21 I Address Bit 21
17 V
CC1
Power Supply 51 V
CC2
Power Supply
18 NC No Connect (Note 1) 52 NC No Connect (Note 1)
19 A16 I Address Bit 16 53 A22 I Address Bit 22
20 A15 I Address Bit 15 54 A23 I Address Bit 23
21 A12 I Address Bit 12 55 A24 I Address Bit 24
22 A7 I Address Bit 7 56 NC No Connect
23 A6 I Address Bit 6 57 NC No Connect
24 A5 I Address Bit 5 58 RESET RESET
25 A4 I Address Bit 4 59 NC No Connect
26 A3 I Address Bit 3 60 NC No Connect
27 A2 I Address Bit 2 61 REG
I Register Select
28 A1 I Address Bit 1 62 BVD
2 O Battery Vltg Detect 2 (Note 2)
29 A0 I Address Bit 0 63 BVD
1 O Battery Vltg Detect 1 (Note 2)
30 D0 I/O Data Bit 0 64 D8 I/O Data Bit 8
31 D1 I/O Data Bit 1 65 D9 I/O Data Bit 9
32 D2 I/O Data Bit 2 66 D10 I/O Data Bit 10
33 WP O Write Protect (Note 3) 67 CD
2 O Card Detect 2 (Note 3)
34 GND Ground 68 GND Ground
4 AmC0XXDFLKA
ORDERING INFORMATION
Standard Products
AMD standard products are available in se ver al packages and operating r anges. The order number (Valid Combination) is formed
by a combination of:
OUTPUT CONFIGURATION:
(x16/x8)
FLASH TECHNOLOGY
PC MEMORY CARD
MEMORY CARD DENSITY
004 = Four Megabytes
008 = Eight Megabytes
020 = Twenty Megabytes
032 = Thirty-two Megabytes
AMD
REVISION LEVEL
5.0 V olt-only OPERATION
WITH 100,000 ERASE/PROGRAM
CYCLES MINIMUM
AM C 0XX D FL
K
A
CSxxxxx
CUSTOMER SPECIFIC
IDENTIFICATION NUMBER
AmC0XXDFLKA 5
Differences Between the D-Series and
C-Series Cards
The differences between the D-Series Card and the
earlier C-Series Cards are as follows:
■
The D-Series Cards are based on AMD’s latest 16
MBit 5.0 Volt-only device, the Am29F016C . The earlier C-Series Cards were based on the 4 MBit 5.0
Volt-only device, the Am29F040.
■
The D-Series Cards program faster than the CSeries Cards. This is due to faster byte write times
and an optimized address unlock sequence for
write operations.
■
The D-Series Cards are offered in higher densities. The D-Series Cards are available in densities
of 4 MBytes, 8 MBytes, 20 MBytes, and 32
MBytes. The earlier C-Series Cards were available in densities of 1 MByte, 2 MBytes, 4 MBytes
and 10 MBytes.
The additional features that are supported in the new
D-Series Cards include
■
The D-Series Cards support the RESET feature.
This allows you to asynchronously RESET the Card
into the read state.
■
The D-Series Cards also provide the RY/BY
functionality. This feature provides a quick way of determining if the Card is busy doing a write or erase
operation, or if it is in a position to undertake the
next operation.
■
Availability of an additional Toggle bit (D2) to determine if the Card is in the Embedded Erase or Erase
Suspend mode.
■
Programming operations can be executed in 8 µ s
pulses, down from the 16 µ s on the C-Series
Cards (typical).
■
Time out from the rising edge of the WE
pulse for
sector erase command reduced from 100 µ s to
50 µ s.
■
The D-Series Cards offers a low power standby
mode with fast recovery time to read. The typical
standby current (I
CCS
) is <1 µ A with recovery at
standard read access time.
6 AmC0XXDFLKA
PIN DESCRIPTION
A0–A24
Address Inputs
These inputs are internally latched during write cycles.
All address lines should be driven.
BVD1, BVD2
Battery V oltage Detect
Internally pulled-up.
CD1, CD2
Card Detect
When card detect 1 and 2 = ground the system detects
the card.
CE1, CE2
Card Enable
This input is active low . The memory card is deselected
and power consumption is reduced to standby levels
when CE
is high. CE activates the internal memor y
card circuitry that controls the high and low byte control
logic of the card, input buffers segment decoders, and
associated memory devices.
D0–D15
Data Input/Output
Data inputs are internally latched on write cycles. Data
outputs during read cycles. Data pins are active high.
When the memory card is deselected or the outputs
are disabled the outputs float to tristate.
GND
Ground
NC
No Connect
Corresponding pin is not connected.
OE
Output Enable
This input is active low and enables the data buffers
through the card outputs during read cycles.
RY/BY
This signal is output from the card and indicates the
status of the operation in progress in the card. If this
signal is low, then the card is still busy with the current
operation. Otherwise, the card is ready to accept anew
operation.
REG
Attribute Memory Select
This input is active low and enables reading the CIS
from the EEPROM.
RESET
This input to the Card is used to reset all the Flash devices inside the Card to a read mode state. If you drive
or assert RESET high during a write or erase operation, then the state of the devices for the purpose of the
operation is undefined. In order to RESET, you need to
hold the RESET pin high for 500 ns, and it takes 20 µ s
before the internal circuit is RESET. When RESET is
driven high, the data bus is in a high impedance state.
V
CC
PC Card Power Supply
For device operation (5.0 V ± 5%).
WE
Write Enable
This input is active low and controls the write function
of the command register to the memory array. The
target address is latched on the falling edge of the WE
pulse and the appropriate data is latched on the rising
edge of the pulse.
WP
Write Protect
This output is active high and disables all Card write
operations (including writes to the attribute memory).
MEMORY CARD OPERATIONS
The D-Series Flash Memory Card is organized as an
array of individual devices. Each device is 2 Mbytes in
size with thirty-two 64K byte sectors. Although the address space is continuous, each physical device defines a logical address segment size.
Erase operations can be performed on two 64KByte
sectors simultaneously. Once a memory sector or
memory segment is erased any address location may
be programmed. Flash technology allows any logical
“1” data bit to be programmed to a logical “0”. The
only way to reset bits to a logical “1” is to erase the
entire memory sector of 64K bytes or memory segment of 2 Mbytes.
Erase operations are the only operations that work on
entire memory sectors or memory segments. All other
operations such as word-wide programming are not affected by the physical memory segments.
The common memory space data contents are altered
in a similar manner as writing to individual Flash memory devices. On-card address and data buffers activate
the appropriate Flash device in the memory array.
Each device internally latches address and data during
write cycles. Refer to Table 1.
Attribute memory is a separately accessed card memory space. The attribute memory space is active when
the REG
pin is driven low. The Card Information Struc-
ture (CIS) describes the capabilities and specification
AmC0XXDFLKA 7
of a card. The CIS is stored in the attribute memory
space beginning at address 00000H. The D-Series
cards contain a separate EEPROM for the Card Information Structure. D0–D7 are active during attribute
memory accesses. D8–D15 should be ignored. Odd order bytes present invalid data. Refer to Table 2.
Word-Wide Operations
The D-Series cards provide the flexibility to operate on
data in a byte-wide or word-wide format. In word-wide
operations the CE
1 and CE2 must be low and A0 is not
used for any addressing.
Table 1. Common Memory Bus Operations
Notes:
1. X indicates a don’t care value.
2. V
PP
pins are not connected in the 5.0 Volt-only Flash Memory Card.
3. Refer to Table 5 for valid D
IN
during a word write operation.
4. Refer to Table 3 and 4 for valid D
IN
during a byte write operation.
5. During odd byte access, A0 = V
IH
outputs or inputs the “odd” b yte (high byte) of the x16 word on D0–D7. This is accomplished
internal to the card by transposing D8–D15 to D0–D7.
6. During odd-byte-only access , A0 = X outputs or inputs the “odd” byte (high byte) of the x16 word on D8–D15.
Function REG CE2CE1OEWE A0 D8–D15 D0–D7
Read Mode
Standby Mode X H H X X X High-Z High-Z
Word Access H L L L H X Data Out-Odd Data Out-Even
Low Byte Access H H L L H L High-Z Data Out-Even
Odd Byte Access H H L L H H High-Z Data Out-Odd
Odd-Byte-Only Access HLHLHXData Out-Odd High-Z
Write Mode
Standby Mode X H H X X X X X
Word Access (Note 3)
H
L L H L X Data In-Odd Data In-Even
Even Byte Access (Note 4) H HLHLL High-Z Data In-Even
Odd Byte Access (Note 4) H HLHLH High-Z Data In-Odd
Odd-Byte-Only Access (Note 4) H L H H L X Data In-Odd High-Z
Output Disable H X X H H X High-Z High-Z
8 AmC0XXDFLKA
Table 2. Attribute Memory Bus Operations
Notes:
1. X indicates any value.
2. V
PP
pins are not connected in the 5.0 Volt-Only Flash Memory Card.
3. During Attribute Memory Read function, REG
and OE must be active for the entire cycle.
4. Only even-byte data is valid during Attribute Memory Read function.
5. During Attribute Memory Write function, REG
and WE must be active for the entire cycle, OE must be inactive for the
entire cycle.
6. The first 128 bytes of the attribute memory is not writable as it contains the CIS. Only the remaining 384 bytes are writable.
Pins/Operation REG CE2CE1OEWE A0 D8–D15 D0–D7
READ/WRITE
Read Mode (Note 3)
Standby Mode X H H X X X High-Z High-Z
Word Access (Note 4) LLLLHX Not Valid Data Out-Even
Even Byte Access L H L L H L High-Z Data Out-Even
Odd Byte Access (Note 4) L H L L H H High-Z Not Valid
Odd-Byte-Only Access (Note 4) L LHLHX Not Valid High-Z
Write Mode (Note 5,6)
Standby Mode X H H X X X X X
Word Access L L L H L X X Data In-Even
Low Byte Access LHLHLL X Data In-Even
Odd Byte Access LHLHLH X X
Odd-Byte-Only Access L L H X H L X X
Output Disable L X X H H X High-Z High-Z
AmC0XXDFLKA 9
Byte-Wide Operations
Byte-wide data is available on D0–D7 f or read and write
operations (CE1 = low, CE2 = high). Even and odd
bytes are stored in separate memory segments (i.e.,
S0 and S1) and are accessed when A0 is low and high
respectively. The even byte is the low order byte and
the odd byte is the high order byte of a 16-bit word.
Erase operations in the byte-wide mode must account
for data multiplexing on D0–D7 b y changing the state of
A0. Each memory sector or memor y segment pair
must be addressed separately for erase operations.
Card Detection
Each CD (output) pin should be read by the host system to determine if the memory card is adequately
seated in the socket. CD1 and CD2 are internally tied
to ground. If both bits are not detected, the system
should indicate that the card must be reinserted.
Write Protection
The AMD Flash memory card has three types of write
protection. The PCMCIA/JEIDA socket itself provides
the first type of write protection. P o wer supply and control pins have specific pin lengths in order to protect the
card with proper power supply sequencing in the case
of hot insertion and removal.
A mechanical write protect switch provides a second
type of write protection. When this switch is activated,
WE is internally forced high. The Flash memory command register is disabled from accepting any write
commands.
The third type of write protection is achieved with V
CC1
and V
CC2
below 3.2 V V
LKO
. Each Flash memory device that comprises a Flash memory segment will
reset the command register to the read-only mode
when VCC is below V
LKO
. V
LKO
is the voltage below
which write operations to individual command registers are disabled.
MEMORY CARD BUS OPERATIONS
Read Enable
Two Card Enable (CE) pins are available on the memory card. Both CE pins must be active low for
word-wide read accesses. Only one CE is required for
byte-wide accesses. The CE pins control the selection
and gates power to the high and low memory segments. The Output Enable (OE) controls gating accessed data from the memory segment outputs.
The device will automatically power-up in the read/
reset state. In this case, a command sequence is not
required to read data. Standard microprocessor read
cycles will retrieve array data. This default value ensures that no spurious alteration of the memory content
occurs during the power transition. Refer to the AC
Read Characteristics and Waveforms for the specific
timing parameters.
Output Disable
Data outputs from the card are disabled when OE is at
a logic-high level. Under this condition, outputs are in
the high-impedance state.
Standby Operations
Byte-wide read accesses only require half of the read/
write output buffer (x16) to be active. In addition, only
one memory segment is active within either the high
order or low order bank. Activation of the appropriate
half of the output buffer is controlled by the combination
of both CE
pins. The CE pins also control power to the
high and low-order banks of memory. Outputs of the
memory bank not selected are placed in the high impedance state. The individual memory segment is activated by the address decoders. The other memory
segments operate in standby. An active memory segment continues to draw power until completion of a
write or erase operation if the card is deselected in the
process of one of these operations.
Auto Select Operation
A host system or external card reader/writer can determine the on-card manufacturer and device I.D. codes.
Codes are available after writing the 90H command to
the command register of a memory segment per
Tables 3 and 4. Reading from address location 00000H
in any segment provides the manufacturer I.D. while
address location 00002H provides the device I.D.
To terminate the Auto Select operation, it is necessary to write the Read/Reset command sequence
into the register.
Write Operations
Write and erase operations are valid only when V
CC1
and V
CC2
are above 4.75 V. This activ ates the state machine of an addressed memory segment. The command register is a latch which saves address,
commands, and data information used by the state machine and memory array.
When Write Enable (WE) and appropriate CE(s) are at
a logic-level low, and Output Enable (OE) is at a
logic-high, the command register is enabled for write
operations. The falling edge of WE latches address information and the rising edge latches data/command
information.
Write or erase operations are performed by writing appropriate data patterns to the command register of accessed Flash memory sectors or memory segments.
The byte-wide and word-wide commands are defined
in Tables 3, 4, and 5, respectively.
10 AmC0XXDFLKA
Table 3. Even Byte Command Definitions (Note 5)
* Address for Memory Segment 0 (S0) only. Address f or the higher ev en memory segments (S2–S14) = (Addr) + (N/2)* 400000H
where N = Memory Segment number (0) for 4 Mbyte, N = (0, 2) for 8 Mb yte, N = (0, 2, 4) f or 12 Mbyte , N = (0…8) f or 20 Mbyte,
N = (0...14) for 32 Mbyte.
Notes:
1. Address bits = X = Don’t Care for all address commands except for Program Address (PA), Read Address (RA) and Sector
Address (SA).
2. Bus operations are defined in Table 1.
3. RA = Address of the memory location to be read.
PA = Address of the memory location to be programmed. Addresses are latched on the falling edge of the WE
pulse.
SA = Address of the sector to be erased. The combination of A17, A18, A19, A20, A21 will uniquely select any sector of a
segment.
To select the memory segment: 4 Mbyte: Use CE
1
8 Mbyte: Use CE
1 and A22
20 and 32 Mbyte: Use CE
1 and A22-A24.
4. RD = Data read from location RA during read operation.
PD = Data to be programmed at location PA. Data is latched on the rising edge of WE
pulse.
5. A0 = 0 and CE
1 = 0.
Embedded
Command
Sequence
Bus
Write
Cycles
Req’d
First Bus
Write Cycle
Second Bus
Write Cycle
Third Bus
Write Cycle
Fourth Bus
Read/Write Cycle
Fifth Bus
Write Cycle
Sixth Bus
Write Cycle
Addr* Data Addr* Data Addr* Data Addr* Data Addr* Data Addr* Data
Reset/Read 1 XXXXH F0
Reset/Read 4 XXXXH AA XXXXH 55 XXXXH F0 RA RD
Autoselect 4 XXXXH AA XXXXH 55 XXXXH 90
00H 01
02H 3D
Byte Write 4 XXXXH AA XXXXH 55 XXXXH A0 P A PD
Segment Erase 6 XXXXH AA XXXXH 55 XXXXH 80 XXXXH AA XXXXH 55 XXXXH 10
Sector Erase 6 XXXXH AA XXXXH 55 XXXXH 80 XXXXH AA XXXXH 55 SA 30
Sector Erase Suspend XXXXH B0 Erase can be suspended during sector erase with Addr (don’t care), Data (B0H)
Sector Erase Resume XXXXH 30 Erase can be resumed after suspend with Addr (don’t care), Data (30H)
AmC0XXDFLKA 11
Table 4. Odd Byte Command Definitions (Notes 1–5)
* Address for Memory Segment 1 (S1) only. Address for the higher odd memory segments (S3–S15) = (Addr) + ((N–1)/2)*
400000H + 20000H where N = Memory Segment number (1) for 4 Mbyte, N = (1, 3) for 8 Mbyte , N = (1, 3, 5) f or 12 Mb yte,
N = (1…9) for 20 Mbyte, N = (1...15) for 32 Mbyte.
Notes:
1. Address bits = X = Don’t Care for all address commands except for Program Address (PA), Read Address (RA) and Sector
Address (SA).
2. Bus operations are defined in Table 1.
3. RA = Address of the memory location to be read.
PA = Address of the memory location to be programmed. Addresses are latched on the falling edge of the WE
pulse.
SA = Address of the sector to be erased. The combination of A17, A18, A19, A20, A21 will uniquely select any sector of a
segment.
To select the memory segment: 4 Mbyte: Use CE
2
8 Mbyte: Use CE
2 and A22
20 and 32 Mbyte: Use CE
2 and A22–A24.
4. RD = Data read from location RA during read operation.
PD = Data to be programmed at location PA. Data is latched on the rising edge of WE
pulse.
5. A0 = 1 and CE
1 = 0 or A0 = X and CE2 = 0.
Embedded
Command
Sequence
Bus
Write
Cycles
Req’d
First Bus
Write Cycle
Second Bus
Write Cycle
Third Bus
Write Cycle
Fourth Bus
Read/Write Cycle
Fifth Bus
Write Cycle
Sixth Bus
Write Cycle
Addr* Data Addr* Data Addr* Data Addr* Data Addr* Data Addr* Data
Reset/Read 1 XXXXH F0
Reset/Read 4 XXXXH AA XXXXH 55 XXXXH F0 RA RD
Autoselect 4 XXXXH AA XXXXH 55 XXXXH 90
00H 01
02H 3D
Byte Write 4 XXXXH AA XXXXH 55 XXXXH A0 P A PD
Segment Erase 6 XXXXH AA XXXXH 55 XXXXH 80 XXXXH AA XXXXH 55 XXXXH 10
Sector Erase 6 XXXXH AA XXXXH 55 XXXXH 80 XXXXH AA XXXXH 55 SA 30
Sector Erase Suspend XXXXH AA Erase can be suspended during sector erase with Addr (don’t care), Data (B0H)
Sector Erase Resume XXXXH AA Erase can be resumed after suspend with Addr (don’t care), Data (30H)
12 AmC0XXDFLKA
Table 5. Word Command Definitions (Notes 1–7)
Notes:
1. Address bits = X = Don’t Care for all address commands except for Program Address (PA) and Sector Address (SA).
2. Bus operations are defined in Table 1.
3. RA = Address of the memory location to be read.
PA = Address of the memory location to be programmed. Addresses are latched on the falling edge of the WE
pulse.
SA = Address of the sector to be erased. The combination of A17, A18, A19, A20, A21will uniquely select any sector of a
segment.
To select the memory segment: 4 Mbyte: Use CE
1, CE2
8 Mbyte: Use CE
1, CE2
20 and 32 Mbyte: Use CE
1, CE2, A22–A24.
4. RW = Data read from location RA during read operation. (Word Mode).
PW = Data to be programmed at location PA. Data is latched on the rising edge of WE
. (Word Mode).
5. Address for Memory Segment Pair 0 (S0 and S1) only. Address for the higher Memory Segment Pairs (S2, S3 = Pair 1; S4,
S5 = Pair 2; S6, S7 = Pair 3…) is equal to (Addr) + M* (40000H) where M = Memory Segment Pair number.
6. Word = 2 bytes = odd byte and even byte.
7. CE
1 = 0 and CE2 = 0.
Embedded
Command
Sequence
Bus
Write
Cycles
Req’d
First Bus
Write Cycle
Second Bus
Write Cycle
Third Bus
Write Cycle
Fourth Bus
Read/Write Cycle
Fifth Bus
Write Cycle
Sixth Bus
Write Cycle
Addr* Data Addr* Data Addr* Data Addr* Data Addr* Data Addr* Data
Reset/Read 1 XXXXH F0F0
Reset/Read 4 XXXXH AAAA XXXXH 5555 XXXXH F0 RA RW
Autoselect 4 XXXXH AAAA XXXXH 5555 XXXXH 90
00H 0101
02H 3D3D
Byte Write 4 XXXXH AAAA XXXXH 5555 XXXXH A0A0 PA PW
Segment
Erase
6 XXXXH AAAA XXXXH 5555 XXXXH 8080 XXXXH AAAA 5554H 5555 XXXXH 1010
Sector Erase 6 XXXXH AAAA XXXXH 5555 XXXXH 8080 XXXXH AAAA 5554H 5555 SA 3030
Sector Erase Suspend XXXXH B0B0 Erase can be suspended during sector erase with Addr (don’t care), Data (B0B0H)
Sector Erase Resume XXXXH 3030 Erase can be resumed after suspend with Addr (don’t care), Data (3030H)
AmC0XXDFLKA 13
FLASH MEMORY PROGRAM/ERASE
OPERATIONS
Details of AMD’s Embedded Write and
Erase Operations
Embedded Erase Algorithm
The automatic memory sector or memory segment
erase does not require the device to be entirely
pre-programmed prior to executing the Embedded
Erase command. Upon e x ecuting the Embedded Erase
command sequence, the addressed memory sector or
memory segment will automatically write and verify the
entire memory segment or memory sector for an all
“zero” data pattern. The system is not required to provide any controls or timing during these operations.
When the memory sector or memory segment is automatically verified to contain an all “zero” pattern, a
self-timed chip erase-and-verify begins. The erase
and verify operations are complete when the data on
D7 (D15 on the odd byte) of the memory sector or
memory segment is “1” (see Write Operation Status
section) at which time the device returns to the Read
mode. The system is not required to provide any control or timing during these operations. A Reset command after the device has begun execution will stop
the device but the data in the operated segment will
be undefined. In that case, restar t the erase on that
sector and allow it to complete.
When using the Embedded Erase algorithm, the erase
automatically terminates when adequate erase margin
has been achieved f or the memory array (no erase v erify command is required). The margin voltages are internally generated in the same manner as when the
standard erase verify command is used.
The Embedded Erase command sequence is a command only operation that stages the memory sector or
memory segment for automatic electrical erasure of all
bytes in the array. The automatic erase begins on the
rising edge of the WE
and terminates when the data on
D7 of the memory sector or memory segment is “1”
(see Write Operation Status section) at which time the
device returns to the Read mode. Please note that for
the memory segment or memory sector erase operation, Data Polling may be performed at any address in
that segment or sector.
Figure 1 and Tab le 6 illustrate the Embedded Er ase Algorithm, a typical command string and bus operations.
As described earlier, once the memory sector in a device or memory segment completes the Embedded
Erase operation it returns to the Read mode and addresses are no longer latched. Therefore, the device
requires that the address of the sector being erased is
supplied by the system at this particular instant of time.
Otherwise, the system will never read a “1” on D7. A
system designer has two choices to implement the Embedded Erase algorithm:
1. The system (CPU) keeps the sector address (within
any of the sectors being erased) valid during the entire Embedded Erase operation, or
2. Once the system executes the Embedded Erase
command sequence, the CPU takes away the address from the device and becomes free to do other
tasks. In this case, the CPU is required to keep trac k
of the valid sector address by loading it into a temporary register. When the CPU comes back for performing Data Polling, it should reassert the same
address.
Since the Embedded Erase operation takes a significant amount of time (1 s–30 s), option 2 makes more
sense. However, the choice of these two options has
been left to the system designer.
Figure 1 and Tab le 6 illustrate the Embedded Er ase Algorithm, a typical command string and bus operations.
Sector Erase
Sector erase is a six bus cycle operation. There are
two “unlock” write cycles. These are followed by writing the “set up” command. Two more “unlock” write cycles are then followed by the sector erase command.
The sector address (any address location within the
desired sector) is latched on the falling edge of WE,
while the command (data) is latched on the rising
edge of WE. A time-out of 50 µs from the rising edge
of the last sector erase command will initiate the sector erase command(s).
Multiple sectors may be erased by writing the six bus
cycle operations as described above. This sequence is
followed with writes of the sector erase command 30H
to addresses in other sectors to be erased. A time-out
of 50 µs from the rising edge of the WE pulse for the
last sector erase command will initiate the sector erase.
If another sector erase command is written within the
50 µs time-out window the timer is reset. Any command
other than sector erase within the time-out window will
reset the device to the read mode, ignoring the previous command string (refer to Write Operation Status
section for Sector Erase Timer operation). Loading the
sector erase buffer may be done in any sequence and
with anysector number.
Table 6. Embedded Erase Algorithm
Bus Operation Command Comments
Standby Wait for VCC ramp
Write
Embedded Erase
command sequence
6 bus cycle
operation
Read
Data
Polling to
verify erasure
14 AmC0XXDFLKA
Sector erase does not require the user to program the
device prior to erase. The device automatically programs all memory locations to “0” in the sector(s) to be
erased prior to electrical erase. When erasing a sector
or sectors the remaining unselected sectors are not affected. The system is not required to provide any controls or timings during these operations. A Reset
command after the device has begun execution will
stop the device but the data in the operated sector will
be undefined. In that case, restart the erase on that
sector and allow it to complete.
The automatic sector erase begins after the 50 µs time
out from the rising edge of the WE
pulse for the last
sector erase command pulse and terminates when the
data on D7 is “1” (see Write Operation Status section)
at which time the device returns to read mode. Data
Polling must be performed at an address within any of
the sectors being erased.
Figure 1 illustrates the Embedded Erase Algorithm
using typical command strings and bus operations.
Embedded Program Algorithm
The Embedded Program setup is a four bus cycle operation that stages the addressed memory sector or
memory segment for automatic programming.
Once the Embedded Program setup operation is performed, the next WE pulse causes a transition to an active programming operation. Addresses are inter nally
latched on the falling edge of the WE pulse. Data is internally latched on the rising edge of the WE
pulse. The
rising edge of WE
also begins the programming operation. The system is not required to provide further control or timing. The device will automatically provide an
adequate internally generated write pulse and verify
margin. The automatic programming operation is completed when the data on D7 of the addressed memory
sector or memory segment is equivalent to data written
to this bit (see Write Operation Status section) at which
time the device returns to the Read mode (no write verify command is required).
Addresses are latched on the falling edge of WE
during
the Embedded Program command execution and
hence the system is not required to keep the addresses
stable during the entire Programming operation. However, once the device completes the Embedded Program operation, it returns to the Read mode and
addresses are no longer latched. Therefore, the de vice
requires that a valid address input to the device is supplied by the system at this particular instant of time.
Otherwise, the system will never read a valid data on
D7. A system designer has two choices to implement
the Embedded Programming algorithm:
1. The system (CPU) keeps the address valid during
the entire Embedded Programming operation, or
2. Once the system ex ecutes the Embedded Program-
ming command sequence, the CPU takes away the
address from the device and becomes free to do
other tasks. In this case, the CPU is required to
keep track of the valid address by loading it into a
temporary register. When the CPU comes back for
performing Data
Polling, it should reassert the same
address.
Howev er , since the Embedded Programming oper ation
takes only 8 µs typically, it may be easier for the CPU
to keep the address stable during the entire Embedded
Programming operation instead of reasserting the valid
address during Data Polling. An yw a y, this has been left
to the system designer’s choice to go for either operation. An y commands written to the segment during this
period will be ignored.
Figure 2 and Table 7 illustrate the Embedded Program
Algorithm, a typical command string, and bus operation.
Reset Command
The Reset command initializes the sector or segment
to the read mode. Please refer to Tables 3 and 4, “Byte
Command Definitions,” and Table 5, “Word Command
Definitions” for the Reset command operation. The
sector or segment remains enabled for reads until the
command register contents are altered.
19521D-2
Figure 1. Embedded Erase Algorithm
Write Embedded Erase
Command Sequence
(Table 3 and 4)
Data
Poll from Device
(Figure 3)
Start
Erasure Complete
Table 7. Embedded Program Algorithm
Bus Operation Command Comments
Standby Wait for VCC ramp
Write
Embedded Program
command sequence
3 bus cycle
operation
Write
Program Address/
Data
1 bus cycle
operation
Read
Data
Polling to
verify program
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