AMD Advanced Micro Devices AM29LV200T-150EI, AM29LV200T-150EEB, AM29LV200T-150EE, AM29LV200T-150ECB, AM29LV200T-150EC Datasheet

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PRELIMINARY

Am29LV200

2 Megabit (256 K x 8-Bit/128 K x 16-Bit) CMOS 3.0 Volt-onl y Boot Sector Flash Memory

DISTINCTIVE CHARACTERISTICS

■ Single power supply operation

— Full voltage range: 2.7 to 3.6 volt read and write

operations for battery-powered applications

— Regulated voltage range: 3.0 to 3.6 volt read and

write operations and for compatibility with high performance 3.3 volt microprocessors

■ High performance

— Full voltage range: access times as fast as 100

— Regulated voltage range: access times as fast as

90 ns

■ Ultra low power consumption (typical v alues at 5

MHz)

— 200 nA Automatic Sleep mode current — 200 nA standby mode current — 10 mA read current — 20 mA program/erase current

■ Flexible sector architecture

— One 16 Kbyte, two 8 Kbyte, one 32 Kbyte, and

three 64 Kbyte sectors (byte mode)

— One 8 Kword, two 4 Kword, one 16 Kword, and

three 32 Kword sectors (word mode) — Supports full chip erase — Sector Protection features:

A hardware method of locking a sector to prevent

any program or erase operations within that

sector

Sectors can be locked via programming

equipment

Temporary Sector Unprotec t feature allows code

changes in previously locked sectors

■ Top or bottom boot block configurations

available

■ Embedded Algorithms

— Embedded Erase algorithm automatically

preprograms and erases the entire chip or any combination of designated sectors

— Embedded Program algorithm automatically

writes and verifies data at specified addresses

■ Typical 1,000,000 write cycles per sector

(100,000 cycles minimum guaranteed)

■ Package option

— 48-pin TSOP — 44-pin SO

■ Compatibility with JEDEC standards

— Pinout and software compatible with single-

power supply Flash

— Superior inadvertent write protection

■ Data# Polling and toggle bits

— Provides a software method of detecting program

or erase operation completion

■ Ready/Busy# pin (RY/BY#)

— Provides a hardware method of detecting

program or erase cycle completion

■ Erase Suspend/Erase Resume

— Suspends an erase operation to read data from,

or program data to, a sector that is not being erased, then resumes the erase operation

■ Hardware reset pin (RESET#)

— Hardware method to reset the device to reading

array data

Publication# 20513 Rev: D Amendment/+1 Issue Date: March 1998

PRELIMINARY

GENERAL DESCRIPTION

The Am29LV200 is a 2 Mbit, 3.0 volt-only Flash memory organized as 262,144 bytes or 131,072 words. The device is offer ed in 44-pin S O and 48-pin TSO P packages. The word-wide data (x16) appears on

DQ15–DQ0; the byte-wide (x8) data appears on DQ7– DQ0. This device is designed to be programmed insystem using only a single 3.0 volt V is required for write or erase operations. The device can also be programmed i n standard EPROM programmers.

The standard device offers access times of 90, 100, 120, and 150 ns, allowing high speed microprocessors to operate without wait states. To eliminate bus contention the device has separate chip enable (CE#), write enable (WE#) and output enable (OE#) controls.

The device requires only a single 3.0 volt power sup- ply for both read and write functions. Internally generated and regulated voltages are provided for the program and erase operations.

The device is entirely command set compatible with the JEDEC single-power-supply Flash standard. Commands are written to the command register using standard micropr ocessor write ti mings. Register c ontents serve as input to an i nternal state-machine that controls the erase and programming circuitry. Write cycles also internally latch addresses and dat a needed for the programming and erase operations. Reading data out of the device is similar to reading from other Flash or EPROM devices.

Device programming occurs by executing the program command sequence. This initiates the Embedded Program algorithm—an internal algorithm that automatically times the program pulse widths and verifies proper cell margin.

Device erasure occurs by executing the erase command sequence. This initiates the Embedded Erase algorithm—an internal algorithm that automatically preprograms the array (if it is not already programmed) before executing the erase operation. During erase, the device automatically times the erase pulse widths and verifies proper cell margin.

supply. No V

The host system can detect whether a program or erase operation is complete by observing the RY/BY# pin, or by re ading the DQ7 (D ata# Polling) and DQ6 (toggle) status bits. After a program or erase cycle has been completed, the device is ready to read array data or accept another command.

The sector erase architecture allows memory sectors to be erased and reprogrammed without affecting the data contents of other sectors. The device is fully erased when shipped from the factory.

Hardware data protection measures include a low

detector that automatically inhibits write opera-

tions during p ower transitions. The hardware sector protection feature disables both program and erase

operations in any combination of the sectors of memory. This can be achieved via programming equipment.

The Erase Sus pend feature enables the user to put erase on hold for any period of time to read data from, or program data to, any sector that is not selected for erasure. True background erase can thus be achieved.

The hardware RESET# pin terminates any operation in progress and resets the internal state machine to reading array data. The RESET# pin may be tied to the system reset circuitry. A system reset would thus also reset the device, enabling the system microprocessor to read the boot-up firmware from the Flash memory.

The device offers two pow er-saving features. When addresses have been stable for a specified amount of time, the device enters the automatic sleep mode. The system can also place the device into the standby mode. Power consumption is greatly reduced in both these modes.

AMD’s Flash technology combines years of Flash memory manufacturing experience to produce the highest levels of quality, reliability and cost effectiveness. The device e lectrically erases a ll b its wit hin a sector simultaneously via Fowler-Nordheim tunneling. The data is programmed using hot electron injection.

Am29LV200 2

PRELIMINARY

PRODUCT SELECTOR GUIDE

Family Part Number Am29LV200

Speed Options

Max access time, ns (t Max CE# access time, ns (tCE) 90 100 120 150 Max OE# access time, ns (tOE) 40 40 50 55

Regulated Voltage Range: VCC =3.0–3.6 V -90R

Full Voltage Range: VCC = 2.7–3.6 V -100 -120 -150

) 90 100 120 150

ACC

Note: See “AC Characteristics” for full specifications.

BLOCK DIAGRAM

DQ0

DQ15 (A-1)

–

Input/Output

Buffers

Data

Latch

RESET#

WE#

BYTE#

CE#

OE#

RY/BY#

State

Control

Command

PGM Voltage

Generator

Sector Switches

Erase Voltage

Generator

Chip Enable

Output Enable

Logic

STB

A0–A16

VCC Detector

Timer

STB

Address Latch

Y-Decoder

X-Decoder

Y-Gating

Cell Matrix

20513D-1

3 Am29LV200

CONNECTION DIAGRAMS

PRELIMINARY

A15 A14 A13 A12 A11 A10

A8 NC NC

WE#

RESET#

NC NC

RY/BY#

NC NC

A16

BYTE#

DQ15/A-1

DQ7

DQ14

DQ6

DQ13

DQ5

DQ12

DQ4

DQ11

DQ3

DQ10

DQ2

DQ9

DQ1

DQ8

DQ0

OE#

CE#

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

Standard TSOP

Reverse TSOP

48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25

A16 BYTE# V

DQ15/A-1 DQ7 DQ14 DQ6 DQ13 DQ5 DQ12 DQ4

DQ11 DQ3 DQ10 DQ2 DQ9 DQ1 DQ8 DQ0 OE#

CE# A0

A15 A14 A13 A12 A11 A10 A9 A8 NC NC WE# RESET# NC NC RY/BY# NC NC A7 A6 A5 A4 A3 A2 A1

20513D-2

Am29LV200 4

CONNECTION DIAGRAMS

PRELIMINARY

NC NC

A7 A6 A5 A4 A3 A2 A1 A0

CE#

OE# DQ0 DQ8 DQ1 DQ9 DQ2

DQ3

2 3 4 5 6 7 8

9 10 11 12 13 14 15 16 17 18 19 20 21 22

RY/BY#

DQ10 DQ11

PIN CONFIGURATION

A0–A16 = 17 addresses DQ0–DQ14 = 15 data inputs/outputs DQ15/A-1 = DQ15 (data input/output, word mode),

A-1 (LSB address input, byte mode)

RESET#

WE#

A10

A11

A12

A13

A14

A15

A16

BYTE#

DQ15/A-1

DQ7

DQ14

DQ6

DQ13

DQ5

DQ12

DQ4

LOGIC SYMBOL

A0–A16

20513D-3

16 or 8

DQ0–DQ15

(A-1)

BYTE# = Selects 8-bit or 16-bit mode CE# = Chip enable OE# = Output enable WE# = Write enable RESET# = Hardware reset pin, active low RY/BY# = Ready/Busy# output

= 3.0 volt-only single power supply

(see Product Selector Guide for speed options and voltage supply tolerances)

= Device ground

NC = Pin not connected internally

CE# OE#

WE# RESET# BYTE# RY/BY#

20513D-4

5 Am29LV200

PRELIMINARY

ORDERING INFORMATION Standard Pr od ucts

AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed by a combination of the elements below.

CE-90RAm29LV200 T

OPTIONAL PROCESSING

Blank = Standard Processing B = Burn-in (Contact an AMD representative for more information)

TEMPERATURE RANGE

C=Commercial (0°C to +70°C) I = Industrial (–40°C to +85°C) E = Extended (–55°C to +125°C)

PACKAGE TYPE

E = 48-Pin Thin Small Outline Package (TSOP)

Standard Pinout (TS 048)

F = 48-Pin Thin Small Outline Package (TSOP)

Reverse Pinout (TSR048)

Am29LV200T-90R, Am29LV200B-90R

Am29LV200T-100, Am29LV200B-100

Am29LV200T-120, Am29LV200B-120

Am29LV200T-150, Am29LV200B-150

Valid Combinations

EC, EI, FC, FI, SC, SI

EC, EI, EE,

FC, FI, FE, SC, SI, SE

SPEED OPTION

See Product Selector Guide and Valid Combinations

BOOT CODE SECTOR ARCHITECTURE

T = Top Sector B = Bottom Sector

DEVICE NUMBER/DESCRIPTION

Am29LV200 2 Megabit (256 K x 8-Bit/128 K x 16-Bit) CMOS Flash Memory

3.0 Volt-only Read, Program, and Erase

Valid Combinations

Valid Combinations list configurations planned to be supported in volume for this device. Consult the local AMD sales office to confirm availability of specific valid combinations and to check on newly released combinations.

Am29LV200 6

PRELIMINARY

DEVICE BUS OPERATIONS

This section describes the re quirements and us e of the device bus operations, which are initiated through the internal command register . The command register itself does not occupy any ad dressable memory locatio n. The register is composed of latches that store the commands, along with the address and data information needed to execute the command. The contents of the

Table 1. Am29LV200 Device Bus Operations

Operation CE# OE# WE# RESET#

Read L L H H A

Write L H L H A

Standby Output Disable L H H H X High-Z High-Z High-Z

Reset X X X L X High-Z High-Z High-Z T emporary Sector Unprotect X X X V

Legend:

L = Logic Low = V

Note: Addresses are A16:A0 in word mode (BYTE# = V

, H = Logic High = VIH, VID = 12.0 ± 0.5 V , X = Don’t Care, AIN = Addresses In, DIN = Data In, D

0.3 V

VCC ±

0.3 V

), A16:A-1 in byte mode (BYTE# = VIL).

register serve as inputs to the internal state machine. The state machine outputs d ictate the function of the device. Table 1 lists the device bus operations, the inputs and control levels they require, and the resulting output. The following subsections describe each of these operations in further detail.

DQ8–DQ15

OUT

BYTE#

= V

OUT

Addresses

(See Note)

IN IN

X High-Z High-Z High-Z

DQ0–

DQ7

BYTE#

= V

DQ8–DQ14 = High-Z,

DQ15 = A-1

High-Z

= Data Out

OUT

Word/Byte Configuration

The BYTE# pin controls whether the device data I/O

pins DQ15–DQ0 operate in the byte or word configuration. If the BYTE# pin is set at logic ‘1’, the device is in word configuration, DQ15–DQ0 are active an d c ontrolled by CE# and OE#.

If the BYTE# pin is set at logic ‘0’, the device is in byte configuration, and only data I/O pins DQ0–DQ7 ar e active and controlled by CE# and OE#. The data I/O pins DQ8–DQ14 are tri-stated, and the DQ15 pin is used as an input for the LSB (A-1) address function.

Requirements for Reading Array Data

To read array data from the outputs, the system must drive the CE# and OE# pins to V control and selects the device. OE# is the output control and gates array data to the output pins. WE# should remain at V

. The BYTE# pin determines

whether the device outputs array data in words or bytes.

The internal state machine is set for reading array data upon device power-up, or after a hardware reset. This ensures that no spurious alteration of the memory content occurs during the power transition. No command is necessary in this mode to obtain array data. Standard microprocessor read cycles that assert valid addr esses on the device address inputs produce valid data on the device data outpu ts. The device rem ains enabled for

. CE# is the power

read access until the command register contents are altered.

See “Reading Array Data” for more information. Refer to the AC Read Operations table for timing specifications and to Figure 12 for the timing diagram. I

CC1

the DC Characteristics table represents the active current specification for reading array data.

Writing Commands/Command Sequences

To write a command or command sequence (which includes programming data to the device and erasing sectors of memory), the system must drive WE# and CE# to V

For program op erations, the BYTE# pin deter mines whether the device accepts program data in bytes or words. Refer to “Word/Byte Configuration” for more information.

An erase operation can erase one sector, multiple sectors, or the entire device. Tables 2 and 3 indicate the address space that each sector occupies. A “sector address” consists of the address b its requ ired to uni quely select a sector. See the “Command Definitions” section has details on erasing a sector or the entire chip, or suspending/resuming the erase operation.

After the system writes the autoselect command sequence, the device enters the autoselect mode. The system can then read autoselect codes from the inter-

, and OE# to VIH.

7 Am29LV200

PRELIMINARY

nal register (which is separate from the memory array)

on DQ7–DQ0. Standard read cycle timings apply in this mode. Refer to the “Autoselect Mode” and “Autoselect Command Sequence” sections for more information.

in the DC Characteristics table represents the ac-

CC2

tive current specification for the write mode . The “AC Characteristics” section contains timing specification tables and timing diagrams for write operations.

Program and Erase Operation Status

During an erase or program operation, t he system may check the status of the operation by reading the status bits on DQ7–DQ0. Standard read cycle timings and I

read specificat ions apply. Refer to “Write Operation Status” for more information, and to “AC Characteristics” for timing diagrams.

Standby Mode

When the system is not reading or writing to the device, it can place the device in the standby mo de. In this mode, current consumption is greatly reduced, and the outputs are placed in the high impedance state, independent of the OE# input.

The device enters the CMOS standby mode when the CE# and RESET# pins are both held at V

± 0.3 V.

(Note that this is a more restricted voltage range than

.) If CE# and RESET# are held at VIH, but not within

± 0.3 V , t he device will be in the standby mode, but

the standby current will be greater . The devi ce requires standard access time (t

) for read access when the

device is in either of these standby modes, before it is ready to read data.

If the device is deselected during erasure or programming, the device draws active current until the operation is completed.

In the DC Characteristics table, I

CC3

and I

CC4

repre-

sents the standby current specifications.

Automatic Sleep Mode

The automatic sleep mode minimizes Flash device energy consumption. The device automatically enables this mode when addresses rema in stable for

+ 30 ns. The automatic sleep mode is inde-

ACC

pendent of the CE#, WE#, and OE# control signals. Standard address access timings provide new data

when addresses are changed. While in sleep mode, output data is latched and always available to the system. I

in the DC Characteristics table represents

CC5

the automatic sleep mode current specification.

RESET#: Hardware Reset Pin

The RESET# pin provides a hardware method of resetting the device to reading array data. When the RESET# pin is driven to V

for at least a period of tRP,

the device immediately terminates any operation in progress, tristates all output pins, and ignores all read/write commands for the duration of the RESET# pulse. The device also resets the internal state machine to reading array data. The operation that was interrupted should be reinitiated once the device is ready to accept another command sequence, to ensure data integrity.

Current is reduced for the duration of the RESET# pulse. When RESET# is held at V draws CMOS standby current (I

but not within VSS±0.3 V , the standby current will

at V

±0.3 V, the device

). If RESET# is held

CC4

be greater. The RESET# pin may be tied to the system reset cir-

cuitry. A system reset would thus also reset the Flash memory, enabling the system to read the boot-up firmware from the Flash memory.

If RESET# is asserted during a program or erase operation, the RY/BY# pin remains a “0” (busy) until the internal reset operation is complete, which re quires a time of t

(during Embedded Algorithms). The

READY

system can thus monitor RY/BY# to determine whether the reset operation is co mplete. If RESET# is asserted when a program or erase operation is not executing (RY/BY# pin is “1”), the reset opera tion is completed within a time of t

READY

rithms). The system can read data t SET# pin returns to V

(not during Embedded Algo-

after the RE -

Refer to the AC Characteristics tables for RESET# parameters and to Figure 13 for the timing diagram.

Output Disable Mode

When the OE# input is at VIH, output from the device is disabled. The output pins are placed in the high impedance state.

Am29LV200 8

PRELIMINARY

Table 2. Am29LV200T Top Boot Block Sector Address Table

Sector Size

(Kbytes/

Sector A16 A15 A14 A13 A12

SA0 0 0 X X X 64/32 00000h–0FFFFh 00000h–07FFFh SA1 0 1 X X X 64/32 10000h–1FFFFh 08000h–0FFFFh SA2 1 0 X X X 64/32 20000h–2FFFFh 10000h–17FFFh SA3 1 1 0 X X 32/16 30000h–37FFFh 18000h–1BFFFh SA4 1 1 1 0 0 8/4 38000h–39FFFh 1C000h–1CFFFh SA5 1 1 1 0 1 8/4 3A000h–3BFFFh 1D000h–1DFFFh SA6 1 1 1 1 X 16/8 3C000h–3FFFFh 1E000h–1FFFFh

Kwords)

Address Range (in hexadecim al )

(x8)

Address Range

(x16)

Table 3. Am29LV200B Bottom Boot Block Sector Address Table

Sector Size

(Kbytes/

Sector A16 A15 A14 A13 A12

SA0 0 0 0 0 X 16/8 00000h–03FFFh 00000h–01FFFh SA1 0 0 0 1 0 8/4 04000h–05FFFh 02000h–02FFFh SA2 0 0 0 1 1 8/4 06000h–07FFFh 03000h–03FFFh SA3 0 0 1 X X 32/16 08000h–0FFFFh 04000h–07FFFh SA4 0 1 X X X 64/32 10000h–1FFFFh 08000h–0FFFFh SA5 1 0 X X X 64/32 20000h–2FFFFh 10000h–17FFFh SA6 1 1 X X X 64/32 30000h–3FFFFh 18000h–1FFFFh

Kwords)

Address Range (in hexadecim al )

(x8)

Address Range

(x16)

Note for Tables 2 and 3: Address range is A16:A-1 in byte mode and A16:A0 in word mode. See “Word/Byte Configuration”

section for more information.

Autoselect Mode

The autoselect mode provides manu facturer and device identification, and sector protection verification,

through identifier codes output on DQ7–DQ0. This mode is primarily intended for programming equipment to automatically match a device to be programmed with its corresponding progra mming algorithm. However, the autoselect codes can also be accessed in-system through the command register.

When using programming equipment, the autoselect mode requires V

(11.5 V to 12.5 V) on address pin

A9. Address pins A6, A1, and A0 must be as shown in Table 4. In addition, when verifying sector protection,

the sector address must appear on the appropriate highest order address bits (see Tables 2 and 3). Table 4 shows the remaining address bits that are don’t care. When all necessary bits have be en set as required, the programming equipment may then read the corresponding identifier code on DQ7–DQ0.

To access the autoselect codes in-system, the host system can issue the autoselect command via the command register, as shown in Table 5. This method does not require V

. See “Command Definitions” for

details on using the autoselect mode.

9 Am29LV200

Table 4. Am29LV200 Autoselect Codes (High Voltage Method)

Description Mode CE# OE# WE#

PRELIMINARY

A16

A12

A11

A10 A9

A7 A6

A2 A1 A0

DQ8

DQ15

DQ7

DQ0

Manufacturer ID: AMD L L H X X V Device ID:

Am29LV200 (Top Boot Block)

Device ID: Am29LV200 (Bottom Boot Block)

Sector Protection Verification L L H SA X V

L = Logic Low = VIL, H = Logic High = VIH, SA = Sector Address, X = Don’t care.

Word L L H

XXV

Byte L L H X 3Bh

Word L L H

XXV

Byte L L H X BFh

XLXLL X 01h

XLXLH

XLXHL

Sector Protection/Unprotection

The hardware sector protection feature disables both program and erase operations in any sec tor. The hardware sector unprotection feature re-enables both program and erase operations in pre viously protected sectors.

Sector protection/unprotection must be implemented using programming equipment.The procedure requires a high voltage (V tails on this method are provided in a supplement, publication number 21226. Contact an AMD representative to request a copy.

The device is shipped with all sectors unprotected. AMD offers the option of programming and protecting sectors at its factory prior to shipping the device

through AMD’s ExpressFlash™ Service. Contact a n AMD representative for details.

) on address pin A9 and OE#. De-

22h 3Bh

22h BFh

START

RESET# = V

(Note 1)

Perform Erase or

Program Operations

RESET# = V

Temporary Sector

Unprotect Completed

(Note 2)

01h

(protected)

00h

(unprotected)

It is possible to determine whether a sector is protected or unprotected. See “Autoselect Mode” for details.

Temporary Sector Unprotect

This feature allows temporary unp rotection of previously protected sectors to change data in-system. The Sector Unprotect mode is activated by setting the RESET# pin to V sectors can be programmed or erased by selecting the sector addres ses. Once V SET# pin, all the previously protected sectors are protected again. Figure 1 shows the algorithm, and Figure 21 shows the timing diagrams, for this feature.

. During this mode, formerly protected

is removed from the RE-

Am29LV200 10

Notes:

20513D-5

1. All protected sectors unprotected.

2. All previously protected sectors are protected once again.

Figure 1. Temporary Sector Unprotect Operation

PRELIMINARY

Hardware Data Protection

The command sequence requirement of unlock cycles for programming or erasing provides data protection against inadvertent writes ( refer to Table 5 for command definitions). In add ition, the following hardwar e data protection measures preve nt accidental erasure or programming, which might otherwise be caused by spurious system level signals during V

power-up

and power-down transitions, or from system noise.

Low V

When V cept any write cycles. This protects data during V

Write Inhibit

is less than V

, the device does not ac-

LKO

power-up and power-down. The command register and all internal program/erase circuits are disabled, and the device resets. Subsequent writes are ignored until V is greater than V

. The system must provide the

LKO

proper signals to the control pins to prevent unintentional writes when V

is greater than V

LKO

COMMAND DEFINITIONS

Writing specific address and data command s or sequences into the command register initiates device operations. Table 5 defines the valid register command sequences. Writing incorrect address and data val- ues or writing them in the improper sequence resets the device to reading array data.

All addresses are latched on the falling edge of WE# or CE#, whichever happens later. All data is latched on the rising edge of WE# or CE#, whichever happens first. Refer to the appropriate timing diagrams in the

“AC Characteristics” section.

Reading Array Data

The device is a utomatically set to reading array data after device power-up. No commands are required to retrieve data. The device is also ready to read array data after completing an Em bedded Program or Embedded Erase algorithm.

After the device accepts an Erase Suspend command, the device enters the Erase Suspend mode. The system can read array data using the standard read timings, except that if it reads at an address within erasesuspended sectors, the device outputs status data. After completing a programming operation in the Erase Suspend mode, the system may once again read array data with the same exception. See “Erase Suspend/Erase Resume Commands” for more information on this mode.

must

The system ble the device for reading array data if DQ5 goes high, or while in the autoselect mode. See the “Reset Command” section, next.

issue the reset command to re-ena-

Write Pulse “Glitch” Protection

Noise pulses of less than 5 ns (typical) on OE#, CE# or WE# do not initiate a write cycle.

Logical Inhibit

Write cycles are inhibited by holding any one of OE# =

, CE# = VIH or WE# = VIH. To initiate a write cycle,

CE# and WE# must be a logical zero wh ile OE# is a logical one.

Power-Up Write Inhibit

If WE# = CE# = V

and OE# = VIH during power up, the

device does not accept commands on the rising edge of WE#. The internal state machin e is automatically reset to reading array data on power-up.

See also “Requirements for Reading Array Data” in the “Device Bus Operations” section for more information. The Read Operations table provides the read parameters, and Figure 12 shows the timing diagram.

Reset Command

Writing the reset command to the device resets the device to reading array data. Address bits are don’t care for this command.

The reset command may be written between the sequence cycles in an erase command sequence before erasing begins. This resets the device to reading array data. Once erasure begins, however, the device ignores reset commands until the operation is complete.

The reset command may be written between the sequence cycles in a program command sequence before programming begins. This resets the device to reading array data (also applies to programming in Erase Suspend mode). Once programming begins, however, the device ignores reset commands until the operation is complete.

The reset command may be written between the sequence cycles in an autoselect command sequence. Once in the autoselect mode, the reset command be written to return to reading array data (also applies to autoselect during Erase Suspend).

If DQ5 goes high during a program or erase operat ion, writing the reset command returns the device to reading array data (also applies during Erase Suspend).

must

11 Am29LV200

PRELIMINARY

Autoselect Command Sequence

The autoselect command sequence allows the host system to access the manufacturer and devices codes, and determine whether or not a sector is protected. Table 5 shows the address and data requirements. This method is an alternative to that shown in Table 4, which is intended for PROM programmers and requires

on address bit A9.

The autoselect command sequence is initiated by writing two unlock cycles, followed by the autoselect command. The device then enters the autoselect mode, and the system may read at any address any number of times, without initiating another command sequence.

A read cycle at address XX00h retrieves the manufacturer code. A read cycle at address XX01h in word mode (or 02h in byte mode) returns the device code. A read cycle containing a sector address (SA) and the address 02h in wor d mode (or 04h i n byte mode) returns 01h if that sector is protected, or 00h if it is unprotected. Refer to Tables 2 and 3 for valid sector addresses.

The system must write the reset command to exit the autoselect mode and return to reading array data.

Word/Byte Program Command Sequence

The system may program the device by word or byte, depending on the state of the BYTE# pin. Programming is a four-bus-cycle operation. The program command sequence is initiated by writing two unlock write cycles, followed by the program set-up command. The program addre ss and data are writte n next, which in turn initiate the Embedded Program algorithm. The

not

system is ings. The device automatically provides internally generated program pulses and verifies the programmed cell margin. Table 5 shows the address and data requirements for the byte program command sequence.

When the Embedded Program algorithm is complete, the device then returns to reading array data and addresses are no longer latched. The system can determine the status of th e program operation by usin g

DQ7, DQ6, or RY/BY#. See “Write Operation Status” for information on these status bits.

Any commands written to the device during the Embedded Program Algorithm are ignored. Note that a hardware reset immediately terminates the programming operation. The program command sequence should be reinitiated once the device has reset to reading array data, to ensure data integrity.

Programming is allowed in any s equence and across sector boundaries. A bit cannot be programmed

from a “0” back to a “1”. Attempting to do so may halt

the operation and set DQ5 to “1”, or cause the Data# Polling algorithm to indicate the operation was suc -

required to provide further controls or ti m-

cessful. However, a succeeding read will show that the data is still “0”. Only erase operations can convert a “0” to a “1”.

Figure 2 illustrates the algorithm for the program operation. See the Erase/Program Operations table in “AC Characteristics” for parameters, and to Figure 16 for timing diagrams.

START

Write Program

Command Sequence

Data Poll

Embedded

Program

algorithm

in progress

Increment Address

Note: See Table 5 for program command sequence.

from System

Verify Data?

Yes

Last Address?

Yes

Programming

Completed

20513D-5

Figure 2. Program Operation

Chip Erase Command Sequence

Chip erase is a six bus cycle operation. The chip erase command sequence is ini tiated by writing two unlock cycles, followed by a set-up command. Two additional unlock write cycles are then followed by the chip erase command, which in turn invokes the Embedded Erase

not

algorithm. The device does preprogram prior to erase. The Embedded Erase algorithm automatically preprograms and verifi es the entire memory for an all zero data pattern prior to electrical erase. The system is not required to provide any controls or timings during these operations. Table 5 shows the address and data requirements for the chip erase command sequence.

require the system to

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