AMD Advanced Micro Devices AM29LV004T-90RFIB, AM29LV004T-90RFEB, AM29LV004T-90RFCB, AM29LV004T-90RFC, AM29LV004T-90REIB Datasheet

PRELIMINARY

This document contains in formation on a product under development at Adv anced Micro Device s . The information
is intended to help you evaluate this product. AMD reserves the right to change or discontinue work on this proposed
product without notice.

Publication# 20510 Rev: D Amendment/+1
Issue Date: March 1998

Refer to AMD’s Website (www.amd.com) for the latest information.

Am29LV004

4 Megabit (512 K x 8-Bit)
CMOS 3.0 Volt-only Boot Sector Flash Memo r y

DISTINCTIVE CHARACTERISTICS

■ Single p ower supply operation

— Full vol t ag e r ange : 2. 7 t o 3.6 v o l t re ad an d w r ite

operations f or battery-powered app licati ons

— Regulated voltage range: 3.0 to 3.6 volt read

and write operations and for compatibility with
high performance 3.3 volt microprocessors

■ High performance

— Full voltage range: access times as fast as 100

ns

— Regulated voltage range: access times as fast

as 90 ns

■ Ultra low power consumptio n (typical values at

5 MHz)

— 200 nA Automatic Sleep mo de current
— 200 nA sta ndby mode current
— 10 mA read current
— 20 mA program/erase current

■ Flexible sector architecture

— One 16 Kbyte, two 8 Kbyte, one 32 Kbyte, and

seven 64 Kbyte sectors
— Supports full chip erase
— Sector Protection features:

A hardware method of locking a sector to

preve nt any program or erase operations within

that sector

Sectors can be locked via programming

equipment

T empor ary Sect or Unprote ct featu re allows c ode

changes in previously locked sectors

■ Top or bottom boot block configurations

available

■ Embedded Algorithms

— Embedded Erase al gorithm automatically

preprograms and erases the entire chi p or any
combination of designated sectors

— Embedded Program algorithm automatically

writes and verifies d ata at sp ecified addresses

■ Typical 1,000,000 write cycles per sector

(100,000 cycles minimum guaranteed)

■ Package option

— 40-pin TSOP

■ Compatibility with JEDEC standards

— Pinout and software compatible with single-

power supply Flash

— Superior inadvertent write p r otection

■ Data# Polling a nd toggle bits

— Provides a software method of detecting

program or erase operation completion

■ Ready/Bu sy # pin (RY/BY#)

— Provides a hardware method of detecting

program or erase cycle completion

■ Erase Su s pe nd/E r as e Resume

— Suspends an erase operation to read data from,

or program data to, a sector that is not being
erased, then resumes the erase operation

■ Hardware reset pin (RESET#)

— Hardware method to reset the device to reading

array data

2 Am29LV004

PRELIMINARY

GENERAL DESCRIPTION

The Am29LV004 is an 4 Mbit, 3.0 volt-only Flash
memory organized as 524,288 bytes. The device is
offered in a 40-pin TSOP package. The byte-wide (x8)

data appe ars on DQ7 –DQ 0. This devic e requ ires onl y
a single, 3.0 volt V

CC

supply to pe rf o rm r ea d, pr og ra m,
and erase operations. A stan dard EPROM pro­grammer can als o be us ed to pr ogram a nd erase the
device.

The standard device offers access times of 90, 100,
120, and 150 ns, allowing high speed microprocessors
to operate without wait states. To eliminate bus conten­tion the d evice ha s separat e chip en able (CE #), writ e
enable (WE#) and outp ut enabl e (OE#) controls.

The device requires only a single 3.0 volt power sup-
ply for both rea d an d write fu nct ions. Interna l ly g en er ­ated and r egulated voltages a re provided for th e
program and erase operations.

The device is entirely command set compatible with the
JEDEC single-power-supply Flash standard. Com­mands ar e w ri tt en to th e c om ma nd re gi s ter us i ng st a n­dard micr opro cess or wr ite timi ngs. R egi ster c ont ents
serve as input to an internal state-machine that con­trols the erase and programming circuitry. Write cycles
also internally latch addresses and data needed for the
progra mming and e rase o pera tion s. Re ading d ata ou t
of the de vice is s imilar to readin g from o ther Flas h or
EPROM devices.

Device programming occurs by executing the program
command sequence. This initiates the Embedded
Program algorithm—an internal algorithm that auto­matical ly time s the program pulse widths and ver ifies
proper cell margin.

Device erasure occurs by executing the erase command
sequence. This initiates the Embedded Erase algo­rithm—an internal algorithm that automatically prepro­grams the array (if it is not already programmed) before
executing the erase operation. During erase, the device
automatically times the erase pulse widths and verifies
proper cell margin.

The host system can detect whether a program or
erase op eratio n is co mpl ete by o bse rving th e RY/B Y#
pin, or by reading the DQ7 (Data# Polling) and DQ6
(toggle) status bits. After a program or erase cycle
has been com p lete d, the devic e is re ady to read a rra y
data o r accept another command.

The sector erase architecture allows memory sect ors
to be er ased and reprog rammed withou t affecting the
data contents of other sectors. The device is fully
erased when shipped from the factory.

Hardware data protection measures include a l ow
V

CC

detector that au tomatically inhibits write opera­tions during power transitions. The hardware sector
protection feature disables both program and erase
operat ions in any combina tion of the s ectors of m em­ory. This can be achieved via programming equipment.

The Erase Suspend feature enables the user to put
erase on hold for any period of time to read data from,
or program data to, any sector that is not selected for
erasure. True background erase can thus be achieved.

The hardware RESET# pin terminates a ny operatio n
in progress and resets the internal state machine to
reading array data. The RESET# pin may b e ti ed to t he
system reset circuitry. A system reset would thus als o
reset the device, enabling the system microprocessor
to read the boot-up firmware from the Flash memory.

The device offers two power-saving features. When
addres ses have been stable for a s p ec i fied amount o f
time, the device enters the automatic sleep mode.
The system can also place the device into the standby
mode. Power co nsumpt ion is greatly reduc ed in bot h
these modes.

AMD’s Flash technology combines years of Flash
memory manufacturing experience to produce the
highest levels of quality, reliability and cost effective­ness. The device electrically erases all b its with in
a sector simultaneously via Fowler-Nordheim tun­neling. The data is programmed using hot electron
injection.

Am29LV004 3

PRELIMINARY

PRODUCT SELECTOR GUIDE

Note: See “AC Characteristics” for full specifications.

BLOCK DIAGRAM

Family Part Number Am29LV004

Speed Options

Regulated Voltage Range: VCC =3.0–3.6 V -90R

Full Voltage Range: VCC = 2.7–3.6 V -100 -120 -150

Max access time, ns (t

ACC

) 90 100 120 150
Max CE# access time, ns (tCE) 90 100 120 150
Max OE# access time, ns (tOE) 40 40 40 55

Input/Output

Buffers

X-Decoder

Y-Decoder

Chip Enable

Output Enable

Logic

Erase Voltage

Generator

PGM Voltage

Generator

Timer

VCC Detector

State

Control

Command

Register

V

CC

V

SS

WE#

CE#

OE#

STB

STB

DQ0

–

DQ7

Sector Switches

RY/BY#

RESET#

Data

Latch

Y-Gating

Cell Matrix

Address Latch

A0–A18

21522A-1

4 Am29LV004

PRELIMINARY

CONNECTION DIAGRAMS

1

16

2
3
4
5
6
7
8

17
18
19
20

9
10
11
12
13
14
15

40

25

39
38
37
36
35
34
33
32
31
30
29
28
27
26

24
23
22
21

A16

A5

A15
A14
A13
A12
A11

A9
A8

WE#

RESET#

NC

RY/BY#

A18

A7
A6

A4
A3
A2
A1

A17

DQ0

V

SS

NC
NC
A10
DQ7
DQ6
DQ5

OE#
V

SS

CE#
A0

DQ4
V

CC

V

CC

NC
DQ3
DQ2
DQ1

1

16

2
3
4
5
6
7
8

17
18
19
20

9
10
11
12
13
14
15

40

25

39
38
37
36
35
34
33
32
31
30
29
28
27
26

24
23
22
21

A16

A5

A15
A14
A13
A12
A11
A9
A8
WE#
RESET#
NC
RY/BY#
A18
A7
A6

A4
A3
A2
A1

A17

DQ0

V

SS

NC
NC

A10
DQ7
DQ6
DQ5

CE#

V

SS

CE#

A0

DQ4

V

CC

V

CC

NC
DQ3
DQ2
DQ1

21522A-2

Reverse TSOP

Standard TSOP

Am29LV004 5

PRELIMINARY

PIN CONFIGURATION

A0–A18 = 19 addresse s
DQ0–DQ7 = 8 data inputs/outputs
CE# = Chip enable
OE# = Output enable
WE# = Write enable
RESET# = Hardware reset pin, active low
RY/BY# = Ready/Busy# output
V

CC

= 3.0 volt-only single power supply

(see Product Selector Guide for speed
options and voltage supply tolerances)

V

SS

= Device ground

NC = Pin not connected internally

LOGIC SYMBOL

21522A-3

19

8

DQ0–DQ7

A0–A18

CE#
OE#

WE#
RESET#

RY/BY#

6 Am29LV004

PRELIMINARY

ORDERING INFORMATION
Standard Products

AMD sta nd ar d p rod ucts are av a il ab le i n seve ral packa ge s and opera ti ng ra ng es. The order nu mb er (Valid Co mb i ­nation) is formed by a combination of the elements below.

Valid Combinations

Valid Combinations list configurations planned to be sup­ported in volume for this device. Consult the local AMD sales
office to confirm availability of specific valid combinations and
to check on newly released combinations.

DEVICE NUMBER/DE SCRIP TION

Am29LV004
4 Megabit (512 K x 8-Bit) CMOS Flash Memory

3.0 Volt-only Read, Program, and Erase

CET

Am29LV004

-90R

OPTIONAL PROCESSING

Blank = Standard Proces sing
B = Burn-in
(Contact an AMD representative for more information)

TEMPERATURE RANGE

C=Commercial (0°C to +70°C)
I = Industrial (–40°C to +85°C)
E = Extended (–55°C to +125°C)

PACKAGE TYPE

E = 40-Pin Thin Small Outline Package (TSOP)

Standard Pinout (TS 040)

F = 40-Pin Thin Small Outline Package (TSOP)

Reverse Pinout (TSR040)

SPEED OPTION

See Product Selector Guide and Valid Combinations

BOOT CODE SECTOR ARCHITECTURE

T = Top Sector
B = Bottom Sector

Valid Combinations

Am29LV004T-70R,
Am29LV004B-70R

EC, EI, FC, FI

Am29LV004T-80,
Am29LV004B-80

EC, EI, EE, FC, FI, FE

Am29LV004T-90,
Am29LV004B-90

Am29LV004T-120,
Am29LV004B-120

Am29LV004 7

PRELIMINARY

DEVICE BUS OPERATIONS

This section describes the requirements and use of the
device bus operations, which are initiated through the
internal command register. The command register itself
does not occupy any addressable memo ry location.
The reg iste r is co mposed of lat che s that store the co m­mands, along with the address and data information
needed to execu te the com mand . The co nte nts of th e

register serve a s input s to the inter nal sta te mac hine.
The state machine outputs dictate the function of the
device. Table 1 lists the devi ce bus op erat ions , the in­puts and control levels they require, and the resulting
output. The following subsections describe eac h of
these operations in further detail.

Table 1. Am29LV004 Device Bus Operations

Legend:

L = Logic Low = VIL, H = Logic High = VIH, VID = 12.0 ± 0.5 V, X = Don’t Care, AIN = Address In, DIN = Data In, D

OUT

= Data Out

Note: Addresses are A18–A0.

Requirements for Reading Array Data

To read array dat a from the ou tputs, the sys tem must
drive the CE# and OE # pins to V

IL

. CE# is the power
control an d sel ects the de vice . OE# is th e outpu t con­trol and gates array data to the output pins. WE#
should remain at V

IH

.

The internal state machine is set for reading array
data upon devic e power-up, or aft er a hardware re set .
This ensures that no spurious alteration of the mem­ory content occurs during the power transition. No
command is necessary i n this mode to obtain array
data. Standard micropr ocessor read cycles that as­sert valid addresses on the device add ress inputs pr o­duce valid data on the device data outputs. The
device remains enabled for read access unt il the com­mand register contents are altered.

See “R ead ing Ar ray Data” fo r more info rmatio n. Refer
to the AC Read Operations table for timing specifica­tions and to Figure 12 for the timing diagram. I

CC1

in

the DC Characteristics table represents the active cur­rent specification for reading array data.

Writing Commands/Command Sequences

To write a command or command sequence (which in­cludes programming data to the device and erasing
sectors of memory ), the sy stem m ust drive WE# an d
CE# to V

IL

, and OE# to VIH.

An eras e op e ra tio n ca n er ase on e s ect or, multipl e se c­tors, or the entire device. Tables 2 and 3 indicate the
address space that each sector occupies. A “sector ad­dress” cons ists of the address bits required to uniquely
select a sector. The “Command Defini tions” section
has details on erasing a sector or the entire chip, or
suspending/resuming the erase operation.

After the system writes the autoselect command se­quence, the device enters the autoselect mode. The
system can th en re ad aut ose lect codes fr om th e inter ­nal register (which is separate from the memory array)
on DQ7– DQ0 . St anda rd r ead cycle ti ming s ap ply in this
mode. Re fer to th e “ Autosele ct Mo de” an d “ Au to select
Command Sequence” sections for more information.

I

CC2

in the DC Charac teristics table represents the ac­tive current specification for the write mode. The “AC
Characteristics” section contains timing specification
tables and timing diagrams for write operations.

Program and Erase Operation Status

During an erase or program operation, the system may
check the status of the operation by reading the status
bits on DQ7–DQ0. Standard read cycle timings and I

CC

read specificati ons apply. Refer to “Write Operation
Status” for more information, and to “AC Characteris­tics” for timing diagrams.

Operation CE# OE# WE# RESET# Addresses (See Note) DQ0–DQ7

Read L L H H A

IN

D

OUT

Write L H L H A

IN

D

IN

Standby

V

CC

±

0.3 V

XX

VCC ±

0.3 V

X High-Z

Output Disable L H H H X High-Z
Reset X X X L X High-Z
Temporary Sector Unprotect X X X V

ID

A

IN

D

IN

8 Am29LV004

PRELIMINARY

Standby Mode

When th e sy st em is not read ing or wr itin g to the dev ice,
it can place the device in the standby mode. In this
mode, current consumption is greatly reduced, and the
outputs are placed in the high impedance state, inde­pendent of the OE# input.

The dev ice en ter s t he CM OS st an dby mode wh en the
CE# and RESET# pins are both held at V

CC

± 0.3 V.
(Note th at thi s is a mor e res trict ed vol tage rang e tha n
V

IH

.) If CE# and RESET# are held at VIH, but no t wit hin

V

CC

± 0.3 V, the device will be in the standby mode, but
the standby current will be greater. The device requires
standard access time (t

CE

) for read access when the
device is i n e ith er of these st and by modes, before it is
ready to read data.

If the device i s desele cte d during erasur e or pro gram ­ming, the device draws active current until the
operation is completed.

In the DC C haracte ristic s tabl es, I

CC3

and I

CC4

repre-

sents the standby current specification.

Automatic Sleep Mode

The au tomatic sl eep mode m inimizes F lash devi ce
energy co nsumption. The device autom atically
enables this mode when addresses remain stable for
t

ACC

+ 30 ns. The automatic sleep mode is indepen­dent of the CE # , WE #, an d O E # co ntr ol s i gn als. St an ­dard address access timings provide new data when
addresses are changed. While in sleep mode, output
data is latched and always available to the system. I

CC5

in the DC Characteristics table represents the auto­matic sleep mode current specification.

RESET#: Hardware Reset Pin

The RESET# pin provides a hardware method of reset­ting the device to reading array data. When the RE-

SET# pin is driven low for at least a per iod of t

RP

, the
device immediately terminates any operation in
progress, tristates all output pins, and ignores all
read/write commands for the duration of the RESET#
pulse. The device also resets the internal state ma­chine to reading array data. The operation that was in­terrupted should be reinitiated once the device is ready
to accept another command sequence, to ensure data
integrity.

Current is reduced for the duration of the RESET #
pulse. When RESET# is held at V

SS

±0.3 V, the device

draws CMOS standby current (I

CC4

). If RESET# is held

at V

IL

but no t wi t hin VSS±0.3 V, the standby current will

be greater.
The RESET# pin may be tied to the system reset cir-

cuitry. A system rese t would thus also res et th e Flas h
memory, enabling the system to read the boot-up firm­ware from the Flash memory.

If RESET# is asserted during a program or erase op­eration, the RY/BY# pin remains a “0” (busy) until the
internal reset operation is complete, which requires a
time of t

READY

(during Embedded Algorithms ). The
system can thus m onitor RY/BY# to determine
whether the reset op erati on is c ompl ete. If R ESET # is
asserted when a prog ram or erase operati on is not ex ­ecuting (RY/BY# pin is “1”), the reset operation is
completed within a time of t

READY

(not during Embed-

ded Algorithms). The system can read data t

RH

after

the RESET# pin returns to V

IH

.

Refer to the AC Characteristics tables for RESET# pa­rameters and to Figure 13 for the timing diagram.

Output Disable Mode

When the OE# input is at VIH, output from the device is
disabl e d . Th e o ut p ut pi n s ar e pl a c ed i n t he h igh i m ped­ance state.

Am29LV004 9

PRELIMINARY

Table 2. Am29LV004T Top Boot Block Sector Address Table

Table 3. Am29LV004B Bottom Boot Block Sector Address Table

Autoselect Mode

The autoselect mode provides manufacturer and de­vice identification, and sector protection verification,

through identifier codes output on DQ7–DQ0. This
mode is primarily intended for programming equipment
to auto mati ca lly match a de vice to b e pr ogra mmed with
its corresponding programming al gorithm. However,
the aut osel ect co des can also be a cces sed in -sy stem
through the command register.

When using programming equipment, the autoselect
mode requires V

ID

(1 1.5 V to 12.5 V) on address pin A9.

Address pins A6, A1, and A0 must be as shown in Table

4. In addition, when verifying sector protection, the sec-

tor address must appear on the appropriate highest
order address bits (see Tables 2 and 3). Table 4 shows
the remaining address bits that are don’t care. When all
necessary bits have been set as required, the program­ming equipment may then read the corresponding iden­tifier code on DQ7–DQ0.

To access the autoselect codes in-system, the host
system can issue the autoselect command via the
command register, as shown in Table 5. This method
does not require V

ID

. See “Command Definitions” for

details on using the autoselect mode.

Sector A18 A17 A16 A15 A14 A13

Sector Size

(Kbytes)

Address Range

(in hexadecimal)

SA0 0 0 0 X X X 64 00000h-0FFFFh
SA1 0 0 1 X X X 64 10000h-1FFFFh
SA2 0 1 0 X X X 64 20000h-2FFFFh
SA3 0 1 1 X X X 64 30000h-3FFFFh
SA4 1 0 0 X X X 64 40000h-4FFFFh
SA5 1 0 1 X X X 64 50000h-5FFFFh
SA6 1 1 0 X X X 64 60000h-6FFFFh
SA7 1 1 1 0 X X 32 70000h-77FFFh
SA8 1 1 1 1 0 0 8 78000h-79FFFh
SA9 1 1 1 1 0 1 8 7A000h-7BFFFh

SA10 1 1 1 1 1 X 16 7C000h-7FFFFh

Sector A18 A17 A16 A15 A14 A13

Sector Size

(Kbytes)

Address Range

(in hexadecimal)

SA0 0 0 0 0 0 X 16 00000h-03FFFh
SA1 0 0 0 0 1 0 8 04000h-05FFFh
SA2 0 0 0 0 1 1 8 06000h-07FFFh
SA3 0 0 0 1 X X 32 08000h-0FFFFh
SA4 0 0 1 X X X 64 10000h-1FFFFh
SA5 0 1 0 X X X 64 20000h-2FFFFh
SA6 0 1 1 X X X 64 30000h-3FFFFh
SA7 1 0 0 X X X 64 40000h-4FFFFh
SA8 1 0 1 X X X 64 50000h-5FFFFh
SA9 1 1 0 X X X 64 60000h-6FFFFh

SA10 1 1 1 X X X 64 70000h-7FFFFh

10 Am29LV004

PRELIMINARY

Table 4. Am29LV004 Autoselect Codes (High Voltage Method)

L = Logic Low = VIL, H = Logic High = VIH, SA = Sector Address, X = Don’t care.

Sector Protection/Unprotection

The hardware sector protection feature disables both
program and erase operations in any sector. The hard­ware sector unprotection feature re-enables both pro­gram and eras e operat ions in p reviou sly prot ected
sectors.

The device is shipped with all secto rs unprotected .
AMD offers the option of progra mming and prote cting
sectors at its factory prior to shipping the device

through AMD’s ExpressFlash™ Service. Contact an
AMD representative for details.

It is p ossi ble t o det ermi ne wh ethe r a s ector is p rotec ted
or unprotected. See “Autoselect Mo de” for details.

Sector protection/unprotection must be implemented
using programming equipment.The procedure requires
a high voltage (V

ID

) on addr ess pin A9 a nd OE#. De ­tails on this method are provided in a supplement, pub­licat ion n umbe r 20 874. Cont act an A MD re pre senta tive
to request a copy .

Temporary Sector Unprotect

This feature allows temporary unprotection of previ­ously protected sectors to change data in-system. The
Sector U n pr ote ct m od e i s a cti va ted by s e tting th e R E­SET# pin t o V

ID

. During thi s mod e, form erly pr otecte d
sector s can b e pr o gr amm ed or er as ed by s ele ct i ng t he
sector addres ses. Once V

ID

is remove d fro m the RE -

SET# pin, all the previously protected sectors are
protected a gain. Figure 1 sh ows the algorithm, a nd
Figure 19 shows the timing diagrams, for this feature.

Description CE# OE# WE#

A18

to

A13

A12

to

A10 A9

A8

to

A7 A6

A5

to

A2 A1 A0

DQ7

to

DQ0

Manufacturer ID: AMD L L H X X V

ID

XLXLL 01h

Device ID: Am29LV004T
(Top Boot Block)

LLHXXV

ID

XLXLH B5h

Device ID: Am29LV004B
(Bottom Boot Block)

LLHXXV

ID

XLXLH B6h

Sector Protection Verification L L H SA X V

ID

XLXHL

01h

(protected)

00h

(unprotected)

START

Perform Erase or

Program Operations

RESET# = V

IH

Temporary Sector

Unprotect Completed

(Note 2)

RESET# = V

ID

(Note 1)

Notes:

1. All protected sectors unprotected.

2. All previously protected sectors are protected once
again.

Figure 1. Temporary Sector Unprotect Operation

21522A-4

Am29LV004 11

PRELIMINARY

Hardware Data Protection

The command sequence requir ement of unlock cycle s
for programming or erasing provides data protection
against inadvertent writes (refer to Table 5 for com­mand definitions). In addition, the following hardware
data protection measures prevent accidental erasure
or prog ramm ing, w hich m ig ht othe rwis e be ca use d by
spurious system level signals during V

CC

power-up

and power-down transition s, or from system noise.

Low V

CC

Write I nhibit

When V

CC

is less than V

LKO

, the device does not ac-

cept any write cycles. This protects data during V

CC

power-up and power-down. The command register and
all internal program/erase circuits are disabled, and the
device resets. Subsequent writes are ignored until V

CC

is greater t han V

LKO

. The system must p rovide the
proper signals to the control pins to prevent uninten­tional writes when V

CC

is greater than V

LKO

.

Write Pulse “Glitch” Protection

Noise pulses of less than 5 ns (typical) on OE#, CE# or
WE# do not initiate a write cycle.

Logical Inhibit

Write cycles are inhibited by holding any one of OE# =
V

IL

, CE# = VIH or WE# = VIH. To initiate a writ e cycle,
CE# and WE# must be a logical zero while OE# is a
logical one.

Power-Up Write Inhibit

If WE# = CE# = V

IL

and OE# = VIH during po wer up, the
device does not accept commands on the rising edge
of WE#. The internal state machine is automatically
reset to reading array data on power-up.

COMMAND DEFINITIONS

Writing specific ad dress and data commands or se­quences into the command register initiates device op­erations. Table 5 defines the valid register command
sequences. W riting incor rect ad dress and da ta val-
ues or writing them in the improper sequence resets
the device to reading array data.

All addresses are latched on the falling edge of WE# or
CE#, whichever happens later. All data is latched on
the rising edge of WE# or CE#, whichever happens
first. Refer to the appropriate timing diagrams in the

“AC Characteristics” section.

Reading Array Data

The device is automatically set to reading array data
after d evice power- up. N o comm ands ar e requ ired t o
retrieve data. The device is also ready to read array
data after completing an Embedded Program or Em­bedded Erase algorithm.

After the device accepts an Erase Suspend com­mand, the de vice enters the E rase Suspend m ode.
The system can read array data using the standard
read timings, except that if it reads at an address
within erase-susp ended sectors, the device outputs
status data. After completing a programming opera­tion in the Erase Suspend mode, the system may
once again read array data with the same exception.
See “Erase Suspend/Erase Resume Commands” for
more information on this mode.

The syst em

must

issue the reset command to re-en­able the device for reading array data if DQ5 goes high,
or while in the a utoselect mode. Se e the “R eset C om ­mand” section, next.

See also “Requirements for Reading Array Data” in the
“Devic e B u s Op er at io ns ” section f or m ore i n for ma tion.
The Read Operations table provides the read parame­ters, and Figure 12 shows the timing diagram.

Reset Command

Writing the reset command to the device resets the de­vice to r ea di n g a rr ay da ta. A dd re ss bits ar e do n’t car e
for this command.

The reset command may be written between the se­quence cycles in an erase command sequence before
erasing begins. This resets the device to reading array
data. Once erasure begins, however, the device ig­nores reset commands until t he operation is complete.

The reset command may be written between the se­quence cycles in a program command sequence be­fore programmi ng begins. This resets the device to
reading a rray data (a lso applie s to programm ing in
Erase Su spend mode ). Once p rogrammin g begins,
however, the device ignores r eset co m mand s until th e
operat ion i s comp l et e.

The reset command may be written between the se­quence cycles in an autoselect command sequence.
Once in the autoselect mode, the reset command

must

be written to re turn to re ading ar ray data (also applies
to autoselect during Erase Suspend).

If DQ5 goes high during a program or erase operation,
writing the res et comm and r eturn s th e devic e to re ad­ing array data (also applies during Erase Suspend).

12 Am29LV004

PRELIMINARY

Autoselect Command Sequence

The autoselect comm and sequence allows the host
system to access the manufacturer and devices codes,
and determine whether or not a sector is protected.
Table 5 shows th e address and d ata requiremen ts.
This meth od is an alternati ve to th at sh own in Table 4,
which is intended for PROM programmers and requires
V

ID

on address bi t A9.

The auto sel e c t comm an d se qu enc e i s ini ti a te d by wr i t­ing two unlock cycles, followed by the autos elect com ­mand. The device then enters the autoselect mode,
and the s yste m may r ead at any addre ss any n um ber
of time s, witho ut initia ting ano ther comma nd sequen ce.

A read cycle at address XX00h retrieves the manufac­turer code. A read cy cle a t address X X0 1h r eturn s th e
device code. A read cycle containing a sector address
(SA) and the address 02h returns 01h if that sector is
protect ed, or 00 h i f it is un pr ote cte d. R e fe r to Tables 2
and 3 for valid sector addresses.

The system must wr ite the reset comma nd to exit the
autoselect mode and return to reading array data.

Byte Program Command Sequence

Programming is a four-bus-cycle operation. The pro­gram command sequence is initiated by writing two un­lock write cycles, followed by the program set-u p
comman d. T he pr ogra m ad dres s an d dat a are wr itten
next, which in turn initiate the Embedded Program a l­gorithm. The system is

not

required to provide further
controls or timin gs. The device automat ically provides
intern ally ge ne r ated p r og ra m pu lse s a nd ve ri fy t h e pr o­grammed cell marg in. Table 5 shows the a ddre ss an d
data requirements for the byte program command se­quence .

When th e Embe dded Pr ogra m algor ithm is compl ete,
the devic e then returns to readi ng array data a nd ad­dresses a re no l ong er latc hed. The sys tem can de ter­mine the status of the program operation by using

DQ7, DQ6, or RY/BY#. See “Write Operation Status”
for information on these status bits.

Any commands written to the device during the Em­bedded Program Algorithm are ignored. Note that a
hardware reset immediately t ermin ates the p rogram­ming opera tion. The Byte Prog ram command se­quence should be reinitiated once the device has reset
to reading array data, to ensure data integrity.

Programming is allowed in any sequence and across
sector boundaries. A bit cannot be programmed

from a “0” back to a “1”. Attempting to do so may halt

the oper ation and set DQ5 to “1”, or cau se the Data #
Polling algorithm to indicate the operation was suc­cessful. However, a succeeding read will show that the
data is still “0”. Only erase operations can convert a “0”
to a “1”.

Figure 2 illustrates the algorithm for the program oper­ation. See the Erase/Program Operations table in “AC
Characteristics” for parameters, and to Figure 14 for
timing diagrams.

Note: See Table 5 for program command sequence.

Figure 2. Program Operation

START

Write Program

Command Sequence

Data Poll

from System

Verify Data?

No

Yes

Last Address?

No

Yes

Programming

Completed

Increment Address

Embedded

Program

algorithm

in progress

21522A-4

Am29LV004 13

PRELIMINARY

Chip Erase Command Sequence

Chip erase is a six bus cycle operation. The chip erase
command s equence i s initiate d by writin g two unloc k
cycles, followed by a set-up command. Two additional
unlock wri t e cyc l es ar e t he n fo ll owe d by th e ch ip era se
command, which in turn invokes the Embedded Erase
algorithm. The device does

not

require the system to
preprogram prior to erase. The Embedded Erase algo­rithm automatical ly preprograms and verifies t he entire
memo ry for an all zero d ata pa ttern prio r to ele ctric al
erase. The system is not required to pro vide any con­trols or timings during these operations. Table 5 shows
the addr ess and data requirem ents for the chip eras e
command sequence .

Any commands written to the chip during the Embed­ded Erase algorithm are ignored. Note that a hardware
reset during the chip erase operation immediately ter­minates the operation. The Chip Erase command se­quence should be reinitiated once the device has
returned to reading array data, to ensure data integrity.

The syste m can deter mine the stat us of the e ras e op­eration by using DQ7, DQ6, DQ2, or RY/BY#. See

“Write Operation Status” for information on these sta­tus bits. When the Embedded Erase algorithm is com­plete, the device returns to reading array data and
addresses are no longer latched.

Figure 3 illustr ates the algor ithm for the e rase opera­tion. See the E rase/P rog ram Ope ratio ns tabl es in “AC
Characteristics” for parameters, and to Figure 15 for
timing diagrams.

Sector Erase Command Sequence

Sector erase is a six bus cycle operation. The sector
erase command sequence is i nitiated by writing two
unlock c ycl es , f o ll owed by a s et- up co mm an d. Two ad­ditional unlock write cycles are then followed by the ad­dress o f th e sector to be er ase d, an d the sec tor e ras e
command. Table 5 shows the addre ss and data re­quirements for the sector erase command sequence.

The device does

not

require the system to preprogram
the memory prior to erase. The Embedded Erase algo­rithm automatically programs and verifies the sector for
an all zero data pattern prior to electrical erase. The
system is not required to provide any controls or tim­ings during these operations.

After the command sequence is written, a sector erase
time-out of 50 µs begins. During the time-out period,
additi onal secto r addresses and secto r erase com ­mands may be written. Loading the sector erase buffer
may be done in any sequence, and the number of sec­tors may be from one sector to all sectors. The time be­tween th es e add it i onal cyc l e s must be less th an 50 µs,
otherwise the last address and command might not be
accepted , and era sur e ma y beg in. It i s re comm ende d

that processor interrupts be disabled during this time to
ensure all commands are accepted. The interrupts can
be re-e nabled after the la st Sec tor Er ase com man d is
written. If the time between additional sector erase
commands can be assumed to be less than 50 µs, the
system need not monitor DQ3. Any command other

than Sector Erase or Erase Suspend during the
time-out period resets the device to reading array
data. The system must rewrite the command sequence

and any additional sector addresses and commands.
The system can monitor DQ3 to determine if the sector

erase timer has timed out. (See the “DQ3: Sector
Erase T imer” sectio n.) The t ime-out begins f rom the ri s­ing edge of the final WE# pulse in the command se­quence .

Once the sector erase operation has begun, only the
Erase Sus p en d co mma nd is v al id. A ll o the r c o mman ds
are ignored. Note that a hardware reset during the
sector er as e op er atio n i m me diately ter min ate s the op ­eration . Th e S ec tor E ras e c o mm an d sequenc e sh ou l d
be reinitiated once the device has retu rned to rea ding
array data, to ensure data integrity.

When the Embedded Erase algorithm is complete, the
device returns to reading array data and addresses are
no longer latch ed. The system can determ ine the sta ­tus of the erase operation by using DQ7, DQ6, DQ2, or
RY/BY #. ( Ref er t o “W rit e Oper ati on Stat us” for i nfo rma­tion on these status bits.)

Figure 3 illustr ates the algor ithm for the e rase opera­tion. Refer to the Era se/Progra m Operat ions table s in
the “AC Characteristics” section for parameters, and to
Figure 15 for timing diagrams.

Erase Suspend/Erase Resume Commands

The Erase Suspend command allow s the system to in­terrupt a sector e rase operation a nd then read data
from, or program data to, any sector not selected for
erasure. This command is valid only during the sector
erase operation, including the 50 µs time-out period
during the sector erase command sequence. The
Erase Suspend command is ignored if written during
the chip eras e o pera tion o r Em bedd ed P rogr am a lgo­rithm. Writing the Erase Suspend command during the
Sector Erase time-out immediately terminates the
time-out period and suspends the erase operation. Ad­dresses are “don’ t- car es” w he n w ri tin g the Eras e S u s­pend command.

When the Era s e Su sp end c o mma nd is written du ring a
sector erase operation, the device requires a maximum
of 20 µs to su spend the er ase operation. H owever,
when the Erase Suspend command is written during
the sector erase tim e-out, th e device imm ediate ly ter­minates the time-out period and suspends the erase
operat ion.

14 Am29LV004

PRELIMINARY

After the eras e operation has been su spended, the
system can read array data from or program data to

any sector not selected for erasure. (The device “erase
suspends” all sec tors selected for erasure.) N ormal
read and write timings and command definitions apply.
Reading at any address within erase-suspended sec­tors produces status data on DQ7–DQ0. The system
can use D Q7 , or DQ6 and DQ2 toge th er, to deter mi n e
if a sector is actively erasing or is erase-suspended.
See “Write Op eration St atus” for informat ion on thes e
status bits.

After an erase-suspended program operation is com­plete, the system can once again read array data within
non-suspended sectors. The system can determine the
status of the program operation using the DQ7 or DQ6
status bits, just as in the standard program operation.
See “Write Operation Status” for more information.

The system may also write the autoselect command
sequence when the device is in the Erase Suspend
mode. The device allows r eading autoselect codes
even at addresses within erasing s ectors, since the
codes are not stored in the memory array. When the
device exits the autoselect mode, the device reverts to
the Erase Su spend mode, an d is ready for ano ther
valid op er ati o n. Se e “A ut os e lec t Comm an d Se qu en c e”
for more information.

The system must write the Erase Resume command
(address bits are “don’t care”) to exit the erase suspend
mode an d co nt in ue th e se ct or e ra se op era ti on. Fu rt h er
writes of the Re sume comman d are ig nored. A nothe r
Erase Suspend command can be written after the de­vice has resumed erasing.

Notes:

1. See Table 5 for erase command sequence.

2. See “DQ3: Sector Erase Timer” for more information.

Figure 3. Erase Operatio n

START

Write Erase

Command Sequence

Data Poll

from System

Data = FFh?

No

Yes

Erasure Completed

Embedded
Erase
algorithm
in progress

21522A-5

Am29LV004 15

PRELIMINARY

Table 5. Am29LV004 Command Definitions

Legend:

X = Don’t care
RA = Address of the memory location to be read.
RD = Data read from location RA during read operation.
PA = Address of the memory location to be programmed.

Addresses latch on the falling edge of the WE# or CE# pulse,
whichever happens later.

PD = Data to be programmed at location P A. Data latches on the
rising edge of WE# or CE# pulse, whichever happens first.

SA = Address of the sector to be verified (in autoselect mode) or
erased. Address bits A18–A13 uniquely select any sector.

Notes:

1. See Table 1 for description of bus operations.

2. All values are in hexadecimal.

3. Except when reading array or autoselect data, all

commandbus cycles are write operations.

4. Address bits A18–A11 are don’t cares for unlock and

command cycles.

5. No unlock or command cycles required when reading array

data.

6. The Reset command is required to return to reading array

data when device is in the autoselect mode, or if DQ5 goes
high (while the device is providing status data).

7. The fourth cycle of the autoselect command sequence is a
read cycle.

8. The data is 00h for an unprotected sector and 01h for a
protected sector. See “Autoselect Command Sequence” for
more information.

9. The system may read and program in non-erasing sectors, or
enter the autoselect mode, when in the Erase Suspend
mode. The Erase Suspend command is valid only during a
sector erase operation.

10. The Erase Resume command is valid only during the Erase
Suspend mode.

Command
Sequence

(Note 1)

Bus Cycles (Notes 2-4)

First Second Third Fourth Fifth Sixth

Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data

Read (Note 5) 1 RA RD
Reset (Note 6) 1 XXX F0

Auto­select
(Note 7)

Manufacturer ID 4 555 AA 2AA 55 555 90 X00 01
Device ID, Top Boot Block 4 555 AA 2AA 55 555 90 X01 B5
Device ID, Bottom Boot Block 4 555 AA 2AA 55 555 90 X01 B6

Sector Protect V erif y
(Note 8)

4 555 AA 2AA 55 555 90

(SA)

X02

00

01
Program 4 555 AA 2AA 55 555 A0 PA PD
Chip Erase 6 555 AA 2AA 55 555 80 555 AA 2AA 55 555 10
Sector Erase 6 555 AA 2AA 55 555 80 555 AA 2AA 55 SA 30
Erase Suspend (Note 9) 1 XXX B0
Erase Resume (Note 10) 1 XXX 30

Cycles

16 Am29LV004

PRELIMINARY

WRITE OPERATION STATUS

The device provides several bits to determine the sta­tus of a write op eratio n: DQ2, DQ 3, DQ5, DQ6 , DQ7,
and RY/BY#. Table 6 and the following subsections de­scribe the functions of these bits. DQ7, RY/BY#, and
DQ6 each offer a method for determining whether a
program or erase operation is complete or in progress.
These three bits are discussed first.

DQ7: Data# Polling

The Data# Polling bit, DQ7, indicates to the host s ystem
whether an Embedded Algorithm is in progress or com­pleted, or whether th e device is in Erase Suspen d.
Data# Polling is valid after the rising edge of the final
WE# pulse in the program or erase command se­quence.

During the Embedded Program algorithm, the device
outputs on DQ7 the c ompleme nt of the da tum pro­grammed to DQ7. This DQ7 status also applies to pro­gramming during Erase Suspend. When the
Embedde d Pro gram al gorith m is co mplete , the devic e
outputs the datum programmed to DQ7. The system
must provide the program address to read valid status
information on DQ7. If a program address falls within a
protected sector, Data# Polling on DQ7 is active for ap­proximately 1 µs, then the device returns to reading

array data.
During the Embedded Erase algorithm, Data# Polling

produces a “0” on DQ7. When the Embedded Erase al­gorithm is comp lete, o r if the de vice en ters t he Erase
Suspend mode, Data# Polling produces a “1” on DQ7.
This is analogous to the complement/true datum output
described for the Embedded Program algorithm: the
erase function changes all the bits in a sector to “1”;
prior to this, the device outputs the “complement,” or
“0.” The system must provide an address within any of
the sectors selected for erasure to read valid status in­formation on DQ7.

After an erase command sequence is written, if all sec­tors selected for erasing are protected, Data# Polling
on DQ7 is active for approximately 100 µs, then the de­vice returns to reading array data. If not all selected
sectors are protected, the Embedded Erase algorithm
erases the unprotected sectors, and ignores the se­lected sectors that are protected.

When the sys tem det ects DQ7 h as changed from the
complement to true data, it can read valid data at DQ7–
DQ0 on t h e

following

read cycles. This is because DQ7
may change asynchronously with DQ0–DQ6 while
Output Enable (OE#) is asserted low. Figure 16, Data#
Polling Timings (During Embedded Algorithms), in the
“AC Characteristics” section illustrates this.

Ta ble 6 show s the outputs fo r Data# Polling o n DQ7.
Figure 4 shows the Data# Polling algorithm.

DQ7 = Data?

Yes

No

No

DQ5 = 1?

No

Yes

Yes

FAIL

PASS

Read DQ7–DQ0

Addr = VA

Read DQ7–DQ0

Addr = VA

DQ7 = Data?

START

Notes:

1. VA = Valid address for programming. During a sector
erase operation, a valid address is an address within any
sector selected for erasure. During chip erase, a valid
address is any non-protected sector address.

2. DQ7 should be rechecked even if DQ5 = “1” because

DQ7 may change simultaneously with DQ5.

21522A-6

Figure 4. Data# Polling Al gorithm

Am29LV004 17

PRELIMINARY

RY/ BY#: Read y/Bu sy#

The RY/BY# is a dedicated, open-drain output pin that
indicates whether an Embedded Algorithm is in
progress or complete. The RY/BY# status is valid after
the rising edge of the f inal WE# pulse in the command
sequence. Since RY/BY# is an open-drain output, sev­eral RY/BY# pins can be tied together in parallel with a
pull-up resistor to V

CC

.

If the output is low (Busy), the device is actively erasing
or programming. (T his includes programm ing in the
Erase Suspend mode.) If the output is high (Ready),
the device is ready to read array data (including during
the Erase Suspend mode), or is in the standby mode.

Table 6 shows the outputs for RY/BY#. Figures 12, 13,
14 and 15 shows RY/BY# for read, reset, program, and
erase operations, respecti vely.

DQ6: Toggle Bit I

Toggle Bit I on DQ6 indicates whether an Embedded
Progra m or Era se alg ori thm is i n progre ss or comple te,
or whether the device has entered the Erase Suspend
mode. Toggle Bit I may be read at an y address, and i s
valid aft er th e risi n g ed ge of the fin al WE # pu l se in th e
command sequence (prior to the program or erase op­erati on), and duri ng the sector er ase tim e -out.

During an Embe dded Prog ram or Eras e algor ithm op ­eration, succe ssive read cycles to any a ddress c ause
DQ6 to toggle. (The system may use either OE# or
CE# to control the read cycles.) When the operation is
complete, DQ6 stops toggling.

After an erase command sequence is written, if all sec­tors selected for erasing are protected, DQ6 toggles for

approximately 100 µs, then returns to reading array
data. If n ot all selected se ctors are pro te cted , the E m ­bedded Erase algorithm erases the unprotected sec­tors, and ignores the selected sectors that are
protect ed.

The system can use DQ6 an d DQ2 togethe r to deter­mine whether a sector is actively erasing or is erase­suspended. When the device is actively erasing (that
is, th e Em be dd e d Er as e alg or i t hm is i n pr og re s s ), D Q6
toggles. When the device enters the Erase Suspend
mode, DQ6 stop s to ggling . Ho wever, the system must
also use DQ2 to deter mine whic h sector s are eras ing
or erase-suspende d. Alter na tively, the system can use
DQ7 (see the subsection on “DQ7: Data# Polling”).

If a program address falls within a protected sector,
DQ6 togg les f or ap proxi mat ely 2 µs afte r the prog ram
comman d s eq uence is wr it ten , th en returns to r ea di n g
array data.

DQ6 also toggles during the erase-suspend-program
mode, and sto ps toggling once the E mbedded Pro­gram algorithm is complete.

Table 6 shows the ou tputs for Toggle Bit I on DQ6.
Refer to Figure 5 for the toggle bit algorithm, and to Fig­ure 17 in t h e “ AC Ch ar ac ter i s ti cs” s ec ti o n fo r th e t og gle
bit timing diagrams. Figure 18 shows the differences
between DQ2 and DQ6 in graphical form. See also the
subsection on “DQ2: Toggle Bit II”.

DQ2: Toggle Bit II

The “Toggle Bit II” on DQ2, when used with DQ6, indi­cates whether a particular sector is actively erasi ng
(that is, the Embedded Erase algorithm is in progress),
or whet her t hat secto r is eras e-sus pen ded. Toggle B it
II is valid after the rising edge of the final WE# pulse in
the command sequence.

DQ2 toggles when the system reads at addresses
within those sectors that have been selected for era­sure. (The syste m may use eith er OE # or CE # to con ­trol the read cycles.) But DQ2 cann ot distinguish
whether the sector is activ ely erasin g or is erase- sus­pended. DQ6, by comparison, indicates whether the
device is actively erasing, or is in Erase Suspend, but
cannot distinguish which sectors are selected for era­sure. Thus, both status bits are required for sector and
mode information. Refer to Table 6 to compare outputs
for DQ2 and DQ6.

Figure 5 shows the toggle bit algorithm i n flowchart
form, and th e section “ D Q2 : Toggle Bit II” e x p lains the
algorithm. See also the “DQ6: Toggle Bit I” subsection.
Figure 17 sh ows the toggl e bit tim ing d iagram . Fi gur e
18 shows the differences between DQ2 and DQ6 in
graphical form.

Reading Toggle Bits DQ6/DQ2

Refer to Figure 5 for the following discussion. Whenever
the system initially begins reading toggle bit status, it
must read DQ7–DQ0 at least twice in a row to determine
whether a toggle bit is toggling. Typically, the system
would note and store the value of the toggle bit after the
first read. After the second read, the system would com­pare the new value of the toggle bit with the first. If the
toggle bit is not toggling, the device has completed the
program or erase operation. The system can read array
data on DQ7–DQ0 on the following read cycle.

However, if after the initial two read cycles, the system
determines that t he toggle bit is still toggling, t he sys ­tem also should note whether the value of DQ5 is high
(see the section on DQ5). If it is, the system should
then determine again whether the toggle bit is toggling,
since the toggle bi t ma y h av e s top ped toggli ng ju s t a s
DQ5 went high. If the toggle bit is no longer toggling,
the device has su cce ssfu lly comp let ed the prog ram o r
erase operation. If it is still t oggling, t he de vice did not
completed the operation successfully, and the system
must write the reset command to return to reading
array data.

18 Am29LV004

PRELIMINARY

The remaining sc enario is that the system initially de ­termi n es th at th e tog gl e b it i s to gg l i ng a nd D Q 5 ha s n ot
gone high. The system may continue to monitor the
toggle bit and DQ5 through successive read cycles, de­termining t he stat us as de scribed in the previ ous para­graph. Alternatively, it may choose to perform other
system tasks. In this case, the system must start at the
beginning of the algorithm when it returns to determine
the status of the operation (top of Figure 5).

DQ5: Exceeded Timing Limits

DQ5 indi ca te s w h eth er th e p ro gr am or e ra se t i me ha s
exceeded a specified in ternal pulse count lim it. Under

these co ndi tions DQ5 p roduc es a “1.” This i s a fa ilur e
condition that indicates the program or erase cycle was
not successfully completed.

The DQ5 failure condition may appear i f the system
tries to program a “1” to a location that is previously
programmed to “0.” Only an erase operation can

change a “0 ” back to a “ 1.” Un der this condition, the
device halts the operation, and when the operation has

exceeded the timing limits, DQ5 produces a “1.”
Under both these conditions, the system must issue

the reset command to return the device to reading
array data.

DQ3: Sector Erase Timer

After writing a sector erase command sequence, the
system may read DQ3 to determine whether or not an
erase operation has begun. (The sector erase ti mer
does not apply to the chip erase command.) If additional
sectors are selected for erasure, the entire time-out also
applies after each additional sector erase command.
When the time-out is comp lete, DQ3 switches from “0”
to “1.” The system may ignore DQ3 if the system can
guarantee that the time between additional sector
erase commands will always be less than 50 µs. See
also the “Sector Erase Command Sequence” section.

After the sector erase command sequence is written,
the sys t em shou l d re ad th e s t at us o n D Q7 ( Da t a# Pol l­ing) or DQ6 (Toggle Bit I) to ensure the device has ac­cepted the command sequence, and then read DQ3. If
DQ3 is “1”, the internally controlled erase cycle has be­gun; all fur t he r c omman ds (o t her t ha n Era s e Sus p en d)
are ignored until the erase opera tion is complete. If
DQ3 is “0”, the device will accept additional se ctor
erase commands. To ensure the command has been
accepted, the system software should check the status
of DQ3 prio r to and f ollo wing each su bsequ ent se cto r
erase c omman d. If DQ3 is high on the s econd status
check, the last command might not have been ac­cepted. Table 6 shows the outputs for DQ3.

START

No

Yes

Yes

DQ5 = 1?

No

Yes

Toggle Bit

= Toggle?

No

Program/Erase

Operation Not
Complete, Write
Reset Command

Program/Erase

Operation Complete

Read DQ7–DQ0

Toggle Bit

= Toggle?

Read DQ7–DQ0

Twice

Read DQ7–DQ0

Notes:

1. Read toggle bit twice to determine whether or not it is
toggling. See text.

2. Recheck toggle bit because it may stop toggling as DQ5

changes to “1” . See text.

21522A-7

Figure 5. Toggle Bit Algorithm

(Notes
1, 2)

(Note 1)

Am29LV004 19

PRELIMINARY

Table 6. Write Operation Status

Notes:

1. DQ5 switches to ‘1’ when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits.
See “DQ5: Exceeded Timing Limits” for more information.

2. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further details.

Operation

DQ7

(Note 2) DQ6

DQ5

(Note 1) DQ3

DQ2

(Note 2) RY/BY#

Standard
Mode

Embedded Program Algorithm DQ7# Toggle 0 N/A No toggle 0
Embedded Erase Algorithm 0 Toggle 0 1 Toggle 0

Erase
Suspend
Mode

Reading within Erase
Suspended Sector

1 No toggle 0 N/A Toggle 1

Reading within Non-Erase
Suspended Sector

Data Data Data Data Data 1

Erase-Suspend-Program DQ7# Toggle 0 N/A N/A 0

20 Am29LV004

PRELIMINARY

ABSOLUTE MAXIMUM RATINGS

Storage Temperature

Plastic Packages . . . . . . . . . . . . . . . –65°C to +150°C

Ambient Temperature

with Power Applied . . . . . . . . . . . . . –65°C to +125°C

Voltage with Respect to Ground

V

CC

(Note 1) . . . . . . . . . . . . . . . . .–0.5 V to +4.0 V

A9, OE#,

and RESET# (Note 2). . . . . . . . .–0.5 V to +12.5 V

All other pins

(Note 1). . . . . . . . . . . . . . . . . –0.5 V to V

CC

+0.5 V

Output Short Circuit Current (Note 3) . . . . . . 200 mA

Notes:

1. Minimum DC voltage on input or I/O pins is –0.5 V. During
voltage transitions, input or I/O pins may undershoot V

SS

to –2.0 V for periods of up to 20 ns. See Figure 6.
Maximum DC voltage on input or I/O pins is V

CC

+0.5 V.
During voltage transitions, input or I/O pins may overshoot
to V

CC

+2.0 V for periods up to 20 ns. See Figure 7.

2. Minimum DC input voltage on pins A9, OE#, and RESET#
is –0.5 V. During voltage transitions, A9, OE#, and
RESET# may undershoot V

SS

to –2.0 V for periods of up
to 20 ns. See Figure 6. Maximum DC input voltage on pin
A9 is +12.5 V which may overshoot to 14.0 V for periods
up to 20 ns.

3. No more than one output may be shorted to ground at a
time. Duration of the short circuit should not be greater
than one second.

Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device. This is
a stress rating only; functional operation of the device at
these or any other conditions above those indicated in the
operational sections of this data sheet is not implied.
Exposure of the device to absolute maximum rating
conditions for extended periods may affect device reliability.

Figure 6 . Maximum Negative Overshoot

Waveform

Figure 7. Maximum Positive Overshoot

Waveform

OPERATING RANGES

Commercial (C) Devices

Ambient Temperature (T

A

) . . . . . . . . . . . 0°C to +70°C

Industrial (I) Devices

Ambient Temperature (T

A

) . . . . . . . . . –40°C to +85°C

Extended (E) Devices

Ambient Temperature (T

A

) . . . . . . . . –55°C to +125°C

V

CC

Supply Voltages

V

CC

for regulated voltage range. . . . . . .3.0 V to 3.6 V

V

CC

for full voltage range. . . . . . . . . . . .2.7 V to 3.6 V

Operating ranges define those limits between which the func­tionality of the device is guaranteed.

20 ns

20 ns

+0.8 V

–0.5 V

20 ns

–2.0 V

21522A-8

20 ns

20 ns

V

CC

+2.0 V

V

CC

+0.5 V

20 ns

2.0 V

21522A-9

Am29LV004 21

PRELIMINARY

DC CHARACTERISTICS
CMOS Compatible

Notes:

1. The I

CC

current listed is typically less than 2 mA/MHz, with OE# at VIH. Typical VCC is 3.0 V.

2. I

CC

active while Embedded Erase or Embedded Program is in progress.

3. Automatic sleep mode enables the low power mode when addresses remain stable for t

ACC

+ 30 ns.

4. Not 100% tested.

Parameter Description Test Conditions Min Typ Max Unit

I

LI

Input Load Current

V

IN

= VSS to VCC,

V

CC

= VCC

max

±1.0 µA

I

LIT

A9 Input Load Current VCC = V

CC max

; A9 = 12.5 V 35 µA

I

LO

Output Leakage Current

V

OUT

= VSS to VCC,

V

CC

= V

CC max

±1.0 µA

I

CC1

VCC Active Read Current
(Note 1)

CE# = V

IL,

OE#

= VIH

5 MHz 10 16

mA

1 MHz 2 4

I

CC2

VCC Active Write Current
(Notes 2 and 4)

CE# = V

IL,

OE#

= VIH

20 30 mA

I

CC3

VCC Standby Current

V

CC

= V

CC max

;

CE#, RESET# = V

CC

±0.3 V

0.2 5 µA

I

CC4

VCC Standby Current During Reset

V

CC

= V

CC max

;

RESET# = V

SS

± 0.3 V

0.2 5 µA

I

CC5

Automatic Sleep Mode (Note 3)

V

IH

= V

CC

± 0.3 V;

V

IL

= V

SS

± 0.3 V

0.2 5 µA

V

IL

Input Low Voltage –0.5 0.8 V

V

IH

Input High Voltage 0.7 x V

CC

VCC + 0.3 V

V

ID

Voltage for Autoselect and
Temporary Sector Unprotect

V

CC

= 3.3 V 11.5 12.5 V

V

OL

Output Low Voltage IOL = 4.0 mA, VCC = V

CC min

0.45 V

V

OH1

Output High Voltage

I

OH

= –2.0 mA, VCC = V

CC min

0.85 V

CC

V

V

OH2

IOH = –100 µA, VCC = V

CC min

VCC–0.4

V

LKO

Low VCC Lock-Out Voltage (Note

4)

2.3 2.5 V

22 Am29LV004

PRELIMINARY

DC CHARACTERISTICS (Contin ued)
Zero Power Flash

25

20

15

10

5

0

0 500 1000 1500 2000 2500 3000 3500 4000

Supply Current in mA

Time in ns

Note: Addresses are switching at 1 MHz

21522A-10

Figure 8. I

CC1

Current vs. Time (Showing Active and Automatic Sleep Currents)

Note: T = 25 °C

21522A-11

Figure 9. Typical I

CC1

vs. Frequency

15

10

5

0

1 2345

3

.

6

V

2

.

7

V

Frequency in MHz

Supply Current in mA

Am29LV004 23

PRELIMINARY

TE S T CONDITIONS

Table 7. Test Spe cifications

KEY TO SWITCHING WAVEFORMS

2.7 kΩ

C

L

6.2 kΩ

3.3 V

Device

Under

Test

21522A-12

Figure 10 . Test Se tup

Note: Diodes are IN3064 or equivalent

Test Condition

-90R,

-100

-120,

-150 Unit

Output Load 1 TTL gate
Output Load Capacitance, C

L

(including jig capacitance)

30 100 pF

Input Rise and Fall Times 5 ns
Input Pulse Levels 0.0–3.0 V

Input timing measurement
reference levels

1.5 V

Output timing measurement
reference levels

1.5 V

KS000010-PAL

WAVEFORM INPUTS OUTPUTS

Steady

Changing from H to L

Changing from L to H

Don’t Care, Any Change Permitted Changing, State Unknown

Does Not Apply Center Line is High Impedance State (High Z)

3.0 V

0.0 V

1.5 V 1.5 V

OutputMeasurement LevelInput

21522A-13

Figure 11. Input Waveforms and Measurement Level s

24 Am29LV004

PRELIMINARY

AC CHARACTERISTICS
Read Operations

Notes:

1. Not 100% tested.

2. See Figure 10 and Table 7 for test specifications.

Parameter

Description

Speed Option

JEDEC Std Test Setup

-90R -100 -120 -150 Unit

t

AVAV

t

RC

Read Cycle Time (Note 1) Min 90 100 120 150 ns

t

AVQV

t

ACC

Address to Output Delay

CE# = V

IL

OE# = V

IL

Max 90 100 120 150 ns

t

ELQV

t

CE

Chip Enable to Output Delay OE# = V

IL

Max 90 100 120 150 ns

t

GLQV

t

OE

Output Enable to Output Delay Max 40 40 50 55 ns

t

EHQZ

t

DF

Chip Enable to Output High Z (Note 1) Max 30 30 30 40 ns

t

GHQZ

t

DF

Output Enable to Output High Z (Note 1) Max 30 30 30 40 ns

t

OEH

Output Enable
Hold Time (Note 1)

Read Min 0 ns
Toggle and

Data# Polling

Min 10 ns

t

AXQX

t

OH

Output Hold Time From Addresses, CE# or
OE#, Whichever Occurs First (Note 1)

Min 0 ns

t

CE

Outputs

WE#

Addresses

CE#

OE#

HIGH Z

Output Valid

HIGH Z

Addresses Stable

t

RC

t

ACC

t

OEH

t

OE

0 V

RY/BY#

RESET#

t

DF

t

OH

21522A-14

Figure 12. Read Operations Timings

Am29LV004 25

PRELIMINARY

AC CHARACTERISTICS
Hardware Reset (RESET#)

Note: Not 100% tested.

Parameter

Description All Speed OptionsJEDEC Std Test Setup Unit

t

READY

RESET# Pin Low (During Embedded
Algorithms) to Read or Write (See Note)

Max 20 µs

t

READY

RESET# Pin Low (NOT During Embedded
Algorithms) to Read or Write (See Note)

Max 500 ns

t

RP

RESET# Pulse Width Min 500 ns

t

RH

RESET# High Time Before Read (See Note) Min 50 ns

t

RPD

RESET# Low to Standby Mode Min 20 µs

t

RB

RY/BY# Recovery Time Min 0 ns

RESET#

RY/BY#

RY/BY#

t

RP

t

Ready

Reset Timings NOT during Embedded Algorithms

t

Ready

CE#, OE#

t

RH

CE#, OE#

Reset Timings during Embedded Algorithms

RESET#

t

RP

t

RB

21522A-15

Figure 13. RESET# Timings

26 Am29LV004

PRELIMINARY

AC CHARACTERISTICS
Erase/Program Operations

Notes:

1. Not 100% tested.

2. See the “Erase and Programming Performance” section for more information.

Parameter

-90R -100 -120 -150JEDEC Std Description Unit

t

AVAV

t

WC

Write Cycle Time (Note 1) Min 90 100 120 150 ns

t

AVWL

t

AS

Address Setup Time Min 0 ns

t

WLAX

t

AH

Address Hold Time Min 50 50 50 65 ns

t

DVWH

t

DS

Data Setup Time Min 50 50 50 65 ns

t

WHDX

t

DH

Data Hold Time Min 0 ns

t

OES

Output Enable Setup Time Min 0 ns

t

GHWL

t

GHWL

Read Recovery Time Before Write
(OE# High to WE# Low)

Min 0 ns

t

ELWL

t

CS

CE# Setup Time Min 0 ns

t

WHEH

t

CH

CE# Hold Time Min 0 ns

t

WLWH

t

WP

Write Pulse Width Min 50 50 50 65 ns

t

WHWL

t

WPH

Write Pulse Width High Min 30 30 30 35 ns

t

WHWH1tWHWH1

Programming Operation (Note 2) Typ 9 µs

t

WHWH2tWHWH2

Sector Erase Operation (Note 2) Typ sec

t

VCSVCC

Setup Time (Note 1) Min 50 µs

t

RB

Recovery Time from RY/BY# Min 0 ns

t

BUSY

Program/Erase Valid to RY/BY# Delay Min 90 ns

Am29LV004 27

PRELIMINARY

AC CHARACTERISTICS

OE#

WE#

CE#

V

CC

Data

Addresses

t

DS

t

AH

t

DH

t

WP

PD

t

WHWH1

t

WC

t

AS

t

WPH

t

VCS

555h

PA PA

Read Status Data (last two cycles)

A0h

t

GHWL

t

CS

Status

D

OUT

Program Command Sequence (last two cycles)

RY/BY#

t

RB

t

BUSY

t

CH

PA

Note: PA = program address, PD = program data, D

OUT

is the true data at the program address.

21522A-16

Figure 14. Program Operation Timings

28 Am29LV004

PRELIMINARY

AC CHARACTERISTICS

OE#

CE#

Addresses

V

CC

WE#

Data

2AAh SA

t

GHWL

t

AH

t

WP

t

WC

t

AS

t

WPH

555h for chip erase

10 for Chip Erase

30h

t

DS

t

VCS

t

CS

t

DH

55h

t

CH

In

Progress

Complete

t

WHWH2

VA

VA

Erase Command Sequence (last two cycles) Read Status Data

RY/BY#

t

RB

t

BUSY

Note: SA = sector address (for Sector Erase), VA = Valid Address for reading status data (see “Write Operation Status”).

21522A-17

Figure 15. Chip/Sector Erase Operat ion Timings

Am29LV004 29

PRELIMINARY

AC CHARACTERISTICS

WE#

CE#

OE#

High Z

t

OE

High

Z

DQ7

DQ0–DQ6

RY/BY#

t

BUSY

Complement

True

Addresses

VA

t

OEH

t

CE

t

CH

t

OH

t

DF

VA VA

Status Data

Complement

Status Data

True

Valid Data

Valid Data

t

ACC

t

RC

Note: VA = Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array data
read cycle.

21522A-18

Figure 16. Data# Polling Timings (During Embedd ed Algorithms)

WE#

CE#

OE#

High Z

t

OE

DQ6/DQ2

RY/BY#

t

BUSY

Addresses

VA

t

OEH

t

CE

t

CH

t

OH

t

DF

VA VA

t

ACC

t

RC

Valid DataValid StatusValid Status

(first read) (second read) (stops toggling)

Valid Status

VA

Note: V A = V alid address; not required for DQ6. Illustration shows first two status cycle after command sequence, last status read
cycle, and array data read cycle.

21522A-19

Figure 17. Toggle Bit Timings (During Embedded Algorithms)

30 Am29LV004

PRELIMINARY

AC CHARACTERISTICS

Temporary Sector Unprotect

Note: Not 100% tested.

Parameter

All Speed OptionsJEDEC Std Description Unit

t

VIDR VID

Rise and Fall Time (See Note) Min 500 ns

t

RSP

RESET# Setup Time for Temporary Sector
Unprotect

Min 4 µs

Note: The system may use CE# or OE# to toggle DQ2 and DQ6. DQ2 toggles only when read at an address within an
erase-suspended sector.

21522A-20

Figure 18. DQ2 vs. DQ6

Enter

Erase

Erase

Erase

Enter Erase

Suspend Program

Erase Suspend

Read

Erase Suspend

Read

Erase

WE#

DQ6

DQ2

Erase

Complete

Erase

Suspend

Suspend

Program

Resume

Embedded

Erasing

RESET#

t

VIDR

12 V

0 or 3 V

CE#

WE#

RY/BY#

t

VIDR

t

RSP

Program or Erase Command Sequence

0 or 3 V

21522A-21

Figure 19. Temporary Sector Unprotect Timing Diagram

Am29LV004 31

PRELIMINARY

AC CHARACTERISTICS
Alternate CE# Controlled Erase/Pr og ram Operati ons

Notes:

1. Not 100% tested.

2. See the “Erase and Programming Performance” section for more information.

Parameter

JEDEC Std Description Unit

t

AVAV

t

WC

Write Cycle Time (Note 1) Min 90 100 120 150 ns

t

AVEL

t

AS

Address Setup Time Min 0 ns

t

ELAX

t

AH

Address Hold Time Min 50 50 50 65 ns

t

DVEH

t

DS

Data Setup Time Min 50 50 50 65 ns

t

EHDX

t

DH

Data Hold Time Min 0 ns

t

OES

Output Enable Setup Time Min 0 ns

t

GHEL

t

GHEL

Read Recovery Time Before Write
(OE# High to WE# Low)

Min 0 ns

t

WLEL

t

WS

WE# Setup Time Min 0 ns

t

EHWH

t

WH

WE# Hold Time Min 0 ns

t

ELEH

t

CP

CE# Pulse Width Min 50 50 50 65 ns

t

EHEL

t

CPH

CE# Pulse Width High Min 30 30 30 35 ns

t

WHWH1

t

WHWH1

Programming Operation (Note 2) Typ 9 µs

t

WHWH2

t

WHWH2

Sector Erase Operation (Note 2) Typ sec

32 Am29LV004

PRELIMINARY

AC CHARACTERISTICS

t

GHEL

t

WS

OE#

CE#

WE#

RESET#

t

DS

Data

t

AH

Addresses

t

DH

t

CP

DQ7# D

OUT

t

WC

t

AS

t

CPH

PA

Data# Polling

A0 for program
55 for erase

t

RH

t

WHWH1 or 2

RY/BY#

t

WH

PD for program
30 for sector erase
10 for chip erase

555 for program
2AA for erase

PA for program
SA for sector erase
555 for chip erase

t

BUSY

Notes:

1. PA = Program Address, PD = Program Data, DQ7# = complement of the data written to the device, D

OUT

is the data written

to the device.

2. Figure indicates the last two bus cycles of the command sequence.

21522A-22

Figure 20. Alternate CE# Controlled Write Operation Timings

Am29LV004 33

PRELIMINARY

ERASE AND PROGRAMMING PERFORMANCE

Notes:

1. Typical program and erase times assume the following conditions: 25

°

C, 3.0 V VCC, 100,000 cycles. Additionally,

programming typicals assume checkerboard pattern.

2. Under worst case conditions of 90°C, V

CC

= 2.7 V, 100,000 cycles.

3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes
program faster than the maximum program times listed.

4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure.

5. System-level overhead is the time required to execute the four-bus-cycle sequence for the program command. See Table 5
for further information on command definitions.

6. The device has a typical erase and program cycle endurance of 1,000,000 cycles. 100,000 cycles are guaranteed.

LATCHUP CHARACTERISTICS

Includes all pins except VCC. Test conditions: VCC = 3.0 V, one pin at a time.

TSOP PIN CAPACITANCE

Notes:

1. Sampled, not 100% tested.

2. Test conditions T

A

= 25°C, f = 1.0 MHz.

DATA RETENTION

Parameter Typ (Note 1) Max (Note 2) Unit Comments

Sector Erase Time 1 15 s

Excludes 00h programming
prior to erasure (Note 4)

Chip Erase Time 11 s
Byte Programming Time 9 300 µs

Excludes system level
overhead (Note 5)

Chip Programming Time
(Note 3)

4.5 13.5 s

Description Min Max

Input voltage with respect to V

SS

on all pins except I/O pins

(including A9, OE#, and RESET#)

–1.0 V 12.5 V

Input voltage with respect to V

SS

on all I/O pins –1.0 V VCC + 1.0 V

V

CC

Current –100 mA +100 mA

Parameter

Symbol Parameter Description Test Setup Typ Max Unit

C

IN

Input Capacitance VIN = 0 6 7.5 pF

C

OUT

Output Capacitance V

OUT

= 0 8.5 12 pF

C

IN2

Control Pin Capacitance VIN = 0 7.5 9 pF

Parameter Test Conditions Min Unit

Minimum Pattern Data Retention Time

150°C 10 Years
125°C 20 Years

34 Am29LV004

PRELIMINARY

PHYSICAL DIMENSIONS*

TS 040—40-Pin Standard TSOP (measured in millimeters)

* For reference only. BSC is an ANSI standard for Basic Space Centering.

18.30

18.50

19.80

20.20

40

20

Pin 1 I.D.

21

1

0.50 BSC

9.90

10.10

0.95

1.05

0.05

0.15

1.20
MAX

0.50

0.70

0˚
5˚

16-038-TSOP-1_AE
TS 040
2-27-97 lv

0.10

0.21

0.08

0.20

Am29LV004 35

PRELIMINARY

PHYSICAL DIMENSIONS

TSR048—48-Pin Reverse TSOP (measured in millimeters)

18.30

18.50

19.80

20.20

40

20

Pin 1 I.D.

21

1

0.50 BSC

9.90

10.10

0.95

1.05

0.05

0.15

1.20

MAX

0.50

0.70

0˚
5˚

16-038-TSOP-1_AE
TSR040
2-27-97 lv

0.10

0.21

0.08

0.20

36 Am29LV004

PRELIMINARY

REVISION SUMMARY

Global

Revised form atting to b e con siste nt w ith ot her c urren t

3.0 volt-only data sheets.

Revision D+1

AC Characteristics

Erase/Program Operations; Alternate CE# Controlled
Erase/Pr ogram Op erati ons:

Correc ted th e n otes refer -

ence for t

WHWH1

and t

WHWH2

. These parameters are

100% tested. Corrected the note reference for t

VCS

.

This parameter is not 100% tested.

Temporary Sector Unpr otect Table

Added note reference for t

VIDR

. This para meter i s not

100% test ed .

Trademarks

Copyright © 1998 Advanced Micro Devices, Inc. All rights reserved.
AMD, the AMD logo, and combinations thereof are registered trademarks of Advanced Micro Devices, Inc.
ExpressFlash is a trademark of Advanced Micro Devices, Inc.
Product names used in this publication are for identification purposes only and may be trademarks of their respective companies.