AMD Advanced Micro Devices AM29F080B, AM29F080B-120FCB, AM29F080B-120FC, AM29F080B-120EIB, AM29F080B-120EI Datasheet

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PRELIMINARY

Am29F080B

8 Megabit (1 M x 8-Bit) CMOS 5.0 Volt-only, Uniform Sector Flash Memory

DISTINCTIVE CHARACTERISTICS

■ 5.0 V ± 10%, single power supply operation

— Minimizes system level power requirements

■ Manufactured on 0.35 µm process technology

— Compatible with 0.5 µm Am29F080 device

■ High performance

— Access times as fast as 70 ns

■ Low power consumption

— 25 mA typical active read current — 30 mA typical program/erase current — 1 µA typical standby current (standard access

time to active mode)

■ Flexible sector architecture

— 16 uniform sectors of 64 Kbytes each — Any combination of sectors can be erased. — Supports full chip erase — Group sector protection:

A hardware method of locking sector groups to prevent any program or erase operations within that sector group

Temporary Sector Group Unprotect allows code changes in previously locked sectors

■ Embedded Algorithms

— Embedded Erase algorithm automatically

preprograms and erases the entire chip or any combination of designated sectors

— Embedded Program algorithm automatically

writes and verifies bytes at specified addresses

■ Minimum 1,000,000 progr am/erase cycles per

sector guaranteed

■ Package options

— 40-pin TSOP — 44-pin SO

■ Compatible with JEDEC standards

— Pinout and software c ompatible with

single-power-supply Flash standard

— Superior inadvertent write protection

■ Data# Polling and toggle bits

— Provides a software method of detecting

program or erase cycle completion

■ Ready/Busy# output (RY/BY#)

— Provides a hardware method f or detecting

program or erase cycle completion

■ Erase Suspend/Erase Resume

— Suspends a sector erase oper ation to read da ta

from, or program data to, a non-erasing sector, then resumes the erase operation

■ Hardware reset p in (RESET#)

— Resets internal state machine to the read mode

Publication# 21503 Rev: C Amendment/+1 Issue Date: April 1998

PRELIMINARY

GENERAL DESCRIPTION

The Am29F080B is an 8 Mbit, 5.0 v olt-only Flash memory organized as 1,048,576 bytes. The 8 bits of data

appear on DQ0–DQ7. The Am29F080B is offered in 40-pin TSOP and 44-pin SO packages. This device is designed to be programmed in-system with the s tandard system 5.0 volt V required for program or erase operations. The device can also be programmed in standard EPROM programmer s.

This device is manufactured using AMD’s 0.35 µm process technology, and offers all the f eatures and benefits of the Am29F080, which was m anufactured using

0.5 µm process technology. The standard device offers access times of 70, 90, 120,

and 150 ns, allowing high-speed microprocessors to operate without wait states. To eliminate bus contention, the device has separate chip enable (CE#), write enable (WE#), and output enable (OE#) controls.

The device requires only a si ngle 5.0 volt power sup- ply for both read and w rite functions. Internally generated and regulated voltages are provided for the program and erase operations.

The device is entirely command set c ompatible with the JEDEC single-power-supply Flash standard. Commands are written to the command register using standard microprocessor write timings. Register contents serve as input to an internal state-machine that controls the erase and programming circuitry. Write cycles also internally latch addresses and data n eeded f o r the programming and erase operations. Reading data out of the device is similar to reading from other Flash or EPROM devices.

Device programming occurs by executing the program command sequence. This initiates the Embedded Program algorithm—an internal algorithm that automatically times the program pulse widths and verifies proper cell margin.

Device erasure occurs by executing the erase command sequence. This initiates the Embedded Erase algorithm—an inter nal algorithm that automatically preprograms the array (if it is not already progr ammed)

supply. A 12.0 volt VPP is not

before e xecutin g the erase operatio n. During erase, t he device automatically times the erase pulse widths and verifies proper cell margin.

The host system can detect whether a program or erase operation is complete by obser ving the RY/BY# pin, or by reading the DQ7 (Data# Polling) and DQ6 (toggle) status bits. After a program or erase cycle has been completed, the de vice is ready to read array data or accept another command.

The sector erase ar chitecture allows memory sectors to be erased and reprogrammed without affecting the data contents of other sectors. The device is fully erased when shipped from the factory.

Hardware data protection measures include a low

detector that automatically inhibits write opera-

tions during power transitions. The hardware sector protection feature disables both program and erase

operations in any com bination of the sectors of memory. This can be achie v ed via prog ramming equipment.

The Erase Suspend feature enables the user to put erase on hold for any period of time to read data from, or program data to, any sector that is not selected for erasure. True background erase can thus be achie ved.

The hardware RESET# pin terminates any operation in progress and resets the internal state machine to reading array data. The RESET# pin ma y be t ied to the system reset circuitry. A system reset would thus also reset the device, enabling the system microprocessor to read the boot-up firmware from the Flash memory.

The system can place the device into the standby mode. Power consumption is greatly reduced in this mode.

AMD’s Flash technology combines years of Flash memory manufacturing experience to produce the highest levels of quality, reliability and cost effectiveness. The device electrically erases all bits within a sector simultaneously via Fowler-Nordheim tunneling. The data is programmed using hot electron injection.

2 Am29F080B

PRELIMINARY

PRODUCT SELECTOR GUIDE

Family Part Number Am29F080B

= 5.0 V ± 5% -75

Speed Option

Max Access Time, ns (t Max CE# Access, ns (t Max OE# Access, ns (t

= 5.0 V ± 10% -90 -120 -150

) 70 90 120 150

ACC

) 70 90 120 150

) 40405075

Note: See the “AC Characteristics” section for more information.

BLOCK DIAGRAM

DQ0

–

DQ7

RY/BY#

RESET#

WE#

CE# OE#

A0–A19

State

Control

Command

VCC Detector

PGM Voltage

Generator

Timer

Sector Switches

Erase Voltage

Generator

STB

Chip Enable

Output Enable

Logic

Y-Decoder

X-Decoder

Address Latch

STB

Input/Output

Buffers

Data

Latch

Y-Gating

Cell Matrix

21503C-1

Am29F080B 3

CONNECTION DIAGRAMS

PRELIMINARY

A19 A18 A17 A16 A15 A14 A13 A12

CE#

RESET#

A11 A10

A9 A8 A7 A6 A5 A4

NC NC

WE#

OE#

RY/BY#

DQ7 DQ6 DQ5 DQ4

DQ3 DQ2 DQ1 DQ0

A0 A1 A2 A3

1 2 3 4 5 6 7 8 9

10 11 12 13 14 15 16 17 18 19 20

40-Pin Standard TSOP

40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21

NC NC WE# OE# RY/BY# DQ7 DQ6 DQ5 DQ4 V

DQ3 DQ2 DQ1 DQ0 A0 A1 A2 A3

21503C-2

1 2 3 4 5 6 7 8

9 10 11 12 13 14 15 16 17 18 19 20

40-Pin Reverse TSOP

40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21

A19 A18 A17 A16 A15 A14 A13 A12 CE# V

NC RESET# A11 A10 A9 A8 A7 A6 A5 A4

21503C-3

A11 A10

A9 A8 A7 A6 A5

A4 NC NC

DQ0 DQ1 DQ2 DQ3

10 11 12 13 14 15 16 17 18 19 20 21 22

2 3 4 5 6 7 8 9

RESET#

4 Am29F080B

44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23

CE# A12 A13 A14 A15 A16 A17 A18 A19 NC NC NC NC WE# OE# RY/BY# DQ7 DQ6 DQ5 DQ4 V

21503C-4

PRELIMINARY

PIN CONFIGURATION

A0–A19 = 20 Addresses DQ0–DQ7 = 8 Data Inputs/Outputs CE# = Chip Enable WE# = Write Enable OE# = Output Enable RESET# = Hardware Reset Pin, Active Low RY/BY# = Ready/Busy Output VCC = +5.0 V single power supply

(see Product Selector Guide for device speed ratings and voltage supply tolerances)

NC = Pin Not Connected Internally

= Device Ground

LOGIC SYMBOL

A0–A19

CE# OE#

WE# RESET# RY/BY#

DQ0–DQ7

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Am29F080B 5

PRELIMINARY

ORDERING INFORMATION Standard Pr od ucts

AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed by a combination of the following:

Am29F080B -75 E I

OPTIONAL PROCESSING

Blank = Standard Processing

B = Burn-In

Contact an AMD representative for more information.

TEMPERATURE RANGE

C = Commercial (0 I=Industrial (–40

PACKAGE TYPE

E = 40-Pin Thin Small Outline Package

(TSOP) Standard Pinout (TS 040)

F = 40-Pin Thin Small Outline Package

(TSOP) Reverse Pinout (TSR040)

S = 44-Pin Small Outline Package (SO 044)

SPEED OPTION

See Product Selector Guide and Valid Combinations

°C to +70°C)

°C to +85°C)

DEVICE NUMBER/DE SCR IP TIO N

Am29F080B 8 Megabit (1 M x 8-Bit) CMOS 5.0 Volt-only Sector Erase Flash Memory

5.0 V Read, Program, and Erase

Valid Combinations

Am29F080B-75 EC, EI, FC, FI, SC, SI Am29F080B-90 Am29F080B-120 Am29F080B-150

EC, EI, EE, FC, FI, FE, SC, SI, SE

Valid Combinations

Valid Combinations list configurations planned to be supported in volume for this device. Cons ult the loc al AM D sale s office to confirm availab ility of specific valid com binations and to check on newly released combinations.

6 Am29F080B

PRELIMINARY

DEVICE BUS OPERATIONS

This section describes the requirements and use of the device bus operations, which are initiated through the internal c ommand register. The command register itself does not occupy any addressable memory location. The register is composed of l atches that store the commands, along with the address and data information needed to execute the command. The contents of

Table 1. Am29F080B Device Bus Operations

Operation CE# OE# WE# RESET# A0–A19 DQ0–DQ7

the register serve as inputs to the internal state machine. The state machine outputs dictate the function of the device. The appropriate device bus operations table lists the inputs and control le vels requ ired, and the resulting output. The following subsections describe each of these operations in further detail.

Read L L X H A Write L H L H A TTL Standby H X X H X HIGH Z CMOS Standby V Output Disable L H H H X HIGH Z Hardware Reset X X X V Temporary Sector Group Unprotect (See Note) X X X V

Legend:

L = Logic Low = V

teristics for voltage levels. Note: See the sections on Sector Group Protection and Temporary Sector Unprotect for more information.

, H = Logic High = VIH, D

OUT

Requirements for Reading Array Data

To read array data from the outputs, the system must drive the CE# and OE# pins to V control and selects the device. OE# is the output control and gates array data to the output pins. WE# should remain at V

The internal state machin e is set for reading array data upon device power-up, or after a hardware reset. This ensures that no spurious alteration of the memory content occurs during the power transition. No command is necessar y in this mode to obtain array data. Standard microprocessor read cycles that assert valid addresses on the device address inputs produce valid data on the device data outputs. The device remains enable d for read access until the command register contents are altered.

See “Reading Array Data” for more information. Refer to the AC Read Operations table for timing specifications and to the Read Operations Timings diagram for the timing waveforms. I

in the DC Characteristics

CC1

table represents the active current specification for reading array data.

. CE# is the power

± 0.3 V X X V

= Data Out, DIN = Data In, AIN = Address In, X = Don’t Care. See DC Charac-

Writing Commands/Command Sequences

To write a command or command sequence (which includes programming data to the device and erasing sectors of memory), the system must drive WE# and CE# to V

An erase operation can erase one sect or, multiple sectors, or the entire de vice. The Sector Address Tables indicate the address space that each sector occupies. A “sector address” consists of the address bits required to uniquely select a sector. See the Command Definitions section for details on erasing a s ector or the entire chip, or suspending/resuming the erase operation.

After the system writes the autoselect command sequence, the device enters the autoselect mode. The system can then read autoselect codes from the internal register (which is separate from the memory array) on DQ7–DQ0. Standard read cycle timings apply in this mode. Refer to the Autoselect Mode and Autoselect Command Sequence sections for more information.

CC2

tive current specification for the write mode. The “AC Characteristics” section contains timing specification

, and OE# to VIH.

in the DC Characteristics table represents the ac-

± 0.3 V X HIGH Z

X HIGH Z

OUT

tables and timing diagrams for write operations.

Am29F080B 7

PRELIMINARY

Program and Erase Operation Status

During an erase or program operation, the system ma y check the status of the operation by reading the status

bits on DQ7–DQ0. Standard read cycle timings and I

read specifications apply. Refer to “Write Operation Status” for more infor mation, and to each AC Characteristics section in the appropriate data sheet f or t iming diagrams.

Standby Mode

When the system is not reading or writing to the device , it can place the device in the standby mode. In this mode, current consumption is great ly reduc ed, and the outputs are placed in the high impedance state, independent of the OE# input.

The device enters the CMOS standb y mode when CE# and RESET# pins are both held at V that this is a more restrict ed voltage range than V

± 0.5 V. (Note

The device enters the TTL standby mode when CE# and RESET# pins are both held at V quires standard access time (t

. The device re-

) for read access when the device is in either of these standb y modes, bef ore it is ready to read data.

The device also enters the standb y mode when the RESET# pin is driven low. Refer to the next section, “RESET#: Hardware Reset Pin”.

If the device is deselected during erasure or program ming, the device draws active current until the operation is completed.

In the DC Charac teristics tables, I

represents the

CC3

standby current specification.

RESET#: Hardware Reset Pin

The RESET# pin provides a har dware method of resetting the device to readi ng arr ay data. When the system

drives the RESET# pin low for at least a period of t the device immediately terminates any operation in progress, tristates all data output pins, and ignores all read/write attempts for the duration o f the RESET# pulse. The device also resets the inter nal state machine to reading array data. The operation that was interrupted should be reinitiated once the device is ready to accept another command sequence, to ensure data integrity.

Current is reduced for the duration of the RESET# pulse. When RESET# is held at V

, the device enters

the TTL standby mode; if RESET# is held at V

0.5 V, the device enters the CMOS standby mode. The RESET# pin may be tied to the system reset cir-

cuitry. A system reset would thus also reset the Flash memory, enabling the system to read the boot-up firmware from the Flash memory.

If RESET# is asserted during a program or erase operation, the RY/BY# pin remains a “0” (busy) until the internal reset operatio n is complete, which requires a time of t

(during Embedded Algorithms). The

READY

system can thus monitor RY/BY# to determine whether the reset operation is complete. If RESET# is asserted when a program or erase operation is not executing (RY/BY# pin is “1”), the reset operation is completed within a time of t rithms). The system can read data t SET# pin returns to V

(not during Embe dded Algo-

READY

Refer to the AC Characteristics tables for RESET# parameters and timing diagram.

Output Disable Mode

When the OE# input is at VIH, output from the device is disabled. The output pins are placed in t he high impedance state.

after the RE-

8 Am29F080B

PRELIMINARY

Table 2. Am29F080B Sector Address Table

Sector A19 A18 A17 A16 Address Range

SA0 0000 0000 00h –00FF FFh SA1 0 0 0 1 0100 00h –0 1FF FFh SA2 0 0 1 0 0200 00h –0 2FF FFh SA3 0 0 1 1 0300 00h –0 3FF FFh SA4 0 1 0 0 0400 00h –0 4FF FFh SA5 0 1 0 1 0500 00h –0 5FF FFh SA6 0 1 1 0 0600 00h –0 6FF FFh SA7 0 1 1 1 0700 00h –0 7FF FFh SA8 1 0 0 0 0800 00h –0 8FF FFh

SA9 1 0 0 1 0900 00h –0 9FF FFh SA10 1 0 1 0 0A0000h–0AFFFFh SA11 1 0 1 1 0B0000h–0BFFFFh SA12 1 1 0 0 0C0000h–0CFFFF h SA13 1 1 0 1 0D0000h–0DFFFF h SA14 1 1 1 0 0E00 00h –0 EFF FF h SA15 1 1 1 1 0F0000h–0FFFFFh

Note: All sectors are 64 Kbytes in size.

Autoselect Mode

The autoselect mode provides manufacturer and device identification, and sector protection verification,

through identifier codes output on DQ7–DQ0. This mode is primarily intended for progr amming equipment to automatically match a device to be progr ammed with its correspondi ng programming al gorithm. However, the autoselect codes can also be accessed in-system through the command register.

When using programming equipment, the autoselect mode requires V A9. Address pins A6, A1, and A0 must be as shown in Autoselect Codes (High Voltage Method) table. I n addition, when verifying sector protection, the sector ad-

(11.5 V to 12.5 V) on address pin

dress must appear on the appropriate highest order address bits. Refer to the corresponding Sector Address Tables. The Comm and Definitions table shows the remaining address bits that are don’t c are. When all necessary bits have been set as required, the programming equipment may then read the corresponding identifier code on DQ7–DQ0.

To access the autoselect codes in-system, the host system can issue the autoselect command via the command register, as shown in the C ommand Definitions table. This method does not require V

. See

“Command Definitions” for details on using the autoselect mode.

Am29F080B 9

Table 3. Am29F080B Autoselect Codes (High Voltage Method)

Description CE# OE# WE#

PRELIMINARY

A19

A12

A11

A10 A9

A7 A6

A2 A1 A0

DQ7

DQ0

Manufacturer ID: AMD L L H X X V Device ID: Am29F080B L L H X X V

Sector Group Protection Verification

Legend: L = Logic Low = VIL, H = Logic High = VIH, SGA = Sector Group Address, X = Don’t care. Note: The system may also autoselect information in-system via the command register. See Table 5.

Sector Group Protection/Unprotection

The hardware group sector protection feature disables both program and erase operations in any sector group. Each sector group consists of two adjacent sectors. Table 4 shows how the sectors are grouped, and the address range that each sector group contains. The hardware sector group unprotection feature re-enables both program and erase operations in previously protected sector groups.

Sector group protection/unprotection must be implemented using programming equipment. The procedure requires a high voltage (V

LLHSGAXV

Temporary Sector Group Unprotect

This feature allows temporary unprotection of previously protected sector groups to change data in-system. The Sector Group Unprotect mode is activated by setting the RESET# pin to V formerly protected sector g roups can be programmed or erased by selecting the sector group addresses. Once V previously protected sector groups are protected again. Figure 1 shows the algorithm, and the Temporary Sector Group Unprotect diagram

) on address pin A9 and the

shows the timing waveforms, for this feature.

XLXLL 01h

XLXLH D5h

XLXHL

is removed from the RESET# pin, all the

control pins. Details on this method are provided in a supplement, listed in publication number 19945. Contact an AMD representative to obtain a copy of the appropriate document.

START

01h (protected)

00h

(unprotected)

. During this mode,

The device is shipped with all sectors unprotected. AMD offers the option of programming and protecting sector groups at its factory prior to shipping the device

through AMD’s ExpressFlash™ Servic e. Contact an AMD representative for details.

It is possible to determine whether a sector group is protected or unprotected. See “Autoselect Mode” for details.

Table 4. Sector Group Addresses

Sector Group A19 A18 A17 Sectors

–

SGA0 0 0 0 SA0 SGA1 0 0 1 SA2 SGA2 0 1 0 SA4 SGA3 0 1 1 SA6 SGA4 1 0 0 SA8 SGA5 1 0 1 SA10 SGA6 1 1 0 SA12 SGA7 1 1 1 SA14

SA1

–

SA3

–

SA5

–

SA7

–

SA9

–

SA11

–

SA13

–

SA15

RESET# = V

(Note 1)

Perform Erase or

Program Operations

RESET# = V

Temporary Sector Group

Unprotect

Completed (Note 2)

Notes:

1. All protected sector groups unprotected.

2. All previously protected sector groups are protected once again.

21503C-6

Figure 1. Temporary Sector Group Unprotect

Operation

10 Am29F080B

PRELIMINARY

Hardware Data Protection

The command sequence requirement of unlock cycles for programming or erasing provides data protection against inadvertent writes (refer to the Command Definitions table). In addition, the following hardware data protection measures pre vent accidental eras ure or programming, which might otherwise be caus ed by spurious system level signals during V power-down transitions, or from system noise.

Low V

When V

Write Inhibit

is less than V

, the device does not ac-

LKO

cept any write cycles. This protects data during V power-up and power-down. The command register and all internal program/erase circuits are disabled, and the device resets. Subsequent writes are ignored until V is greater than V

. The system must provide the

LKO

power-up and

proper signals to the control pins to prevent unintentional writes when V

is greater than V

LKO

Write Pulse “Glitch” Protection

Noise pulses of less than 5 ns (typical) on OE#, CE# or WE# do not initiate a write cycle.

Logical Inhibit

Write cycles are inhibited by holding any one of OE# =

, CE# = VIH or WE# = VIH. To initiate a write cycle,

CE# and WE# must be a logical zero while OE# is a logical one.

Power-Up Write Inhibit

If WE# = CE# = V

and OE# = VIH during power up , the

device does not accept commands on the rising edge of WE#. The internal state mac hine is automatically reset to reading array data on power-up.

Am29F080B 11

PRELIMINARY

COMMAND DEFINITIONS

Writing specific addre ss and data commands or sequences into the command register initiates device operations. The Command Definitions table defines the valid register command sequences. Writing incorrect

address and data values or writing them in the im- proper sequence resets the device to reading array

data. All addresses are latched on the falling edge of WE# or

CE#, whichever happens later. All data is latched on the rising edge of WE# or CE#, whichever happens first. Refer to the appropriate timing diagrams in the

“AC Characteristics” section.

Reading Array Data

The device is automatically set to reading array data after device power-up. No commands are required to retrieve data. The device is also ready to read array data after comp leting an Embe dded Program or Embedded Erase algorithm.

After the device accepts an Er ase Suspend command, the device enters the Erase Suspend m ode. The system can read array data using the standard read timings, except that if it reads at an address within erasesuspended sectors, the device outputs status data. After completing a programming operation in the Erase Suspend mode, the system may once agai n read arra y data with the same ex ception. See “Erase Suspend/ Erase Resume Commands” for more information on this mode.

must

The system able the dev ice f or reading arra y data if DQ5 goes high, or while in the autoselect mode. See the “Reset Command” section, next.

See also “Requirements for Reading Arr a y Data” in the “Device Bus Operations” section for more information. The Read Operations table provides the read parameters, and Read Operation Tim ings diagram shows the timing diagram.

issue the reset command to re-en-

Reset Command

Writing the reset command to the devi ce resets the device to reading array data. Address bits are don’t care for this command.

The reset command may be written between the sequence cycles in an erase command sequence before erasing begins. This resets the device to reading array data. Once erasure begins, however, the device ignores reset commands until the operation is complete.

The reset command may be written between the sequence cycles in a program command sequence before programming begins. This resets the device to reading array data (also applies to programming in Erase Suspend mode). Once programming begins,

however, the device ignores reset commands until the operation is complete.

The reset command may be written between the sequence cycles in an autoselect command sequence. Once in the autoselect mode, t he reset c ommand be written to return to reading array data (also applies to autoselect during Erase Suspend).

If DQ5 goes high during a program or erase operation, writing the reset command returns the device to reading array data (also applies during Erase Suspend).

must

Autoselect Command Sequence

The autoselect c ommand sequenc e allows the host system to access the manufacturer and devices codes , and determine whether or not a sector is protected. The Command Definitions table shows the address and data requirements. This method is an a lternative to that shown in the Autoselect Codes (High Voltage Method) table, which is in tended for PROM programmers and requires V

The autoselect command sequence is initiated by writing two unlock cycles, followed by the autoselect command. The device then en ters the autoselect mode, and the system may read at any address any number of times, without initiating another command sequence.

A read cycle at address XX00h retrieves the manufacturer code. A read cycle at address XX01h returns the device code. A read cycle containing a sector address (SA) and the address 02h in returns 01h if that sector is protected, or 00h if it is unprotected. Refer to the Sector Ad dr e ss ta bles for valid sector addres s es.

The system must write the reset command to exit the autoselect mode and return to reading array data.

on address bit A9.

Byte Program Command Sequence

Programming is a four-bus-cycle operation. The program command sequence is initiated by writing two unlock write cycles, followed by the program set-up command. The program address and data are wr itten next, which in turn initiate the Embedded Program al-

not

gorithm. The system is controls or timings. The device automatically provides internally generated program pulses and v erify the programmed cell margin. The Command Definitions take shows the address and data requirements for the byte program command sequence.

When the Embedded Program algorithm is complete, the device then returns to reading array data and addresses are no longer latched. The system can determine the status of the program operation b y using DQ7, DQ6, or RY/BY#. See “Write Operation Status” for information on these status bits.

required to provide further

12 Am29F080B

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