AMD Advanced Micro Devices AM29F017B-90FIB, AM29F017B-90FI, AM29F017B-90FEB, AM29F017B-90FE, AM29F017B-90FCB Datasheet
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PRELIMINARY
Am29F017B
16 Megabit (2 M x 8-Bit)
CMOS 5.0 Volt-only, Uniform Sector Flash Memory
DISTINCTIVE CHARACTERISTICS
■ Optimized for memory card applications
— Backwards-compatible with the Am29F016C
■ 5.0 V ± 10%, single power supply operation
— Minimizes system level power requirements
■ Manufactured on 0.35 µm process technology
■ High performance
— Access times as fast as 70 ns
■ Low power consumption
— 25 mA typical active read current
— 30 mA typical program/erase current
—1 µA typical standby current (standard access
time to active mode)
■ Flexible sector architecture
— 32 uniform sectors of 64 Kbytes each
— Any combination of sectors can be erased.
— Supports full chip erase
— Group sector protection:
A hardware method of locking sector groups to
prevent any program or erase operations within
that sector group
Temporary Sector Group Unprotect allows code
changes in previously locked sectors
■ Embedded Algorithms
— Embedded Erase algorithm automatically
preprograms and erases the entire chip or any
combination of designated sectors
— Embedded Program algorithm automatically
writes and verifies bytes at specified addresses
■ Minimum 1,000,000 progr am/erase cycles per
sector guaranteed
■ Package options
— 48-pin TSOP
■ Compatible with JEDEC standards
— Pinout and software compatible with
single-power-supply Flash standard
— Superior inadvertent write protection
■ Data# Polling and toggle bits
— Provides a software method of detecting
program or erase cycle completion
■ Ready/Busy# output (RY/BY#)
— Provides a hardware method for detecting
program or erase cycle completion
■ Erase Suspend/Erase Resume
— Suspends a sector erase oper ation to read da ta
from, or program data to, a non-erasing sector,
then resumes the erase operation
■ Hardware reset p in (RESET#)
— Resets internal state machine to the read mode
Publication# 21195 Rev: B Amendment/+2
Issue Date: April 1998
PRELIMINARY
GENERAL DESCRIPTION
The Am29F017B is a 16 Mbit, 5.0 v olt-only Flash memory organized as 2,097,152 bytes. The 8 bits of data
appear on DQ0–DQ7. The Am29F017B is offered in a
48-pin TSOP package. This d evice is designed to be
programmed in-system with the standard system 5.0
volt V
gram or erase operations. The device can also be programmed in standard EPROM programmers.
This device is manufactured using AMD’s 0.35
process technology, and offers all the f eatures and benefits of the Am29F016C, which was manufactured
using 0.5
The standard device of fers access t imes of 70, 90, 120,
and 150 ns, allowing high-speed microprocessors to
operate without wait states. To elim inate bus conten tion, the device has separate c hip enable (CE#), write
enable (WE#), and output enable (OE#) controls.
The device requires only a si ngle 5.0 volt power sup-
ply for both read and w rite functions. Internally generated and regulated voltages are provided for the
program and erase operations.
The device is entirely command set c ompatible with the
JEDEC single-power-supply Flash standard. Commands are written to the command register using standard microprocessor write timings. Register contents
serve as input to an internal state-machine that controls the erase and programming circuitry. Write cycles
also internally latch addresses and data n eeded f o r the
programming and erase operations. Reading data out
of the device is similar to reading from other Flash or
EPROM devices.
Device programming occurs by executing the program
command sequence. This initiates the Embedded
Program algorithm—an internal algorithm that automatically times the program pulse widths and verifies
proper cell margin.
Device erasure occurs by executing the erase command sequence. This initiates the Embedded Erase
algorithm—an inter nal algorithm that automatically
preprograms the array (if it is not already progr ammed)
supply. A 12.0 volt VPP is not required for pro-
CC
µm process technology.
µm
before e xecutin g the erase operatio n. During erase, t he
device automatically times the erase pulse widths and
verifies proper cell margin.
The host system can detect whether a program or
erase operation is complete by obser ving the RY/BY#
pin, or by reading the DQ7 (Data# Polling) and DQ6
(toggle) status bits. After a program or erase cycle has
been completed, the de vice is ready to read array data
or accept another command.
The sector erase ar chitecture allows memory sectors
to be erased and reprogrammed without affecting the
data contents of other sectors. The device is fully
erased when shipped from the factory.
Hardware data protection measures include a low
detector that automatically inhibits write opera-
V
CC
tions during power transitions. The hardware sector
protection feature disables both program and erase
operations in any com bination of the sectors of memory. This can be achie v ed via prog ramming equipment.
The Erase Suspend feature enables the user to put
erase on hold for any period of time to read data from,
or program data to, any sector that is not selected for
erasure. True background erase can thus be achie ved.
The hardware RESET# pin terminates any operation
in progress and resets the internal state machine to
reading array data. The RESET# pin ma y be t ied to the
system reset circuitry. A system reset would thus also
reset the device, enabling the system microprocessor
to read the boot-up firmware from the Flash memory.
The system can place the device into the standby
mode. Power consumption is greatly reduced in
this mode.
AMD’s Flash technology combines years of Flash
memory manufacturing experience to produce the
highest levels of quality, reliability and cost
effectiveness. The device electrically erases all
bits within a sector simultaneously via
Fowler-Nordheim tunneling. The data is
programmed using hot electron injection.
2 Am29F017B
PRELIMINARY
PRODUCT SELECTOR GUIDE
Family Part Number Am29F017B
Speed Options (V
Max Access Time (ns) 70 90 120 150
CE# Access (ns) 70 90 120 150
OE# Access (ns) 40 40 50 75
= 5.0 V ± 10% -70 -90 -120 -150
CC
Note: See the AC Characteristics section for more information.
BLOCK DIAGRAM
–
DQ7
DQ0
V
CC
V
SS
RY/BY#
RESET#
WE#
CE#
OE#
State
Control
Command
Register
PGM Voltage
Generator
Sector Switches
Erase Voltage
Generator
Chip Enable
Output Enable
Logic
STB
Input/Output
Buffers
Data
Latch
A0–A20
VCC Detector
Timer
STB
Address Latch
Y-Decoder
X-Decoder
Y-Gating
Cell Matrix
21195B-1
Am29F017B 3
CONNECTION DIAGRAMS
PRELIMINARY
NC
NC
A19
A18
A17
A16
A15
A14
A13
A12
CE#
V
NC
RESET#
A11
A10
A9
A8
A7
A6
A5
A4
NC
NC
NC
NC
A20
NC
WE#
OE#
RY/BY#
DQ7
DQ6
DQ5
DQ4
V
CC
V
SS
V
SS
DQ3
DQ2
DQ1
DQ0
A0
A1
A2
A3
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
CC
13
14
15
16
17
18
19
20
21
22
48-Pin Standard TSOP
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
NC
NC
A20
NC
WE#
OE#
RY/BY#
DQ7
DQ6
DQ5
DQ4
V
CC
V
SS
V
SS
DQ3
DQ2
DQ1
DQ0
A0
A1
A2
A3
NC
NC
21195B-2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
48-Pin Reverse TSOP
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
NC
NC
A19
A18
A17
A16
A15
A14
A13
A12
CE#
V
CC
NC
RESET#
A11
A10
A9
A8
A7
A6
A5
A4
NC
NC
21195B-3
4 Am29F017B
PRELIMINARY
PIN CONFIGURATION
A0–A20 = 21 Addresses
DQ0–DQ7 = 8 Data Inputs/Outputs
CE# = Chip Enable
WE# = Write Enable
OE# = Output Enable
RESET# = Hardware Reset Pin, Active Low
RY/BY# = Ready/Busy Output
VCC = +5.0 V single power supply
(see Product Selector Guide for
device speed ratings and voltage
supply tolerances)
V
SS
NC = Pin Not Connected Internally
= Device Ground
LOGIC SYMBOL
21
A0–A20
CE#
OE#
WE#
RESET# RY/BY#
8
DQ0–DQ7
21195B-4
Am29F017B 5
PRELIMINARY
ORDERING INFORMATION
Standard Pr od ucts
AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is
formed by a combination of the following:
Am29F017B -70 E I
OPTIONAL PROCESSING
Blank = Standard Processing
B = Burn-in
(Contact an AMD representative for more information)
TEMPERATURE RANGE
C=Commercial (0°C to +70°C)
I = Industrial (–40 °C to +85 °C)
E = Extended (–55°C to +125°C)
PACKAGE TYPE
E = 48-Pin Thin Small Outline Package
(TSOP) Standard Pinout (TS 048)
F = 48-Pin Thin Small Outline Package
(TSOP) Reverse Pinout (TSR048)
SPEED OPTION
See Product Selector Guide and Valid Combinations
Am29F017B-70
Am29F017B-90
Am29F017B-120
Am29F017B-150
DEVICE NUMBER/DE SCR IP TIO N
Am29F017B
16 Megabit (2 M x 8-Bit) CMOS 5.0 Volt-only Sec tor Erase Fla sh Mem or y
5.0 V Read, Program, and Erase
Valid Combinations
EC, EI, EE, FC, FI, FE
Valid Combinations
Valid Combinations list configurations planned to be supported in volume for this device. Cons ult the loc al AM D sale s office to confirm availab ility of specific valid com binations and
to check on newly released combinations.
6 Am29F017B
PRELIMINARY
DEVICE BUS OPERATIONS
This section describes the requirements and use of the
device bus operations, which are initiated through the
internal c ommand register. The command register itself does not occupy any addressable memory location. The register is composed of l atches that store the
commands, along with the address and data information needed to execute the command. The contents of
Table 1. Am29F017B Device Bus Operations
Operation CE# OE# WE# RESET# A0–A20 DQ0–DQ7
the register serve as inputs to the internal state machine. The state machine outputs dictate the function of
the device. The appropriate device bus operations
table lists the inputs and control le vels requ ired, and the
resulting output. The following subsections describe
each of these operations in further detail.
Read L L H H A
Write L H L H A
CMOS Standby VCC ± 0.5 V X X VCC ± 0.5 V X High-Z
TTL Standby H X X H X High-Z
Output Disable L H H H X High-Z
Hardware Reset X X X L X High-Z
Temporary Sector Unprotect
(See Note)
Legend:
L = Logic Low = V
Note:
See the sections on Sector Protection and Temporary Sector Unprotect for more information.
, H = Logic High = VIH, VID = 12.0 ± 0.5 V, X = Don’t Care, DIN = Data In, D
IL
Requirements for Reading Array Data
To read array data from the outputs, the system must
drive the CE# and OE# pins to V
control and selects the device. OE# is the output control
and gates array data to the output pins. WE# should remain at V
.
IH
The internal state machin e is set for reading array
data upon device power-up, or after a hardware reset.
This ensures that no spurious alteration of the memory content occurs during the power transition. No
command is necessar y in this mode to obtain array
data. Standard microprocessor read cycles that assert valid addresses on the device address inputs
produce valid data on the device data outputs. The
device remains enable d for read access until the
command register contents are altered.
See “Reading Array Data” for more information. Refer
to the AC Read Operations table for timing specifications and to the Read Operations Timings diagram for
the timing waveforms. I
in the DC Characteristics
CC1
table represents the active current specification for
reading array data.
. CE# is the power
IL
XXX V
ID
Writing Commands/Command Sequences
To write a command or command sequence (which includes programming data to the device and erasing
sectors of memory), the system must drive WE# and
CE# to V
An erase operation can erase one sect or, multiple sectors, or the entire de vice. The Sector Address Tabl es indicate the address space that each sector occupies. A
“sector address” consists of the address bits required
to uniquely select a sector. See the “Command Definitions” section for details on erasing a sector or the entire chip, or suspending/resuming the erase operation.
After the system writes the autoselect command sequence, the device enters the autoselect mode. The
system can then read autoselect codes from the internal register (which is separate from the memory array)
on DQ7–DQ0. Standard read cycle timings apply in this
mode. Refer to the “Autoselect Mode” and “Autoselect
Command Sequence” sections for more information.
I
CC2
tive current specification for the write mode. The “AC
Characteristics” section contains timing specification
, and OE# to VIH.
IL
in the DC Characteristics table represents the ac-
OUT
IN
IN
A
IN
= Data Out, AIN = Address In
D
OUT
D
D
IN
IN
tables and timing diagrams for write operations.
Am29F017B 7
PRELIMINARY
Program and Erase Operation Status
During an erase or program operation, the system ma y
check the status of the operation by reading the status
bits on DQ7–DQ0. Standard read cycle timings and I
CC
read specifications apply. Refer to “Write Operation
Status” for more infor mation, and to each AC Characteristics section for timing diagrams.
Standby Mode
When the system is not reading or writing to the device ,
it can place the device in the standby mode. In this
mode, current consumption is great ly reduc ed, and the
outputs are placed in the high impedance state, independent of the OE# input.
The device enters the CMOS standb y mode when CE#
and RESET# pins are both held at V
that this is a more restrict ed voltage range than V
± 0.5 V. (Note
CC
IH
The device enters the TTL standby mode when CE#
and RESET# pins are both held at V
. The device re-
IH
quires standard access time (tCE) for read access when
the device is in either of these standb y modes, bef ore it
is ready to read data.
The device also enters the standb y mode when the RESET# pin is driven low. Refer to the next section, “RESET#: Hardware Reset Pin”.
If the device is deselected during erasure or program ming, the device draws active current until the
operation is completed.
In the DC Charac teristics tables, I
represents the
CC3
standby current specification.
RESET#: Hardware Reset Pin
The RESET# pin provides a har dware method of resetting the device to readi ng arr ay data. When the system
drives the RESET# pin low for at least a period of t
the device immediately terminates any operation in
progress, tristates all data output pins, and ignores all
read/write attempts for the duration o f the RESET#
pulse. The device also resets the inter nal state machine to reading array data. The operation that was interrupted should be reinitiated once the device is ready
to accept another command sequence, to ensure data
integrity.
Current is reduced for the duration of the RESET#
pulse. When RESET# is held at V
, the device enters
IL
the TTL standby mode; if RESET# is held at V
0.5 V, the device enters the CMOS standby mode.
The RESET# pin may be tied to the system reset cir-
cuitry. A system reset would thus also reset the Flash
memory, enabling the system to read the boot-up firmware from the Flash memory.
.)
If RESET# is asserted during a program or erase operation, the RY/BY# pin remains a “0” (busy) until the internal reset operatio n is complete, which requires a
time of t
(during Embedded Algorithms). The
READY
system can thus monitor RY/BY# to determine whether
the reset operation is complete. If RESET# is asserted
when a program or erase operation is not executing
(RY/BY# pin is “1”), the reset operation is completed
within a time of t
rithms). The system can read data t
SET# pin returns to V
(not during Embe dded Algo-
READY
.
IH
RH
Refer to the AC Characteristics tables for RESET# parameters and timing diagram.
Output Disable Mode
When the OE# input is at VIH, output from the device is
disabled. The output pins are placed in t he high impedance state.
RP
SS
after the RE-
,
±
8 Am29F017B
PRELIMINARY
Table 2. Sector Address Table
Sector A20 A19 A18 A17 A16 Address Range
SA0 0 0 0 0 0 000000h-00FFFFh
SA1 0 0 0 0 1 010000h-01FFFFh
SA2 0 0 0 1 0 020000h-02FFFFh
SA3 0 0 0 1 1 030000h-03FFFFh
SA4 0 0 1 0 0 040000h-04FFFFh
SA5 0 0 1 0 1 050000h-05FFFFh
SA6 0 0 1 1 0 060000h-06FFFFh
SA7 0 0 1 1 1 070000h-07FFFFh
SA8 0 1 0 0 0 080000h-08FFFFh
SA9 0 1 0 0 1 090000h-09FFFFh
SA10 0 1 0 1 0 0A0000h-0AFFFFh
SA11 0 1 0 1 1 0B0000h-0BFFFFh
SA12 0 1 1 0 0 0C0000h-0CFFFFh
SA13 0 1 1 0 1 0D0000h-0DFFFFh
SA14 0 1 1 1 0 0E0000h-0EFFFFh
SA15 0 1 1 1 1 0F0000h-0FFFFFh
SA16 1 0 0 0 0 100000h-10FFFFh
SA17 1 0 0 0 1 110000h-11FFFFh
SA18 1 0 0 1 0 120000h-12FFFFh
SA19 1 0 0 1 1 130000h-13FFFFh
SA20 1 0 1 0 0 140000h-14FFFFh
SA21 1 0 1 0 1 150000h-15FFFFh
SA22 1 0 1 1 0 160000h-16FFFFh
SA23 1 0 1 1 1 170000h-17FFFFh
SA24 1 1 0 0 0 180000h-18FFFFh
SA25 1 1 0 0 1 190000h-19FFFFh
SA26 1 1 0 1 0 1A0000h-1AFFFFh
SA27 1 1 0 1 1 1B0000h-1BFFFFh
SA28 1 1 1 0 0 1C0000h-1CFFFFh
SA29 1 1 1 0 1 1D0000h-1DFFFFh
SA30 1 1 1 1 0 1E0000h-1EFFFFh
SA31 1 1 1 1 1 1F0000h-1FFFFFh
Note: All sectors are 64 Kbytes in size.
Am29F017B 9
PRELIMINARY
Autoselect Mode
The autoselect mode provides manufacturer and device identification, and sector protection verification,
through identifier codes output on DQ7–DQ0. This
mode is primarily intended for progr amming equipment
to automatically match a device to be progr ammed with
its correspondi ng programming al gorithm. However,
the autoselect codes can also be accessed in-system
through the command register.
When using programming equipment, the autoselect
mode requires V
(11.5 V to 12.5 V) on address pin
ID
A9. Address pins A6, A1, and A0 must be as shown in
Autoselect Codes (High Voltage Method) table. I n addition, when verifying sector protection, the sector ad-
Table 3. Am29F017B Autoselect Codes (High Voltage Method)
Description CE# OE# WE# A20-A18 A17-A10 A9 A8-A7 A6 A5-A2 A1 A0 DQ7-DQ0
dress must appear on the appropriate highest order
address bits. Refer to the corresponding Sector Address Tables. The Comm and Definitions table shows
the remaining address bits that are don’t c are. When all
necessary bits have been set as required, the programming equipment may then read the corresponding
identifier code on DQ7–DQ0.
To access the autoselect codes in-system, the host
system can issue the autoselect command via the
command register, as shown in the C ommand Definitions table. This method does not require V
“Command Definitions” for details on using the autoselect mode.
. See
ID
Manufacturer ID:
AMD
Device ID:
Am29F017B
Sector Group
Protection
Ve r ific atio n
L = Logic Low = VIL, H = Logic High = VIH, SA = Sector Address, X = Don’t care.
LLH X X V
LLH X X VIDXVILXVILV
Sector
LLH
Group
Address
XVIDXVILXVIHV
Sector Group Protection/Unprotection
The hardware sector group protection feature disables both program and erase operations in any sector. Each sector group consists o f four ad jacent
sectors. Table 4 shows how the sectors are goruped,
and the address range that each sector group contains. The hardware sector group unprotection feature re-enables both program and erase operations in
previously protected sectors.
Sector group protection/unprotection must be implemented using programming equipment. The procedure
requires a high voltage (V
control pins. Details on this method are provided in a
supplement, publication number 21544. Contact an
AMD representative to obtain a cop y of the appropriate
document.
The device is shipped with all sector grou ps unprotected. AMD offers t he optio n of prog r amming a nd protecting sectors at its factory prior to shipping the device
through AMD’s ExpressFlash™ Servic e. Contact an
AMD representative for details.
It is possible to determine whether a sector group is
protected or unprotected. See
details.
) on address pin A9 and the
ID
“Autoselect Mode” for
XVILXVILV
ID
Table 4. Sector Group Addresses
Sector
Group A20 A19 A18 Sectors
SGA0 0 0 0 SA0
SGA1 0 0 1 SA4
SGA2 0 1 0 SA8
SGA3 0 1 1 SA12
SGA4 1 0 0 SA16
SGA5 1 0 1 SA20
SGA6 1 1 0 SA24
SGA7 1 1 1 SA28
Temporary Sector Group Unprotect
This feature allows temporary unprotection of previously protected sector s groups t o change dat a in-system. The Sector Group Unprotect mode is activated
by setting the RESET# pin to V
formerly protected sector g roups can be programmed
or erased by selecting the sector group addresses.
Once V
previously protected sector groups are
protected again. Figure 1 shows the algorithm, and
the Temporary Sector/Sector Group Unprotect dia-
is removed from the RESET# pin, all the
ID
gram shows the timing waveforms, for this feature.
IL
IH
IL
01h
3Dh
01h (protected)
00h (unprotected)
–
–
–
–
–
–
–
–
. During this mode,
ID
SA3
SA7
SA11
SA15
SA19
SA23
SA27
SA31
10 Am29F017B
PRELIMINARY
START
RESET# = V
(Note 1)
Perform Erase or
Program Operations
RESET# = V
Temporary Sector Group
Unprotect
Completed (Note 2)
Notes:
1. All protected sector groups unprotected.
2. All previously protected sector groups are protected
once again.
ID
IH
21195B-5
Figure 1. Temporary Sector Group Unprotect
Operation
Hardware Data Protection
The command sequence requirement of unlock cycles
for programming or erasing provides data protection
against inadvertent writes (refer to the Command Definitions table). In addition, the following hardware data
protection measures pre vent a ccidental eras ure or programming, which might otherwise be caused by spurious system level signals during V
power-down transitions, or from system noise.
Low V
When V
Write Inhibit
CC
is less than V
CC
, the device does not ac-
LKO
cept any write cycles. This protects data during V
power-up and power-down. The command register and
all internal program/erase circuits are disabled, and the
device resets. Subsequent writes are ignored until V
is greater than V
. The system must provide the
LKO
proper signals to the control pins to prevent unintentional writes when V
is greater than V
CC
Write Pulse “Glitch” Protection
Noise pulses of less than 5 ns (typical) on OE#, CE# or
WE# do not initiate a write cycle.
Logical Inhibit
Write cycles are inhibited by holding any one of OE# =
, CE# = VIH or WE# = VIH. To initiate a write cycle,
V
IL
CE# and WE# must be a logical zero while OE# is a
logical one.
power-up and
CC
.
LKO
CC
CC
Power-Up Write Inhibit
If WE# = CE# = V
and OE# = VIH during power up , the
IL
device does not accept commands on the rising edge
of WE#. The internal state mac hine is automatically
reset to reading array data on power-up.
Am29F017B 11
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